Ultra-wideband signal acquisition and processing equipment
By adopting a modular design and a multi-interface redundant transmission scheme, the channel scalability and real-time transmission problems of ultra-wideband signal acquisition and processing equipment are solved, enabling flexible configuration and efficient data transmission, and improving the portability and synchronization accuracy of the equipment.
Patent Information
- Application Number
- CN202520365278.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-04
- Publication Date
- 2026-01-13
- Estimated Expiration
- 2035-03-04
AI Technical Summary
Existing ultra-wideband signal acquisition and processing equipment uses a hardware architecture with a fixed number of channels, making it difficult to flexibly configure the number of input channels through modularization. This results in the need for multiple devices to be cascaded in multi-target collaborative monitoring scenarios, increasing system complexity. At the same time, a single data transmission interface is insufficient to meet the real-time transmission requirements of ultra-wideband signals.
The ultra-wideband signal acquisition and processing equipment adopts a modular design. The number of input channels can be flexibly configured through the FMC interface on the FPGA data acquisition and processing board, and real-time transmission can be achieved through multiple interfaces such as Gigabit Ethernet, 10 Gigabit Ethernet, and USB 3.0. It supports modular expansion and efficient data transmission.
It enables flexible configuration of the number of channels and real-time transmission, reduces system complexity, improves synchronization accuracy, and features miniaturized and portable equipment, meeting the needs of multi-target collaborative monitoring.
Smart Images
Figure CN223798237U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to electronic equipment technical field, specifically, it is a kind of ultra-wideband signal acquisition processing equipment. BACKGROUND
[0002] As the key hardware carrier in radar detection, radio monitoring, high-speed communication and other fields, the performance of ultra-wideband signal acquisition processing equipment directly determines the system's perception and analysis ability to transient signals and wideband complex electromagnetic environment. With the increasing demand for signal sampling rate, real-time processing capability and multi-channel synchronous acquisition in modern electronic systems, the traditional acquisition equipment gradually exposes the following technical bottlenecks in architecture design:
[0003] 1. Conflict between channel expansion and sampling bandwidth: Existing equipment mostly uses a fixed number of channel hardware architecture, which is difficult to flexibly configure the number of input channels through modularization. When facing multi-target cooperative monitoring scenarios, multiple devices are often cascaded, resulting in a dramatic increase in system complexity and a decrease in synchronization accuracy.
[0004] 2. Interface compatibility and real-time transmission limitations: Existing equipment generally uses a single data transmission interface (such as USB3.0 or Gigabit Ethernet), which is difficult to meet the real-time transmission needs of ultra-wideband signals. INVENTION CONTENT
[0005] The utility model aims at providing an ultra-wideband signal acquisition processing equipment to solve the problem that existing ultra-wideband signal acquisition processing equipment mostly uses a fixed number of channel hardware architecture, which is difficult to flexibly configure the number of input channels through modularization. When facing multi-target cooperative monitoring scenarios, multiple devices are often cascaded, resulting in a dramatic increase in system complexity and a decrease in synchronization accuracy. Further, the problem that existing ultra-wideband signal acquisition processing equipment generally uses a single data transmission interface (such as USB3.0 or Gigabit Ethernet), which is difficult to meet the real-time transmission needs of ultra-wideband signals.
[0006] The utility model solves the above problems through the following technical solutions:
[0007] An ultra-wideband signal acquisition processing equipment includes a case, a partition is arranged in the case, a general-purpose motherboard and an FPGA data acquisition processing board are fixedly connected on the partition, the general-purpose motherboard and the FPGA data acquisition processing board are electrically connected through a first communication interface, a Gigabit Ethernet interface, a Gigabit Ethernet interface, a USB3.0 interface and a VGA interface are arranged on the general-purpose motherboard, the general-purpose motherboard is further provided with a second communication interface for electrically connecting a system disk, a data disk and a CPU module; a time service module, an RS422 interface, a debugging interface and a plurality of FMC interfaces for electrically connecting data acquisition daughter cards are arranged on the FPGA data acquisition processing board, and the data acquisition daughter cards are electrically connected with radio frequency modules.
[0008] The utility model discloses a plurality of FMC interfaces set on the FPGA data acquisition processing board can select the quantity of data acquisition daughter card connected according to actual conditions, thereby the number of input channels is flexibly configured through modularization, and the channel expansibility problem is solved through data acquisition daughter card plugging.
[0009] Adopt gigabit network interface, terabit network interface, USB3.0 interface and VGA interface, first communication interface, second communication interface and various interfaces, solve the problem that the single data transmission interface (such as USB3.0 or gigabit ethernet) is generally used in ultra-wideband signal acquisition processing equipment, and it is difficult to meet the real-time transmission demand of ultra-wideband signal.
[0010] Further, the first communication interface is an IPEX interface.
[0011] Further, the second communication interface includes a COMe interface, an mSATA interface and an M.2 interface, the COMe interface is used for communication connection between the general motherboard and the CPU module, the mSATA interface is used for communication connection between the general motherboard and the system disk, and the M.2 interface is used for communication connection between the general motherboard and the data disk.
[0012] Further, the gigabit network interface has three.
[0013] Further, the USB3.0 interface has two.
[0014] Further, the FMC interface has three, which is used for connection between the FPGA data acquisition processing board and three data acquisition daughter cards, realizes clock, signal and power interconnection between the FPGA data acquisition processing board and the data acquisition daughter card.
[0015] Further, the gigabit network interface is extended to the panel of the case through an RJ45 connector, realizing interconnection between the equipment and the external network.
[0016] The terabit network interface is extended to the panel of the case through an LC flange optical fiber interface, which is used for data interaction between the general motherboard and the external network.
[0017] The USB3.0 interface is extended to the panel of the case through a Type-A connector, which is used for connecting a mouse, a keyboard or a U disk and other external devices.
[0018] The VGA interface extends to the panel of the case through a D-sub 15 connector and is used for connecting an external display;
[0019] The RS422 interface extends to the panel of the case through a D-sub 9 connector and is used for low-speed signal communication;
[0020] The debugging interface extends to the panel of the case through an H30J connector and extends to the front panel through a J30J connector and is used for debugging the FPGA on the FPGA data acquisition and processing board.
[0021] The timing module extends to the panel of the case through an SMA connector and is used for providing accurate time synchronization.
[0022] Preferably, the interfaces and the timing module all extend to the same panel of the case, for example, the front panel of the case.
[0023] Preferably, the general mainboard and the FPGA data acquisition and processing board are designed with PCIe interfaces (extending through I-PEX connectors) and are interconnected through I-PEX connecting lines.
[0024] Further, the general mainboard and the FPGA data acquisition and processing board are fixed on the partition plate through screws.
[0025] Further, the radio frequency module is provided with two input interfaces and two output interfaces, the input interfaces extend to the panel of the case through SMA connectors, and the output interfaces are electrically connected with the data acquisition sub-cards.
[0026] Compared with the prior art, the utility model has the following advantages and beneficial effects:
[0027] (1) The utility model can access various radio frequency modules and data acquisition sub-cards flexibly, has strong customization, and solves the channel expansibility problem.
[0028] (2) The utility model can control the corresponding radio frequency module and acquisition sub-card to work independently, thereby realizing the control of the whole machine power consumption.
[0029] (3) The utility model can provide ultra-wideband, multi-channel radio frequency input interfaces, and the number of radio frequency input channels has strong tailoring;
[0030] (4) The utility model discloses a modularized equipment, which can quickly build a stable ultra-wideband signal acquisition platform. The utility model realizes miniaturization and portability of the whole machine under the premise of ensuring stable performance. The utility model solves the problem of the prior art, i.e., in order to realize wideband coverage, the prior art usually adopts a multi-chip parallel architecture, which greatly increases the power consumption of the equipment and requires a forced cooling system, thereby increasing the volume and seriously restricting the field mobile deployment capability and causing an imbalance between power consumption and portability. BRIEF DESCRIPTION OF DRAWINGS
[0031] Figure 1 Fig. 1 is a schematic diagram of the internal structure of an ultra-wideband signal acquisition and processing device according to the utility model.
[0032] Figure 2 Fig. 2 is a schematic diagram of the front panel of an ultra-wideband signal acquisition and processing device according to the utility model.
[0033] In the drawings, 1 is a case; 2 is a partition; 3 is a general-purpose mainboard; 4 is an FPGA data acquisition and processing board; 5 is a data acquisition daughter card; 6 is a radio frequency module; 7 is a system disk; 8 is a data disk; 9 is a CPU module; 10 is a power management module; 11 is a clock management circuit; 31 is a first IPEX interface; 32 is an mSATA interface; 33 is an M.2 interface; 34 is a COMe interface; 35 is a gigabit network port; 36 is a terabit network port; 37 is a USB3.0 interface; 38 is a VGA interface; 41 is a second IPEX interface; 42 is a time service module interface; 43 is a debugging interface; 44 is an RS422 interface; 51 is a first SMA interface; 52 is an FMC interface; 61 is a second SMA interface; and 62 is a third SMA interface. DETAILED DESCRIPTION
[0034] The utility model will be further described in detail below in combination with examples, but the implementation manner of the utility model is not limited thereto.
[0035] Example:
[0036] In combination with the drawings, Figure 1 and Figure 2 shown, an ultra-wideband signal acquisition and processing device includes a case 1, three radio frequency modules 6, three data acquisition daughter cards 5, an FPGA data acquisition and processing board 4, a general-purpose mainboard 3, a CPU module 9, a system disk 7, and a data disk 8. The utility model supports a 3-way gigabit network port 35, a 1-way terabit network port 36, a 2-way USB3.0 interface 37, a VGA interface 38, an RS422 interface 44, a time service module interface 42 (an SMA interface), and a debugging interface 43. The utility model has ultra-wideband multi-channel data acquisition and processing capability and supports clock management and power low-power consumption management of the whole machine.
[0037] The chassis 1 adopts a standard 19-inch 2U rack design and has a structure with reinforcement features to ensure high stability and durability. A partition 2 is designed in the middle of the chassis 1, and the general motherboard 3, the FPGA data acquisition processing board 4 and the radio frequency module 6 are all fixed on the partition 2 in the chassis 1 by screws.
[0038] The three radio frequency modules 6 have the same function and performance, each module contains two input interfaces, i.e., the second SMA interface 61, and two output interfaces, i.e., the third SMA interface 62, wherein the second SMA interface 61 is connected to the front panel, and the third SMA interface 62 is connected to the data acquisition sub-card 5.
[0039] The three data acquisition sub-cards 5 have the same function and performance, each sub-card contains two input interfaces, i.e., the first SMA interface 51, which is connected to the radio frequency module 6 through the first SMA interface 51; each sub-card is designed with an FMC interface 52, which is interconnected with the FPGA data acquisition processing board 4 through an FMC connector.
[0040] The FPGA data acquisition processing board 4 is designed with a high-performance FPGA logic chip, three FMC connectors at the front end, six second IPEX interfaces 41 at the rear end, which are interconnected with the general motherboard 3 through an I-PEX connector, and a timing module interface 42, an RS422 interface 44 and a debugging interface 43. The functions of the FPGA logic chip on the FPGA data acquisition processing board 4 are as follows:
[0041] 1) The FPGA logic chip is interconnected with the three data acquisition sub-cards 5 through the FMC connector, thereby realizing the communication of high-speed signals and low-speed signals of the two parts;
[0042] 2) The FPGA logic chip processes the high-speed signals transmitted by the data acquisition sub-card 5;
[0043] 3) The FPGA logic chip transmits the processed data to the general motherboard 3 through the I-PEX connector.
[0044] The general motherboard 3 is designed with six first IPEX interfaces 31 at the front end, an M.2 interface 33 and an mSATA interface 32 at the right end, a COMe interface 34 in the middle, and further designed with two-way USB3.0 interface 37, three-way gigabit network interface 35, one-way terabit network interface 36 and VGA interface 38. The specific functions of the general motherboard 3 are as follows:
[0045] 1) The general motherboard 3 is interconnected with the CPU module 9 through the COMe interface 34, thereby constructing a small and efficient core processing platform;
[0046] 2) The general motherboard 3 is interconnected with the system disk 7 through the mSATA interface 32, which is used for installing and running an operating system;
[0047] 3) through M.2 interface 33 with data disk 8 interconnection, for storage operating system after processing data;
[0048] 4) through the first IPEX interface 31 and FPGA data acquisition processing board 4 interconnection, using PCIE x8 Gen3 bus standard realizes two parts high speed data transmission;
[0049] 5) through USB3.0 interface 37 can be interconnected with external equipment, such as mouse, keyboard or U disk, etc.;
[0050] 6) through the gigabit network port 35 can be realized with external interconnection;
[0051] 7) through the 10 gigabit network port 36 can support the external network large data transmission demand;
[0052] 8) through VGA interface 38 can be external display.
[0053] The above-mentioned general-purpose motherboard 3 is designed with clock management circuit 11, can realize the clock synchronization of each part board card;General-purpose motherboard 3 is also designed with power management module 10, can control the working state of each board card through ultra-wideband signal acquisition processing equipment software, so as to realize the optimization of the whole board power consumption according to the specific application.
[0054] The utility model provides an ultra-wideband signal acquisition processing equipment, this equipment is through modularization design, widely adapts market demand, on the whole machine design, fully considers electromagnetic interference, heat dissipation, portability and safety factor etc., provides the very valuable guiding meaning for similar application.
[0055] Although the utility model has been described herein with reference to the explanatory embodiments of the utility model, the above-mentioned embodiments are only the preferred implementation of the utility model, and the implementation of the utility model is not limited by the above-mentioned embodiments, it should be understood that the person skilled in the art can design a lot of other modifications and implementation, these modifications and implementation will fall in the principle range and the spirit disclosed in this application.
Claims
1. An ultra-wideband signal acquisition processing device comprising a chassis, characterized in that, The cabinet is provided with a partition plate, a general mainboard and an FPGA data acquisition and processing board are fixedly connected on the partition plate, the general mainboard and the FPGA data acquisition and processing board are electrically connected through a first communication interface, a gigabit network interface, a terabit network interface, a USB3.0 interface and a VGA interface are arranged on the general mainboard, and the general mainboard is further provided with a second communication interface for electrically connecting a system disk, a data disk and a CPU module; a timing module, an RS422 interface, a debugging interface and a plurality of FMC interfaces for electrically connecting data acquisition subcards are arranged on the FPGA data acquisition and processing board, and the data acquisition subcards are electrically connected with radio frequency modules.
2. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The first communication interface is an IPEX interface.
3. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The second communication interface comprises a COMe interface, an mSATA interface and an M.2 interface, the COMe interface is used for communication connection between the general mainboard and the CPU module, the mSATA interface is used for communication connection between the general mainboard and the system disk, and the M.2 interface is used for communication connection between the general mainboard and the data disk.
4. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The gigabit network interface has three.
5. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The USB3.0 interface has two.
6. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The FMC interface has three.
7. The ultra-wideband signal acquisition and processing device according to claim 1, wherein, The gigabit network interface is extended to the panel of the cabinet through an RJ45 connector; The terabit network interface is extended to the panel of the cabinet through an LC flange optical fiber interface; The USB3.0 interface is extended to the panel of the cabinet through a Type-A connector; The VGA interface is extended to the panel of the cabinet through a D-sub 15 connector; The RS422 interface is extended to the panel of the cabinet through a D-sub9 connector; The debugging interface is extended to the panel of the cabinet through an H30J connector; The timing module is extended to the panel of the cabinet through an SMA connector.
8. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The general mainboard and the FPGA data acquisition and processing board are fixed on the partition plate through screws.
9. The ultra-wideband signal acquisition and processing device of claim 1, wherein, The radio frequency module is provided with two input interfaces and two output interfaces, the input interfaces are extended to the panel of the cabinet through SMA connectors, and the output interfaces are electrically connected with the data acquisition subcards.