Display device and display panel

Abstract

The utility model provides a display device and a display panel, and relates to the technical field of display. The display panel comprises a driving backboard and a light-emitting layer, the light-emitting layer is arranged on one side of the driving backboard and comprises a plurality of light-emitting devices, and each light-emitting device comprises a light-emitting unit, a first electrode and a second electrode; the light-emitting unit comprises a light-emitting body and an outer insulation protection layer covering at least partial area of the side wall of the light-emitting body. The luminous body comprises a first semiconductor layer, a quantum well layer and a second semiconductor layer which are stacked in sequence; the first semiconductor layer is connected with the driving backboard through a first electrode; and the second semiconductor layer is connected with the driving back plate through the second electrode. The luminous efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display device and a display panel. Background Technology

[0002] Light-emitting diodes (LEDs) are characterized by their small size, long lifespan, rich and varied colors, and low energy consumption, and have been widely used in the display field. However, the luminous efficiency of existing LED-based display panels still needs to be improved.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content

[0004] This disclosure provides a display device and display panel that can improve luminous efficiency.

[0005] According to one aspect of this disclosure, a display panel is provided, comprising:

[0006] Drive backplane:

[0007] A light-emitting layer is disposed on one side of the driving backplate and includes a plurality of light-emitting devices. Each light-emitting device includes a light-emitting unit, a first electrode, and a second electrode. The light-emitting unit includes a light-emitting body and an outer insulating protective layer covering at least a portion of the sidewall of the light-emitting body. The light-emitting body includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked sequentially. The first semiconductor layer is connected to the driving backplate through the first electrode. The second semiconductor layer is connected to the driving backplate through the second electrode.

[0008] In one exemplary embodiment of this disclosure, the light-emitting layer further includes a substrate and an insulating filler layer; each of the light-emitting units is stacked on the side of the substrate near the driving backplate, and the insulating filler layer fills the gap between adjacent light-emitting units and contacts the outer insulating protective layer.

[0009] In one exemplary embodiment of this disclosure, the first electrode and the second electrode are located on the surface of the light-emitting layer near the driving backplate.

[0010] In one exemplary embodiment of this disclosure, the first electrode is located on the surface of the light-emitting element away from the driving backplate, and the first electrode, the light-emitting element, and the second electrode are stacked sequentially in a direction close to the driving backplate.

[0011] In one exemplary embodiment of this disclosure, the first electrode connected to each of the light-emitting units is an integral structure.

[0012] In one exemplary embodiment of this disclosure, the light emitter includes a plurality of sub-light emitters spaced apart, and at least a portion of the sidewalls of at least some of the sub-light emitters are covered with an inner insulating protective layer.

[0013] In one exemplary embodiment of this disclosure, the thickness of the outer insulating protective layer gradually increases in the direction parallel to the drive backplate, moving away from the drive backplate.

[0014] In one exemplary embodiment of this disclosure, the thickness of the inner insulating protective layer in the direction parallel to the drive back plate gradually decreases in the direction close to the drive back plate.

[0015] In one exemplary embodiment of this disclosure, at least one of the outer insulating protective layer and the inner insulating protective layer is made of a semiconductor oxide.

[0016] According to one aspect of this disclosure, a display device is provided, comprising the display panel described in any of the preceding claims.

[0017] The display device and display panel disclosed herein can achieve light emission by controlling the electrical signals of the first electrode and the second electrode, which enables the charge carriers (electrons and holes) provided by the first semiconductor layer and the second semiconductor layer to undergo radiative recombination in the quantum well layer. The outer insulating protective layer can cover defects such as damage caused by etching processes on the sidewalls of the light-emitting body, preventing leakage current at the defect sites and thus improving luminous efficiency.

[0018] During manufacturing, the outer insulating protective layer is the residual oxide part, which can protect the sidewall of the light-emitting body, so that the sidewall of the light-emitting body is not etched and formed, avoiding deep energy level defects in the material such as dangling bonds caused by etching, reducing non-radiative recombination; it can effectively reduce the sidewall effect of the light-emitting unit and improve the luminous efficiency.

[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0021] Figure 1 This is a partial cross-sectional schematic diagram of a first embodiment of the display panel of this disclosure.

[0022] Figure 2-8 A cross-sectional schematic diagram corresponding to some steps in forming the display panel of the first embodiment.

[0023] Figure 9 This is a partial cross-sectional schematic diagram of a first embodiment of the display panel of this disclosure.

[0024] Figures 10-13 A cross-sectional schematic diagram corresponding to some steps in forming the display panel of the second embodiment.

[0025] Figure 14 This is a partial cross-sectional schematic diagram of a third embodiment of the display panel of this disclosure.

[0026] Figures 15-20 A cross-sectional schematic diagram corresponding to some steps in forming the display panel of the third embodiment.

[0027] Figure 21 This is a partial cross-sectional schematic diagram of a fourth embodiment of the display panel of this disclosure.

[0028] Figures 22-25 A cross-sectional schematic diagram corresponding to some steps in forming the display panel of the fourth embodiment. Detailed Implementation

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0030] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0031] This disclosure provides a display panel divided into a display area and a peripheral area outside the display area. The peripheral area can be a continuous annular region surrounding the display area, or it can be a discontinuous region surrounding the display area, for example, the peripheral area can be distributed on both sides of the display area. The display area can emit light to display images, while the peripheral area does not emit light.

[0032] This disclosure provides a display panel divided into a display area and a peripheral area outside the display area. The peripheral area can be a continuous annular region surrounding the display area, or it can be a discontinuous region surrounding the display area, for example, the peripheral area can be distributed on both sides of the display area. The display area can emit light to display images, while the peripheral area does not emit light.

[0033] like Figure 1 , Figure 9 , Figure 14 and Figure 21 As shown, the display panel may include a driving backplate BP and a light-emitting layer EL disposed on one side of the driving backplate BP. The light-emitting layer EL may include multiple light-emitting devices LD, wherein:

[0034] The driving backplane (BP) has a driving circuit that drives the light-emitting diode (LD) to emit light to display an image. In some embodiments of this disclosure, the driving backplane (BP) may include a substrate and a circuit layer located on one side of the substrate. The substrate may be a flat plate structure, and its material may be a rigid material such as glass or a flexible material such as polyimide. Furthermore, the substrate may be a single-layer or multi-layer structure.

[0035] The circuit layer includes the aforementioned driving circuitry. For example, the driving circuitry may include pixel circuitry located in the display area and peripheral circuitry located in the peripheral area. The pixel circuitry can be an nTmC structure, as long as it can drive the light-emitting diode (LD) to emit light; its structure is not specifically limited here. Here, nTmC indicates that a pixel circuitry includes n thin-film transistors (represented by the letter "T") and m capacitors (represented by the letter "C"). The number of pixel circuits can be the same as the number of LDs, and they are connected one-to-one with each LD. Of course, multiple LDs can be connected to the same pixel circuitry; this is not specifically limited here. The peripheral circuitry is connected to the pixel circuitry and is used to input driving signals to the pixel circuitry to control the LDs to emit light. The peripheral circuitry may include gate driving circuitry and light-emitting control circuitry; of course, it may also include other circuits. The specific structure of the peripheral circuitry is not specifically limited here.

[0036] like Figure 1 , Figure 9 , Figure 14 and Figure 21 As shown, the light-emitting layer EL can be stacked on the driving backplane BP, and the light-emitting layer EL can include multiple light-emitting devices LD. The light-emitting devices LD can be Mini LED (sub-millimeter light-emitting diode, size 100μm-200μm), Micro LED (micro light-emitting diode, size no greater than 100μm) and LED (light-emitting diode, size greater than 200μm) using inorganic light-emitting materials, etc., without special limitations.

[0037] Any light-emitting device (LD) can be disposed on a driving backplane (BP). The LD may include a light-emitting unit (LU) and a first electrode (NE) and a second electrode (PE) connected to the LU. The first electrode (NE) and the second electrode (PE) can be connected to the driving circuit of the driving backplane (BP) to drive the light-emitting unit (LU) to emit light. Taking a Micro LED as an example, the light-emitting unit (LU) may include a first semiconductor layer (NL), a quantum well layer (MQW), and a second semiconductor layer (PL) stacked sequentially. The first semiconductor layer (NL) may be made of an N-type semiconductor material, and the second semiconductor layer (PL) may be made of a P-type semiconductor material. For example, the first semiconductor layer (NL) may be made of N-type GaN, and the second semiconductor layer (PL) may be made of P-type GaN. The first semiconductor layer (NL) is connected to the first electrode (NE), and the second electrode (PE) is connected to the second semiconductor layer (PL). Electrical signals can be transmitted to the first semiconductor layer (NL) and the second semiconductor layer (PL) through the driving backplane (BP), respectively, so that the charge carriers generated in the first semiconductor layer (NL) and the second semiconductor layer (PL) undergo radiative recombination in the quantum well layer (MQW) to achieve light emission.

[0038] Each light-emitting unit (LU) can be spaced apart and can be mounted on the drive backplate (BP) using an inverted, vertical, or upright structure. For example... Figure 1 As shown, if a flip-chip structure is used, the first electrode NE and the second electrode PE can be disposed on the same layer and connected to the pads on the driving backplane BP. If a vertical structure is used, the first semiconductor layer NL, the quantum well layer MQW, and the second semiconductor layer PL are located between the first electrode NE and the second electrode PE. The second electrode PE can be bonded to the pads on the driving backplane BP to achieve connection, and the first electrode NE can also be connected to the driving backplane BP; and the first electrode NE of each light-emitting unit LU can be an integral structure, that is, the first electrode NE can be a continuous whole layer structure, and each light-emitting unit LU shares the same first electrode NE. If a conventional structure is used, the first semiconductor layer NL, the quantum well layer MQW, and the second semiconductor layer PL can be stacked sequentially in the direction away from the driving backplane BP; the first electrode NE and the second electrode PE can be disposed on the side of the second semiconductor layer PL away from the driving backplane BP, and can be connected to the driving circuit of the driving backplane BP through connecting wires.

[0039] Furthermore, the light-emitting layer EL can be a continuous, monolithic structure, integrally connected to the driving backplane BP. In this case, the light-emitting unit LU can adopt an inverted or vertical structure, such as... Figure 1 , Figure 9 , Figure 14 and Figure 21 As shown, in some embodiments of this disclosure, the light-emitting layer EL may further include an insulating filling layer FL, which can fill the space between adjacent light-emitting units LU, so that the light-emitting layer EL becomes a whole structure and can be stacked and connected as a whole with the driving backplane BP.

[0040] In some embodiments of this disclosure, such as Figure 1 and Figure 2 As shown, for the light-emitting unit LU with flip-chip and upright structures, the light-emitting layer EL may also include a substrate SU. The substrate SU may be made of insulating materials such as sapphire. The first semiconductor layer NL, the quantum well layer MQW, and the second semiconductor layer PL may be sequentially formed on the substrate SU through epitaxial processes to form an epitaxial layer ML with an integral structure. At the same time, the substrate SU of each light-emitting unit LU may be an integral structure, and the light-emitting unit LU may not be an upright structure. Alternatively, each light-emitting unit LU may be obtained by splitting the same substrate SU and its epitaxial layer ML through a dicing process, so that the substrate SU of each light-emitting unit LU may be arranged at intervals.

[0041] In some embodiments of this disclosure, such as Figure 14 As shown, for a vertically structured light-emitting unit LU, a substrate can be provided during the formation of the light-emitting layer EL. The first electrode NE can be stacked on the substrate SU. The first semiconductor layer NL, the quantum well layer MQW, the second semiconductor layer PL, and the second electrode PE are sequentially formed on the first electrode NE. After connecting the light-emitting unit LU to the driving backplane BP, the substrate SU can be peeled off; of course, the substrate SU can also be used to encapsulate the light-emitting unit LU without peeling it off. Furthermore, the substrates SU of each light-emitting unit LU can be spaced apart or used as a single unit, and the first electrode NE can also be a single unit.

[0042] The light emitter LP can be a continuous, monolithic structure; however, in some embodiments of this disclosure, such as Figure 9 and Figure 21 As shown, the light emitter LP can also include multiple sub-light emitters LPs spaced apart. Each sub-light emitter LP can be a columnar structure and may include a first semiconductor layer NL, a quantum well layer MQW, and a second semiconductor layer PL stacked sequentially, so that each sub-light emitter LP can emit light. The sub-light emitters LPs of the same light emitter LP can be connected to the same first electrode NE and the same second electrode PE, so that all sub-light emitters LPs of the same light emitter LP can emit light simultaneously. There are gaps between adjacent sub-light emitters LPs of the same light emitter LP. Because each sub-light emitter LP can emit light, compared to a single-structure light emitter LP, it is advantageous to increase the light emission angle.

[0043] When forming a light-emitting unit (LU), a first semiconductor layer NL, a quantum well layer MQW, and a second semiconductor layer PL of an integral structure can be formed first. Then, the first semiconductor layer NL, the quantum well layer MQW, and the second semiconductor layer PL are patterned by plasma etching or other processes to separate the first semiconductor layer NL, the quantum well layer MQW, and the second semiconductor layer PL of each light-emitting unit LU. During this process, the inventors discovered that the etching process can damage the sidewalls of individual light-emitting units LU, forming sidewall defects. Defects such as deep-level defects and dislocations act as nonradiative recombination centers, leading to an increase in nonradiative recombination and a decrease in radiative recombination in the light-emitting device (LD), resulting in a reduction in internal / external quantum efficiency and affecting luminous efficiency. For example, the mechanism by which sidewall defects affect EQE (external quantum efficiency) includes: electrons and holes recombine at the sidewall surface to form photons, but the light emitted from the sidewall is not effectively utilized; leakage channels are formed at the sidewall defects, and charge carriers form leakage current at the defects; charge carriers are trapped at the defects and undergo nonradiative recombination. To address this technical problem, the inventors proposed that an insulating protective layer can be used to protect the sidewalls of the light-emitting unit (LU), preventing sidewall defects and thus improving luminous efficiency. This will be explained in detail below:

[0044] like Figure 1 , Figure 9 , Figure 14 and Figure 21 As shown, for any light-emitting device LD, its light-emitting unit LU may include a light-emitting element LP and an outer insulating protective layer W1. The light-emitting elements LP of each light-emitting device LD may be distributed at intervals, and the light-emitting element LP is the part of the light-emitting device LD that actually radiates photons outward. It may include the stacked first semiconductor layer NL, quantum well layer MQW and second semiconductor layer PL. The outer insulating protective layer W1 does not directly participate in radiation. It may cover at least a part of the sidewall of the light-emitting element LP. That is, the outer insulating protective layer W1 may cover at least a part of the sidewall of at least one of the first semiconductor layer NL, quantum well layer MQW and second semiconductor layer PL.

[0045] like Figure 4 , Figure 10 and Figure 17As shown, when forming each light-emitting unit LU, an epitaxial layer ML containing a first semiconductor layer NL, a quantum well layer MQW, and a second semiconductor layer PL can be formed first. Then, a portion of the epitaxial layer ML is selectively thermally oxidized (STO) to form an oxide portion OP made of semiconductor oxide material. The oxide portion OP is then etched using processes such as inductively coupled plasma (ICP) to remove a portion of the oxide portion OP, thereby achieving patterning and obtaining multiple light-emitting units LU. Each light-emitting unit LU includes a light emitter LP and an outer insulating protective layer W1 covering the sidewall of the light emitter LP. Thus, the sidewall of the light emitter LP can be etched directly instead of the oxide portion OP, thereby preventing the sidewall defects mentioned above from appearing on the sidewall of the light emitter LP. This reduces nonradiative recombination of the light-emitting device LD, improves radiative recombination and internal / external quantum efficiency, and is beneficial to improving luminous efficiency.

[0046] Furthermore, in some embodiments of this disclosure, the thickness of the outer insulating protective layer W1 in the direction parallel to the drive backplate BP can gradually increase in the direction away from the drive backplate BP.

[0047] In a first embodiment of the display panel of this disclosure, such as Figures 1-8 As shown, the light-emitting device LD adopts a flip-chip structure. The light-emitting layer EL includes a substrate SU and a plurality of light-emitting units LU formed on the substrate SU at intervals. The substrate SU can be made of sapphire or other materials that can be epitaxially processed. Each light-emitting unit LU includes a light emitter LP and an outer insulating protective layer W1 covering the sidewall of the light emitter LP. The light emitter LP includes a first semiconductor layer NL, a quantum well layer MQW and a second semiconductor layer PL stacked sequentially in a direction away from the substrate SU. A protrusion is formed on a local protrusion on the surface of the first semiconductor layer NL away from the substrate SU, and the quantum well layer MQW is stacked on the protrusion. The outer insulating protective layer W1 extends to the surface of the first semiconductor layer NL away from the substrate SU, other than the protrusion, thereby covering the quantum well layer MQW, the second semiconductor layer PL and the sidewall of the protrusion, and the outer insulating protective layer W1 does not exceed the boundary of the first semiconductor layer NL.

[0048] The light-emitting layer EL also includes an insulating filling layer FL, which can fill the gaps between the light-emitting units LU and achieve planarization. The surface of the insulating filling layer FL away from the substrate can be coplanar with the surface of the light-emitting unit LU away from the substrate; or, the insulating filling layer FL can also cover each light-emitting unit LU to achieve planarization.

[0049] The first electrode NE and the second electrode PE can be disposed on the surface of the light-emitting layer EL near the driving backplane BP. For example, the surface of the insulating filling layer FL away from the substrate can be coplanar with the surface of the light-emitting unit LU away from the substrate. In this case, the first electrode NE can be disposed on the surface of the insulating filling layer FL near the driving backplane BP and connected to the first semiconductor layer NL via a via. The second electrode PE is disposed on the surface of the second semiconductor layer PL near the driving backplane BP and connected to the second semiconductor layer PL. Of course, if the insulating filling layer FL can also cover each light-emitting unit LU, then the first electrode NE and the second electrode PE can be disposed on the surface of the insulating filling layer FL near the driving backplane BP, and the first electrode NE can be connected to the first semiconductor layer NL via a via, and the second electrode PE can be connected to the second semiconductor layer PL via a via.

[0050] In a second embodiment of the display panel of this disclosure, such as Figures 9-13 As shown, the light-emitting device (LD) adopts a flip-chip structure, and its structure can be referred to the first embodiment described above. The light-emitting element (LP) may include multiple spaced sub-light-emitting elements (LPs). The depth of the gap (GP) between adjacent sub-light-emitting elements (LPs) is not greater than the thickness of the light-emitting element (LP). For example, the gap (GP) may extend from the second semiconductor layer (PL), through the quantum well layer (MQW), to the first semiconductor layer (NL), but may not penetrate the first semiconductor layer (NL). The second electrode (PE) may simultaneously cover the second semiconductor layer (PL) of each sub-light-emitting element (LP), thereby simultaneously connecting to the second semiconductor layer (PL) of each sub-light-emitting element (LP). The first electrode (NE) may connect to the surface of the first semiconductor layer (NL) without protrusions, thereby simultaneously connecting to the first semiconductor layer (NL) of each sub-light-emitting element (LP).

[0051] like Figure 9 , Figure 11 , Figure 21 and Figure 23 As shown, at least a portion of the sidewalls of at least some of the sub-emitters LPs are covered with an inner insulating protective layer W2, the material of which may include a semiconductor oxide. During the formation of the sub-emitters LPs, a selective thermal oxidation process can be performed on the epitaxial layer ML to form multiple unoxidized sub-emitters LPs and oxidized sub-oxide portions OPs. By locally removing the sub-oxide portions OPs, sub-emitters LPs covered with the inner insulating protective layer W2 can be obtained. Since the sidewalls of the sub-emitters LPs are covered by the inner insulating protective layer W2, they are not directly etched, preventing sidewall defects and improving luminous efficiency. Furthermore, the thickness of the inner insulating protective layer W2 gradually decreases in the direction close to the driving backplate BP in the direction parallel to the driving backplate BP. The gaps GAP between adjacent sub-emitters LPs may or may not be filled with an insulating material.

[0052] In a third embodiment of the display panel of this disclosure, such as Figures 14-20As shown, the light-emitting device LD adopts a vertical structure. The light-emitting layer EL includes a substrate SU and a plurality of light-emitting units LU formed on the substrate SU at intervals. Each light-emitting unit LU includes a light emitter LP and an outer insulating protective layer W1 covering the sidewall of the light emitter LP. The light emitter LP includes a first electrode NE, a first semiconductor layer NL, a quantum well layer MQW and a second semiconductor layer PL stacked sequentially in a direction away from the substrate SU. The outer insulating protective layer W1 extends to the surface of the first electrode NE away from the substrate SU, thereby covering the sidewalls of the first semiconductor layer NL, the quantum well layer MQW and the second semiconductor layer PL.

[0053] The light-emitting layer EL also includes an insulating filling layer FL, which can fill the gaps between the light-emitting units LU and achieve planarization. The surface of the insulating filling layer FL away from the substrate can be coplanar with the surface of the light-emitting unit LU away from the substrate; or, the insulating filling layer FL can also cover each light-emitting unit LU to achieve planarization.

[0054] The first electrode NE can be disposed on the surface of the substrate SU near the driving backplane BP. For example, the surface of the insulating filling layer FL away from the substrate SU can be coplanar with the surface of the light-emitting unit LU away from the substrate SU. Then, the second electrode PE can be disposed on the surface of the second semiconductor layer PL near the driving backplane BP, thereby connecting with the second semiconductor layer PL. Of course, the insulating filling layer FL can also cover each light-emitting unit LU. In this case, the second electrode PE can be disposed on the surface of the insulating filling layer FL near the driving backplane BP, and the second electrode PE can be connected to the second semiconductor layer PL via a via.

[0055] In a fourth embodiment of the display panel of this disclosure, such as Figures 21-25 As shown, the light-emitting device (LD) adopts a vertical structure, which can be referred to in the third embodiment described above. The light-emitting element (LP) may include multiple spaced sub-light-emitting elements (LPs). The depth of the gap between adjacent self-light-emitting elements (LPs) can be equal to the thickness of the light-emitting element (LP), that is, the gap can penetrate the second semiconductor layer (PL), the quantum well layer (MQW), and the first semiconductor layer (NL). A second electrode (PE) can simultaneously cover the second semiconductor layer (PL) of each sub-light-emitting element (LP) of the same light-emitting element (LP), thereby simultaneously connecting to the second semiconductor layer (PL) of each sub-light-emitting element (LP).

[0056] At least a portion of the sidewalls of at least some of the sub-emitters (LPs) are covered with an inner insulating protective layer W2, the material of which may include a semiconductor oxide. During the formation of the sub-emitters (LPs), a selective thermal oxidation process can be performed on the epitaxial layer ML to form multiple unoxidized sub-emitters (LPs) and oxidized sub-oxide portions (OPs). By locally removing the sub-oxide portions (OPs), sub-emitters (LPs) covered with the inner insulating protective layer W2 can be obtained. Since the sidewalls of the sub-emitters (LPs) are covered by the inner insulating protective layer W2 and are not directly etched, sidewall defects are prevented, which is beneficial for improving luminous efficiency. Furthermore, the thickness of the inner insulating protective layer W2 gradually decreases in the direction parallel to the driving backplate BP, moving closer to the driving backplate BP. The gaps between adjacent sub-emitters (LPs) may or may not be filled with an insulating material.

[0057] This disclosure also provides a method for manufacturing a display panel, which can be any of the display panels described in the above embodiments, and its structure will not be detailed here; the manufacturing method may include steps S10 and S20, wherein:

[0058] Step S10: Oxidize a portion of an epitaxial layer ML to obtain multiple light emitters LP and an oxide portion OP that divides the light emitters LP; the epitaxial layer ML includes a first semiconductor layer NL, a quantum well layer, and a second semiconductor layer PL stacked sequentially.

[0059] Step S20: Remove a portion of the oxide portion OP and divide a plurality of light-emitting units LU on the epitaxial layer ML; the light-emitting unit LU includes a light-emitting element LP and an outer insulating protective layer W1, the outer insulating protective layer W1 is the remaining oxide portion OP, and the outer insulating protective layer W1 covers at least a portion of the sidewall of the light-emitting element LP.

[0060] The manufacturing method of this embodiment involves locally oxidizing the epitaxial layer ML and then removing part of the oxide portion OP. The sidewall of the light emitter LP is protected by an outer insulating layer W1, which does not participate in the etching of the oxide portion OP. This avoids sidewall defects and helps to improve luminous efficiency. The specific principle has been explained in detail above and will not be repeated here.

[0061] The manufacturing method of this disclosure will be described in detail below:

[0062] In step S10, an epitaxial layer ML can be formed on a substrate by an epitaxial process. By performing local oxidation and etching on the epitaxial layer ML, a plurality of light-emitting units LU are obtained. Each light-emitting unit LU includes a light emitter LP and an outer insulating protective layer W1 covering the sidewall of the light emitter LP. The epitaxial layer ML may include a first semiconductor layer NL, a quantum well layer MQW, and a second semiconductor layer PL stacked in sequence.

[0063] In some embodiments of this disclosure, a portion of an epitaxial layer ML is oxidized; i.e., step S10, which includes steps S110 and S120, wherein:

[0064] Step S110: A first masking layer CL1 is formed on an epitaxial layer ML, exposing a portion of the epitaxial layer ML. For example... Figure 3 and Figure 16 As shown.

[0065] The material of the first masking layer CL1 can be silicon oxide (SiO2). The patterned first masking layer CL1 can be formed by a mask, and the first masking layer CL1 is used to protect the epitaxial layer ML it covers.

[0066] Step S120: Anneal the epitaxial layer ML on which the first shielding layer CL1 is formed, so that the region of the epitaxial layer ML not covered by the first shielding layer CL1 is oxidized, to obtain the oxidized part OP and the light emitter LP divided by the oxidized part OP. Figure 4 and Figure 17 As shown.

[0067] The oxidized area is the oxide part OP, and the unoxidized area is the light emitter LP. The epitaxial layer ML can be placed in a heating furnace under ambient air and annealed at a specified temperature for a specified time to oxidize the area not protected by the first shielding layer CL1; the specified time can be 4 hours, and the specified temperature can be 800°C.

[0068] In some embodiments of this disclosure, the first shielding layer CL1 may include multiple shielding units, each shielding unit covering a light emitter LP. The boundary of the orthographic projection of a shielding unit onto the substrate is located outside the boundary of the orthographic projection of the light emitter LP it shields onto the substrate; that is, the shielding unit is larger than the light emitter LP it shields, thus preventing the light emitter LP from being oxidized. Furthermore, the orthographic projections of the light emitter LP and the shielding unit onto the substrate can be identical. For example, both can be squares, with the orthographic projection of the light emitter LP onto the substrate being a 30μm × 30μm square, and the orthographic projection of the shielding unit onto the substrate being a 34μm × 34μm square. Additionally, the thickness of the first shielding layer CL1 is 3μm.

[0069] After obtaining the light-emitting element LP and the oxide portion OP, but before removing a portion of the oxide portion OP (i.e., after step S120 and before step S20), the manufacturing method further includes:

[0070] Step S30: Remove the first occlusion layer CL1.

[0071] The first shielding layer CL1 can be removed by HF (hydrogen fluoride) vapor to expose the epitaxial layer ML.

[0072] In some embodiments of this disclosure, for the first embodiment described above, the thickness of the oxide portion OP is less than the thickness of the epitaxial layer ML. A portion of the oxide portion OP is removed; that is, step S20 includes steps S210 and S220, wherein:

[0073] Step S210: Remove a portion of the oxide layer OP until the epitaxial layer ML is exposed, obtaining the outer insulating protective layer W1. (Example) Figure 5 As shown.

[0074] The oxide portion OP can be etched using processes such as inductively coupled plasma (ICP-P), but without penetrating the epitaxial layer ML; simultaneously, a portion of the oxide portion OP is retained as an outer insulating protective layer W1. The maximum thickness of the outer insulating protective layer W1 can be 2 μm.

[0075] Step S220: Remove the epitaxial layer ML exposed by the oxidized portion OP to form multiple light emitters LP; an outer insulating layer covers at least a portion of the sidewalls of the light emitters LP, and the light-emitting unit LU includes the light emitter LP and the outer insulating protective layer W1. For example... Figure 6 As shown.

[0076] Based on the etching in step S210, further etching can be performed to penetrate the epitaxial layer ML but not the substrate, thereby dividing the epitaxial layer ML into multiple light emitters LP. The sidewalls of each light emitter LP are partially covered by an outer insulating protective layer W1.

[0077] Based on the first and second implementation methods described above, such as Figure 7 and Figure 8 As shown, in some embodiments of this disclosure, after removing a portion of the oxide portion OP, i.e., after step S20, the manufacturing method further includes steps S40-S60, wherein:

[0078] Step S40: Form an insulating filling layer FL between adjacent light-emitting units LU to obtain the light-emitting layer EL.

[0079] Step S50: A first electrode NE and a second electrode PE are formed on the surface of the light-emitting layer EL. The first electrode NE is connected to the first semiconductor layer NL, and the second electrode PE is connected to the second semiconductor layer PL.

[0080] Step S60: Connect the first electrode NE and the second electrode PE to a drive backplate BP.

[0081] The specific structures of the insulating filler layer FL, the first electrode NE, and the second electrode PE have been described above and will not be detailed here.

[0082] Based on the third and fourth implementation methods described above, such as Figure 15As shown, in some embodiments of this disclosure, before oxidizing a portion of an epitaxial layer ML, i.e. before step S10, the manufacturing method further includes steps S70 and S80, wherein:

[0083] Step S70: Form a first electrode NE on a substrate;

[0084] Step S80: An epitaxial layer ML is formed on the side of the first electrode NE away from the substrate, and the first electrode NE is connected to the first semiconductor layer NL.

[0085] Furthermore, after removing a portion of the oxidized OP region, i.e., after step S20, the manufacturing method further includes steps S40-S60, wherein:

[0086] Step S40: Form an insulating fill layer FL between adjacent light-emitting units LU; as shown Figure 20 As shown.

[0087] In step S50, a second electrode PE is formed on the surface of the insulating filling layer FL away from the substrate, and the second electrode PE is connected to the second semiconductor layer PL.

[0088] Step S60: Connect the first electrode NE and the second electrode PE to a drive backplane BP. For example... Figure 14 As shown.

[0089] The specific structures of the insulating filler layer FL, the first electrode NE, and the second electrode PE have been described above and will not be detailed here.

[0090] Regarding the light emitter LP having sub-light emitters LPs in the second and fourth embodiments described above, as follows: Figures 9-13 as well as Figures 21-25 As shown, in some embodiments of this disclosure, after removing the first shielding layer CL1 and before removing a portion of the oxide portion OP, i.e. after step S30 and before step S20, the manufacturing method further includes steps 90 and 100, wherein:

[0091] Step 90: Form sub-oxidized parts OPs in the luminescent body LP, dividing the luminescent body LP into multiple spaced sub-luminescent bodies LPs. For example... Figure 11 and Figure 23 As shown.

[0092] Step 100: Remove a portion of the sub-oxidized portion OPs to obtain an inner insulating protective layer W2, which covers at least a portion of the sidewalls of the sub-emitting elements LPs. For example... Figure 12 and Figure 25 As shown.

[0093] The oxide part OP can be etched by processes such as inductively coupled plasma. The width of the etched area can be 120nm. Sub-oxide parts OPs with a width of 40nm are left on both sides of the etched area as an inner insulating protective layer W2. The unetched area is the sub-light emitter LPs.

[0094] In some embodiments of this disclosure, the formation of sub-oxidation portions OPs in the light emitter LP, i.e., step 90, includes steps 910-930, wherein:

[0095] Step 910: Form a second shielding layer CL2 on the surface of the epitaxial layer ML. For example... Figure 10 and Figure 22 As shown.

[0096] The second shielding layer CL2 can be made of heat-resistant materials such as silicon oxide, and its thickness can be 1μm. The second shielding layer CL2 covers the area where sub-emitters LPs are to be formed, exposing the gaps between the sub-emitters LPs, thereby protecting the sub-emitters LPs. The width of the gap can be 200nm.

[0097] Step 920: Anneal the epitaxial layer ML on which the second shielding layer CL2 is formed, to form sub-oxides OPs within the luminescent body LP. For example... Figure 11 and Figure 23 As shown.

[0098] The epitaxial layer ML is oxidized again through an annealing process. The oxidized areas are the sub-oxidized parts OPs, and the unoxidized areas are the sub-light emitters LPs. The epitaxial layer ML can be placed in a heating furnace under ambient air and annealed at a specified temperature for a specified time, so that the areas not protected by the first shielding layer CL1 are oxidized. The annealing time and temperature when protected by the first shielding layer CL1 can be less than the annealing time and temperature when protected by the second shielding layer CL2. For example, the specified annealing time in step S920 can be 2 hours, and the specified temperature can be 600°C.

[0099] Step 930: Remove the second occlusion layer CL2. (e.g.) Figure 24 As shown.

[0100] It should be noted that although the various steps of the manufacturing method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0101] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. The specific structure and beneficial effects of the display panel can be referred to the above embodiments of the display panel, and will not be described in detail here. The display device of this disclosure may be a vehicle-mounted display device, a laptop computer or other medium to large-sized display device, or it may be used in other electronic devices with display functions such as mobile phones, which will not be listed here.

[0102] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a driving back plate; a light-emitting layer arranged on one side of the driving back plate and comprising a plurality of light-emitting devices, each of the light-emitting devices comprising a light-emitting unit, a first electrode and a second electrode; the light-emitting unit comprising a light-emitting body and an outer insulating protective layer covering at least part of a side wall of the light-emitting body; the light-emitting body comprising a first semiconductor layer, a quantum well layer and a second semiconductor layer stacked in sequence; the first semiconductor layer being connected to the driving back plate through the first electrode; the second semiconductor layer being connected to the driving back plate through the second electrode.

2. The display panel of claim 1, wherein, The light-emitting layer further comprises a substrate and an insulating filling layer; each of the light-emitting units is stacked on one side of the substrate close to the driving back plate; the insulating filling layer fills a gap between adjacent light-emitting units and is in contact with the outer insulating protective layer.

3. The display panel of claim 1, wherein, The first electrode and the second electrode are located on a surface of the light-emitting layer close to the driving back plate.

4. The display panel of claim 1, wherein, The first electrode is located on a surface of the light-emitting body away from the driving back plate; and the first electrode, the light-emitting body and the second electrode are stacked in sequence along a direction close to the driving back plate.

5. The display panel of claim 4, wherein, The first electrode connected to each of the light-emitting units is of an integral structure.

6. The display panel of claim 1, wherein, The light-emitting body comprises a plurality of sub-light-emitting bodies distributed at intervals; at least part of a side wall of at least part of the sub-light-emitting bodies is covered with an inner insulating protective layer.

7. The display panel according to any one of claims 1-6, wherein, A thickness of the outer insulating protective layer in a direction parallel to the driving back plate gradually increases along a direction away from the driving back plate.

8. The display panel of claim 6, wherein, A thickness of the inner insulating protective layer in a direction parallel to the driving back plate gradually decreases along a direction close to the driving back plate.

9. The display panel of claim 6, wherein, A material of at least one of the outer insulating protective layer and the inner insulating protective layer comprises a semiconductor oxide.

10. A display device, characterized by comprising: The display panel comprises the display panel of any one of claims 1-9. The display panel comprises the display panel of any one of claims 1-9.

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