Aging test device for intelligent electronic switch

Abstract

The utility model provides an aging test device for intelligent electronic switches, at least two of N intelligent electronic switches are connected in series and then connected with a load to form at least one load path, the at least one load path is connected between the positive end and the negative end of a power supply, the input ends of the N intelligent electronic switches are connected with a signal source, and the input ends of the N intelligent electronic switches are connected with the signal source. The signal source is used for controlling the on-off states of the N intelligent electronic switches; and the signal acquisition circuit is connected with the at least one load path and is used for acquiring a connection signal on the at least one load path and determining an aging test result of the intelligent electronic switch set to be tested according to the connection signal. Namely, according to the test scheme, the intelligent electronic switch to be tested is connected in series to the load path, so that the load is saved, the power consumption in the aging test process can be greatly reduced, and the power consumption is saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to an aging test device for an intelligent electronic switch. BACKGROUND

[0002] With the development of electronic technology, the degree of integration of chips or chip products is improved, and the manufacturing process is more complex. Potential defects may occur in the manufacturing process. Aging test, as a necessary part of the production process of new products, plays a key role in product stability. For example, intelligent electronic switches, as electronic components that control the on-off of load circuits, will undergo strict aging tests before leaving the factory to verify whether the quality of the intelligent electronic switches meets the standards.

[0003] Figure 1 is a schematic diagram of an existing aging test scheme for an intelligent electronic switch. As Figure 1 shown, in the existing aging test scheme, multiple intelligent electronic switches to be tested are simultaneously subjected to aging tests, and the test circuits of each intelligent electronic switch to be tested are connected in parallel, that is, one end of each intelligent electronic switch to be tested is connected to a power supply, the other end is connected to a load R, and the control end is connected to a signal source. The signal source is used to control the working state of each intelligent electronic switch to be tested, thereby controlling the test state of each intelligent electronic switch to be tested.

[0004] However, according to the AEC-Q100 test standard for automotive chips, 77 samples are required for each batch of aging tests of each type of automotive chip, and the aging test time is 1000 hours. The large number of tests and long test time result in the problem of large test power consumption in the above aging test scheme. CONTENT OF THE INVENTION

[0005] The present application provides an aging test device for an intelligent electronic switch, which is used to solve the problem of large test power consumption in the existing aging test scheme.

[0006] In a first aspect, the present application provides an aging test device for an intelligent electronic switch, comprising a power supply, a signal source, a load, a signal acquisition circuit and a set of intelligent electronic switches to be tested.

[0007] The set of intelligent electronic switches to be tested includes N intelligent electronic switches, and N is an integer greater than 1. The N intelligent electronic switches each include a power supply end, a power ground end, a load output end and an input end.

[0008] In the N intelligent electronic switches, at least two of the N intelligent electronic switches are connected in series and then connected with a load to form at least one load path, and the at least one load path is connected between the positive terminal and the negative terminal of the power supply, wherein the load output terminal of at least one intelligent electronic switch is connected with the power supply terminal of the next intelligent electronic switch or the power ground terminal of the previous intelligent electronic switch or the load, the input terminals of the N intelligent electronic switches are connected with the signal source, and the signal source is used to control the switching state of the N intelligent electronic switches.

[0009] The signal acquisition circuit is connected with the at least one load path and is used to acquire the continuous signal on the at least one load path, and the aging test result of the set of intelligent electronic switches to be tested is determined according to the continuous signal.

[0010] Optionally, in the N intelligent electronic switches, the power supply terminal of the first intelligent electronic switch is connected with the positive terminal of the power supply, the load output terminal of the first intelligent electronic switch is connected with the power supply terminal of the second intelligent electronic switch, and the load output terminal of the (N-1)th intelligent electronic switch is connected with the power supply terminal of the Nth intelligent electronic switch, and the load output terminal of the Nth intelligent electronic switch is connected with one end of the load, and the other end of the load and the power ground terminals of the N intelligent electronic switches are connected with the negative terminal of the power supply.

[0011] Optionally, in the N intelligent electronic switches, the power supply terminals of the N intelligent electronic switches and one end of the load are connected with the positive terminal of the power supply, the other end of the load is connected with the load output terminal of the first intelligent electronic switch, the power ground terminal of the first intelligent electronic switch is connected with the load output terminal of the second intelligent electronic switch, and the power ground terminal of the (N-1)th intelligent electronic switch is connected with the load output terminal of the Nth intelligent electronic switch, and the power ground terminal of the Nth intelligent electronic switch is connected with the negative terminal of the power supply.

[0012] Optionally, in the N intelligent electronic switches, the first n intelligent electronic switches are connected in series between the positive terminal of the power supply and the load, and the remaining (N-n) intelligent electronic switches are connected in series between the load and the negative terminal of the power supply, and n is an integer greater than or equal to 1 and less than or equal to N.

[0013] Optionally, the number of loads is x, the N intelligent electronic switches form x load paths with the x loads, at least one load path in the x load paths includes at least two intelligent electronic switches connected in series, and x is an integer greater than or equal to 2 and less than or equal to (N-1).

[0014] Optionally, the signal acquisition circuit is configured to acquire a continuous signal on each load path, and determine that the aging test result of the at least one intelligent electronic switch connected to the load path is normal when the continuous signal indicates that there is a load current on the corresponding load path, and determine that the aging test result of the at least one intelligent electronic switch connected to the load path is abnormal when the continuous signal indicates that there is no load current on the corresponding load path.

[0015] Optionally, the signal acquisition circuit comprises an oscilloscope or a multimeter, and the continuous signal is measured at the load output of the intelligent electronic switch by using the oscilloscope or the multimeter.

[0016] Optionally, the test power consumption of the aging test device is equal to the product of the power supply voltage and the load current flowing through each load path, and the number of load paths.

[0017] Optionally, the signal source provides a test signal to the N intelligent electronic switches to start the aging test of the N intelligent electronic switches when receiving a trigger signal.

[0018] Optionally, the aging test device further comprises a timing circuit connected to the signal source, and the timing circuit is configured to start timing and output a timing signal when the signal source outputs a test signal, or the timing circuit is configured to count a first level in the test signal output by the signal source and output a count signal.

[0019] Optionally, the aging test device further comprises a counting circuit connected to the signal source, and the counting circuit is configured to count a period of the test signal output by the signal source and output a count signal.

[0020] The aging test device for intelligent electronic switches provided in the present application, wherein N intelligent electronic switches to be tested and a load are connected in series to form at least one load path, and the at least one load path is connected between the positive terminal and the negative terminal of a power supply, the load output terminal of at least one intelligent electronic switch is connected to the power supply terminal of the next intelligent electronic switch or the power supply ground terminal of the previous intelligent electronic switch or the load, the input terminals of the N intelligent electronic switches are connected to a signal source, and the signal source is configured to control the switching state of the N intelligent electronic switches; a signal acquisition circuit is connected to the at least one load path, and is configured to acquire a continuous signal on the at least one load path, and determine the aging test result of the set of intelligent electronic switches to be tested according to the continuous signal. The test scheme connects the intelligent electronic switches to be tested in series to the load path, not only saves the load, but also greatly reduces the power consumption in the aging test process and saves the power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0021] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate embodiments consistent with the application and, together with the description, further serve to explain the principles of the application.

[0022] Figure 1 is a schematic diagram of an aging test scheme of an existing intelligent electronic switch;

[0023] Figure 2 is a schematic diagram of a circuit module of an aging test device for an intelligent electronic switch provided by an embodiment of the application;

[0024] Figure 3 is a schematic diagram of a connection relationship of an intelligent electronic switch with a power supply and a load;

[0025] Figure 4 is a schematic diagram of a connection relationship of an intelligent electronic switch connected as a high-side switch;

[0026] Figure 5 is a schematic diagram of a connection relationship of an intelligent electronic switch connected as a low-side switch;

[0027] Figure 6 is Figure 5 a schematic diagram of a connection relationship of an intelligent electronic switch shown in FIG. 6 with a power supply and a load;

[0028] Figure 7 is a schematic diagram of a connection relationship of an intelligent electronic switch in which part of the intelligent electronic switch is connected as a low-side switch and another part is connected as a high-side switch;

[0029] Figure 8 is Figure 7 a schematic diagram of a connection relationship of an intelligent electronic switch shown in FIG. 7 with a power supply and a load;

[0030] Figures 9A to 9C is a schematic diagram of several possible connection relationships of an intelligent electronic switch with a load in an aging test device provided by an embodiment of the application;

[0031] Figure 10 is a schematic diagram of a structure of an aging test device provided by another embodiment of the application.

[0032] The specific embodiments have been shown and described in the foregoing drawings and text, and will be described in more detail hereinafter. These drawings and text are not intended to limit the scope of the concept of the application in any way, but to illustrate the concept of the application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0033] In order to make the purposes, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0034] The terms "comprise" and "have" and any variations thereof that appear in the specification, claims, and drawings of the present application are intended to cover not exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or units, but can optionally include steps or units not listed, or can optionally include other steps or units inherent to the process, method, product, or device.

[0035] In addition, the terms "first", "second", and "third" and the like are used to distinguish different objects, and are not used to describe a specific order. The electrical connection of the present application includes direct electrical connection and indirect electrical connection, and the indirect electrical connection means that there can be other electronic components, pins, etc. between the two components of the electrical connection. The XX terminal mentioned in the present application can be an actually existing terminal, or can not be an actually existing terminal, for example, only one end of a component or one end of a wire. The "and / or" mentioned in the present application includes three cases, for example, A and / or B includes A, B, A and B.

[0036] With the acceleration of the intelligentization of the automobile industry, more and more electronic switches are installed in the automobile. In practical application, intelligent electronic switches are used as the driving and switching of the load in the vehicle due to their high reliability, flexibility, low power consumption, and small size and light weight, and the load is protected and diagnosed, so the intelligent electronic switch has gradually become the development trend of the switch.

[0037] In order to ensure the stability and reliability of the intelligent electronic switch, the aging test of the intelligent electronic switch is one of the indispensable test means, which is an important reference factor for evaluating the reliability of the intelligent electronic switch, and is an important link for evaluating its batch application. The effect of reliability test is directly related to the judgment of the service life of the intelligent electronic switch, therefore, all signal products or chip degrees are tested by reliability test, i.e. aging test.

[0038] By way of example, Figure 1A scheme and a scheme diagram for testing the intelligent electronic switch in the prior art are given. In the scheme, since each intelligent electronic switch is connected between a power supply and a load, according to the AEC-Q100 test standard of the automotive chip, the aging test of each type of intelligent electronic switch chip is 77 samples (test quantity n) per batch, and the aging test time is 1000 hours (T). For example, in the test application, the power supply voltage is 12V, and the rated current is 5A. At this time, based on the total power consumption formula W=P*T=U*I*T*n=12V*5A*1000h*77=4620000J=4620 kilojoules, the test power consumption of the aging test scheme is very large.

[0039] To this end, the embodiment of the present application provides an aging test device for an intelligent electronic switch, which innovatively connects the to-be-tested intelligent electronic switch in series to a load path, so that not only the load can be saved, but also the power consumption in the aging test process can be greatly reduced, and the power consumption can be saved.

[0040] The technical scheme of the present application and how the technical scheme of the present application solves the above technical problems will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described again in some embodiments. The embodiments of the present application will be described below with reference to the drawings.

[0041] For example, Figure 2 is a circuit module schematic diagram of the aging test device for an intelligent electronic switch provided by the embodiment of the present application, Figure 3 is a connection relationship schematic diagram of an intelligent electronic switch and a power supply and a load. As Figure 2 shown, the aging test device can include a power supply 10, a signal source 20, a load 30, a signal acquisition circuit 40 and a to-be-tested intelligent electronic switch set 50. The to-be-tested intelligent electronic switch set 50 includes N intelligent electronic switches, and N is an integer greater than 1. Referring to Figure 3 each intelligent electronic switch includes a power supply end VBAT, a power ground end GND, a load output end OUT and an input end INPUT.

[0042] In the N intelligent electronic switches, at least two of the N intelligent electronic switches are connected in series and connected with the load 30 to form at least one load path, and the at least one load path is connected between the positive terminal and the negative terminal of the power supply 10, wherein the load output terminal OUT of at least one intelligent electronic switch is connected with the power supply terminal VBAT of the next intelligent electronic switch or the power ground terminal GND of the previous intelligent electronic switch or the load. For example, when the N intelligent electronic switches are all connected as high-side switches, the load output terminal OUT of at least one intelligent electronic switch is connected with the power supply terminal VBAT of the next intelligent electronic switch, as shown in Figure 3 For example, when the N intelligent electronic switches are all connected as low-side switches, the load output terminal OUT of at least one intelligent electronic switch is connected with the power ground terminal GND of the previous intelligent electronic switch, as shown in Figure 6 For example, when part of the N intelligent electronic switches are connected as a high-side switch group and the rest are connected as a low-side switch group, the load output terminal OUT of the last high-side switch of the high-side switch group is connected with one end of the load, and the other end of the load is connected with the load output terminal OUT of the first intelligent electronic switch of the low-side switch group, as shown in Figure 8 For example, when part of the N intelligent electronic switches are connected as a high-side switch group and the rest are connected as a low-side switch group, the load output terminal OUT of the last high-side switch of the high-side switch group is connected with one end of the load, and the other end of the load is connected with the load output terminal OUT of the first intelligent electronic switch of the low-side switch group, as shown in

[0043] Optionally, in the embodiments of the present application, the input terminals INPUT of the N intelligent electronic switches are all connected with the signal source 20, and the signal source 20 is used to control the switching state of the N intelligent electronic switches; the signal acquisition circuit 40 is connected with the at least one load path and is used to acquire the continuous signal on the at least one load path, and the aging test result of the to-be-tested intelligent electronic switch set 50 is determined according to the continuous signal.

[0044] For example, in Figure 2 , the intelligent electronic switches are all connected between the power supply 10 and the load 30, and the N intelligent electronic switches form two load paths, at this time, the intelligent electronic switches in the to-be-tested intelligent electronic switch set 50 are connected as high-side switches.

[0045] Optionally, Figure 3 two intelligent electronic switches and are all connected as high-side switches. In Figure 3 , the high-side switch HSS1 and the high-side switch HSS2 are connected in series, that is, the power supply terminal VBAT of the HSS1 is connected with the positive terminal of the power supply 10, the load output terminal OUT of the HSS1 is connected with the power supply terminal VBAT of the HSS2, the load output terminal OUT of the HSS2 is connected with one end of the load, and the power ground terminals GND of the HSS1 and the HSS2 and the other end of the load are all connected with the negative terminal of the power supply 10. It can be understood that the input terminals (INPUT) of the HSS1 and the HSS2 are all connected to the signal source 20Figure 3 The power supply of the intelligent electronic device is not directly connected to the positive terminal of the power supply, but is indirectly connected through other electrical elements.

[0046] It can be understood that in the embodiments of the present application, the power supply terminal of each intelligent electronic device is not directly connected to the positive terminal of the power supply, but is indirectly connected through other electrical elements. For example, a low dropout regulator can be connected between the positive terminal of the power supply 10 and the power supply terminal of the intelligent electronic device. The specific connection mode can be determined according to actual needs, and the embodiments of the present application do not limit the connection mode.

[0047] Optionally, the intelligent electronic device can also include a power switch. In one possible design, the intelligent electronic device is included in an integrated circuit chip, that is, the power switch is built-in the integrated circuit chip. In another possible design, the intelligent electronic device is included in two integrated circuit chips. The elements of the intelligent electronic device other than the power switch are located on the first integrated circuit chip, and the power switch is located on the second integrated circuit chip. The specific circuit modules of the intelligent electronic device are not limited in the embodiments of the present application, and can be selected and set according to actual use scenarios.

[0048] Optionally, in the embodiments, the power switch can be an N-type metal-oxide-semiconductor field-effect transistor (NMOS FET, referred to as NMOS tube), a PMOS tube, a junction field effect transistor (JFET) or an insulated gate bipolar transistor (IGBT), etc. In another possible design of the embodiments, the power switch can also be implemented as a silicon device, or can be implemented using other semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs) or gallium nitride (GaN), etc. The embodiments of the present application do not limit the form of the power switch.

[0049] Optionally, in the embodiments, the signal acquisition circuit 40 is connected with each load path for acquiring the load current on each load path. During the aging test, if a certain intelligent electronic device is disconnected due to aging, the load path where the intelligent electronic device is located will be disconnected, which will prevent the signal acquisition circuit 40 from acquiring the continuous signal, thereby reflecting the aging test result to a certain extent. It can be understood that if the intelligent electronic device with poor aging performance is to be accurately located, the number of series-connected intelligent electronic devices can be reduced for troubleshooting, and the embodiments of the present application do not limit the same.

[0050] Optionally, in the embodiments of the present application, the test power consumption of the aging test device is equal to the power supply voltage multiplied by the load current flowing through each load path and multiplied by the number of load paths.

[0051] For example, in the embodiments of the present application, at least two intelligent electronic switches are connected in series between the power supply 10 and the load 30, so that the load current of the intelligent electronic switches in the same load path is the same during the test, i.e. the power consumption on each load path is W1=UI*I1*T=12V*5A*1000=60kJ, and the total power consumption of the aging test device is W1*Y (total load path), which greatly reduces the power consumption compared to the prior art scheme in which each intelligent electronic switch forms a load path.

[0052] Optionally, in order to further reduce the power consumption of the intelligent electronic switch during the test, the following further shows several circuit module schematic diagrams of the aging test device according to the connection relationship between the intelligent electronic switch and the load.

[0053] For example, Figure 4 is a connection relationship schematic diagram in which the intelligent electronic switch is connected as a high-side switch. In this example, the connection relationship between the intelligent electronic switches can refer to the schematic diagram described above Figure 3 . As shown in Figure 3 and Figure 4 , among the N intelligent electronic switches, the power supply end VBAT of the first intelligent electronic switch is connected to the positive end of the power supply 10, the load output end OUT thereof is connected to the power supply end VBAT of the second intelligent electronic switch, and so on, the load output end OUT of the (N-1)th intelligent electronic switch is connected to the power supply end VBAT of the Nth intelligent electronic switch, and the load output end OUT of the Nth intelligent electronic switch is connected to one end of the load 30. The other end of the load 30 and the power ground end GND of the N intelligent electronic switches are all connected to the negative end of the power supply 10.

[0054] Optionally, in this embodiment, the N intelligent electronic switches are all connected as high-side switches (HSS1 to HSS N), and the N intelligent electronic switches are connected in series one by one, i.e. the load is connected between the load output end OUT of the Nth intelligent electronic switch and the ground potential (the negative end of the power supply 10). Optionally, the input end INPUT of the N intelligent electronic switches is connected to the signal source 20, so that the signal source 20 can simultaneously control the switching state of the N intelligent electronic switches.

[0055] It can be understood that in this embodiment, only when the N intelligent electronic switches are all turned on, there is a load current flowing through the load path. The signal acquisition circuit 40 can acquire the continuous signal at any point of the load path, Figure 4The signal acquisition circuit 40 acquires the continuous signal between the HSS N and the load 30 in this embodiment, and the embodiment is not limited in this regard.

[0056] An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 5 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 6 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 5 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 6 Two intelligent electronic switches are explained in this embodiment. As shown in FIG. 5, Figure 5 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 6 As shown in FIG. 5, in the N intelligent electronic switches, the power supply end VBAT of the N intelligent electronic switches and one end of the load 30 are connected to the positive end of the power supply 10, the other end of the load 30 is connected to the load output end OUT of the first intelligent electronic switch, the power supply ground end GND of the first intelligent electronic switch is connected to the load output end OUT of the second intelligent electronic switch, and so on, the power supply ground end GND of the (N-1)th intelligent electronic switch is connected to the load output end OUT of the Nth intelligent electronic switch, and the power supply ground end GND of the Nth intelligent electronic switch is connected to the negative end of the power supply 10.

[0057] Optionally, in this embodiment, the N intelligent electronic switches are all connected as low-side switches (LSS1 to LSS N), and the N intelligent electronic switches are connected in series, that is, the load 30 is connected between the positive end of the power supply 10 and the load output end OUT of the first intelligent electronic switch. Similarly, the input end INPUT of the N intelligent electronic switches is connected to the signal source 20, so that the signal source 20 can simultaneously control the switching states of the N intelligent electronic switches. In this embodiment, the signal acquisition circuit 40 acquires the continuous signal between the LSS1 and the load 30, and the embodiment is not limited in this regard. Figure 5

[0058] Further, in other embodiments of the present application, the N intelligent electronic switches can also be partially connected as high-side switches and partially connected as low-side switches. An exemplary connection relationship of the intelligent electronic switches, in which part of the intelligent electronic switches are connected as low-side switches and part of the intelligent electronic switches are connected as high-side switches, is shown in FIG. 6. Figure 7 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 8 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 7 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 8 Two intelligent electronic switches are explained in this embodiment. As shown in FIG. 5, Figure 7 An exemplary connection relationship of the intelligent electronic switch as a low-side switch is shown in FIG. 4. Figure 8 ​As shown, among the N intelligent electronic switches, the first n intelligent electronic switches are connected in series between the positive terminal of the power supply 10 and the load 30, and the remaining (N-n) intelligent electronic switches are connected in series between the load 30 and the negative terminal of the power supply 10, where n is an integer greater than or equal to 1 and less than or equal to N.

[0059] For example, referring to Figure 7 As shown, assuming that N is greater than or equal to 3 and n is greater than or equal to 2, and the first n of the N intelligent electronic switches are connected as high-side switches and the remaining (N-n) are connected as low-side switches, that is, the first n intelligent electronic switches are connected in series and then connected in series with the load, and finally connected in series with the remaining (N-n) intelligent electronic switches, that is, the first to the n-th intelligent electronic switches are connected between the positive terminal of the power supply 10 and the load, and the (n+1)th to the Nth intelligent electronic switches are connected between the load and the ground potential (the negative terminal of the power supply 10). In combination Figure 8 As shown, the power supply terminal VBAT of the first intelligent electronic switch (SS1) is connected to the positive terminal of the power supply 10, and the load output terminal OUT is connected to the power supply terminal VBAT of the second intelligent electronic switch (SS2), and so on. The load output terminal OUT of the n-th intelligent electronic switch (SS n) is connected to one end of the load 30, and the other end of the load is connected to the load output terminal OUT of the (n+1)th intelligent electronic switch (SS(n+1)). Correspondingly, the power supply ground terminal GND of the Nth intelligent electronic switch is connected to the load output terminal OUT of the (N-1)th intelligent electronic switch, and the power supply ground terminal GND of the Nth intelligent electronic switch is connected to the negative terminal of the power supply 10.

[0060] In Figure 7 , the input terminals INPUT of the N intelligent electronic switches are also connected to the signal source 20, so that the signal source 20 can control the switching state of the N intelligent electronic switches at the same time. Optionally, when the N intelligent electronic switches are all NMOS tubes, the drive circuit of the first to the n-th intelligent electronic switches may need a voltage boosting module to ensure that the first to the n-th intelligent electronic switches can be normally driven. Among them, Figure 7 In this embodiment, the signal acquisition circuit 40 is used to collect the signal between the HSS n and the load 30, and this embodiment is not limited.

[0061] It can be understood that in Figure 8 , two intelligent electronic switches SS are used to explain and illustrate, the first intelligent electronic switch is connected as a high-side switch HSS, and the second intelligent electronic switch is connected as a low-side switch LSS.

[0062] It can be understood that in Figures 3 to 8In the embodiment shown, when the intelligent electronic switches in the set of intelligent electronic switches 50 are all connected in series on the same load path, the power consumption of the aging test device is 1 / N of the existing test scheme, that is, the more the number of intelligent electronic switches to be tested, the more power consumption the aging test device of the present application can save, and the more significant the power saving.

[0063] For example, in other embodiments of the present application, the number of loads in the aging test device can be multiple, and N intelligent electronic switches can form multiple load paths with multiple loads. For example, Figures 9A to 9C is a schematic diagram of several possible connection relationships between intelligent electronic switches and loads in the aging test device provided by embodiments of the present application. As shown in Figures 9A to 9C In this embodiment, the number of loads is x, N intelligent electronic switches form x load paths with x loads, at least one of the x load paths includes at least two intelligent electronic switches connected in series, and x is an integer greater than or equal to 2 and less than or equal to (N-1).

[0064] For example, Figures 9A to 9C In the embodiment shown in FIG. 3, the number of loads in the aging test device is 3, and N intelligent electronic switches form 3 load paths with 3 loads. For example, in Figure 9A In the embodiment shown in FIG. 3, the N intelligent electronic switches are all connected as high-side switches (HSS1 to HSS N), wherein HSS1 to HSS n form a load path 1 with the load R1, HSS(n+1) to HSS(n+m) form a load path 2 with the load R2, and HSS(n+m+1) to HSS N form a load path 3 with the load R3.

[0065] In the embodiment shown in FIG. 3, Figure 9B In the embodiment shown in FIG. 3, the N intelligent electronic switches are all connected as low-side switches (LSS1 to LSS N), and similarly, the load R1 forms a load path 1 with LSS1 to LSS n, the load R2 forms a load path 2 with LSS(n+1) to LSS(n+m), and the load R3 forms a load path 3 with LSS(n+m+1) to LSS N.

[0066] In the embodiment shown in FIG. 3, Figure 9CIn the N intelligent electronic switches and 3 loads form the load path, the first load path in the n intelligent electronic switch is connected as a high side switch, the second load path in the m intelligent electronic switch is connected as a low side switch, the first k intelligent electronic switch in the third load path is connected as a high side switch, and the remaining part is connected as a low side switch. For example, SS1 to SS n and load R1 form load path 1, load R2 and SS(n+1) to SS(n+m) form load path 2, and SS(n+m+1) to SS(n+m+k) are connected in series and then connected to load R3 and SS(n+m+k+1) to SS N form load path 3.

[0067] Optionally, in Figures 9A to 9C In the N intelligent electronic switches and 3 loads form the load path, the first load path in the n intelligent electronic switch is connected as a high side switch, the second load path in the m intelligent electronic switch is connected as a low side switch, the first k intelligent electronic switch in the third load path is connected as a high side switch, and the remaining part is connected as a low side switch. For example, SS1 to SS n and load R1 form load path 1, load R2 and SS(n+1) to SS(n+m) form load path 2, and SS(n+m+1) to SS(n+m+k) are connected in series and then connected to load R3 and SS(n+m+k+1) to SS N form load path 3.

[0068] Optionally, the above embodiments introduce the connection relationship between the intelligent electronic switch and the load through the schematic diagram. Different connection relationships may have different power consumptions of the aging test device. Generally, the fewer the load paths, the lower the power consumption of the aging test device. However, if an abnormality occurs during the aging test process, the process of troubleshooting the abnormality is more complex. Therefore, the tester can select the test architecture based on actual needs.

[0069] Optionally, in order to determine the aging test result of the to-be-tested intelligent electronic switch set 50, in the embodiments of the present application, the signal acquisition circuit 40 is configured to acquire the continuity signal on each load path, and when the continuity signal indicates that there is a load current on the corresponding load path, it is determined that the aging test result of the intelligent electronic switch connected to the load path is normal, and when the continuity signal indicates that there is no load current on the corresponding load path, it is determined that the aging test result of at least one intelligent electronic switch connected to the load path is abnormal.

[0070] Optionally, the signal acquisition circuit 40 includes an oscilloscope or a multimeter, and the continuity signal is measured at the load output end OUT of the intelligent electronic switch using the oscilloscope or the multimeter.

[0071] For example, during the aging test process, the tester can connect the two ends of the oscilloscope or the multimeter to the load path to test whether there is a load current on the load path. If yes, it is considered that the load path is connected, and the current aging test result is normal. If not, it is considered that the load path has an open circuit, indicating that at least one intelligent electronic switch in the load path may have an open circuit due to aging, that is, the aging test result of at least one intelligent electronic switch connected to the load path is abnormal.

[0072] It can be understood that in actual applications, the signal acquisition circuit 40 can also acquire the voltage drop across the intelligent electronic switch or the voltage drop across the load, and then determine the aging test result of at least one intelligent electronic switch on the load path according to the voltage drop across the intelligent electronic switch or the voltage drop across the load.

[0073] Optionally, in the embodiment of the present application, the signal source 20 provides a test signal to the N intelligent electronic switches when receiving the trigger signal, so as to start the aging test on the N intelligent electronic switches.

[0074] For example, the signal source 20 is configured to provide a test signal for performing the aging test. The signal source 20 is, for example, a power supply signal provided by a driver, which does not exceed the maximum input voltage of the driver. In the present application, the test signal provided by the signal source 20 can be set according to actual test requirements, for example, a high-level signal, a sinusoidal signal, a square wave signal, a rectangular pulse, a Gaussian pulse, or other periodic signals, which are not limited in the present application.

[0075] Optionally, in order to improve the intelligence of the aging test device, the aging test device can further include a timing device to time the test time of the aging test device, and / or a counting device to count the number of working cycles of the aging test device. For example, Figure 10 is a structural schematic diagram of the aging test device provided by another embodiment of the present application.

[0076] In a possible design, as shown in Figure 10 the aging test device further includes a timing circuit 60 connected with the signal source 20.

[0077] As an example, the timing circuit 60 is used to start timing and output a timing signal when the signal source 20 outputs the test signal. Optionally, the timing circuit 60 can output a timing arrival reminder signal when the timing reaches a preset time length.

[0078] For example, the enable end of the timing circuit 60 is connected with the signal source 20, and the signal source 20 is connected with the input end INPUT of the N intelligent electronic switches. In this way, after the signal source 20 outputs the test signal, the N intelligent electronic switches are turned on, the load path where the N intelligent electronic switches are located is connected, the aging test device starts to perform the aging test, and at the same time, the timing circuit 60 starts to time, i.e., the timing circuit 60 can time the test time of the aging test device.

[0079] Optionally, the timing circuit 60 continuously outputs a timing signal during the timing process, so that the tester can monitor the test progress at any time based on the timing signal. Moreover, multiple test time points can be preset in the timing circuit 60, so that the timing circuit 60 outputs an arrival reminder signal when each test time point is reached, so that the tester can keep track of the timing and check the test status.

[0080] As another example, the timing circuit 60 is used to time the first level of the test signal output by the signal source 20 and output a timing signal. For example, if the test signal is a periodic square wave signal (high and low level signal), and the intelligent electronic switch turns on when it receives a high level signal and turns off when it receives a low level signal, then in this embodiment, the timing circuit 60 can start timing when it first receives a high level signal and stop timing when it receives a low level signal. Correspondingly, it can accumulate timing when it receives a high level signal again, until the total time reaches a preset time threshold, at which point it outputs a timing completion signal so that the tester can know the effective test time of the aging test device.

[0081] In another possible design, such as Figure 10 As shown, the aging test apparatus also includes a counting circuit 70, which is connected to the signal source 20. The counting circuit 70 is used to count the periods of the test signal output by the signal source 20 and output a counting signal. In this possible design, the test signal is a periodic signal. Therefore, the counting circuit can count the number of periods of the test signal after the aging test process begins, and then use it to determine the total test duration or effective test duration, or for other purposes. This embodiment does not limit these uses.

[0082] It is understood that the aging test device for smart electronic switches provided in this application embodiment can also be applied to multi-chip testing processes in other fields, and this application embodiment does not limit it.

[0083] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0084] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An aging test device for intelligent electronic switches, characterized in that, It includes a power supply, signal source, load, signal acquisition circuit, and a set of intelligent electronic switches under test; The set of intelligent electronic switches under test includes N intelligent electronic switches, where N is an integer greater than 1. Each of the N intelligent electronic switches includes a power supply terminal, a power ground terminal, a load output terminal, and an input terminal. In the N intelligent electronic switches, at least two of the N intelligent electronic switches are connected in series and then connected to the load to form at least one load path, and the at least one load path is connected between the positive and negative terminals of the power supply. The load output terminal of at least one intelligent electronic switch is connected to the power supply terminal of the next intelligent electronic switch or the power ground terminal of the previous intelligent electronic switch or the load. The input terminals of the N intelligent electronic switches are all connected to the signal source, and the signal source is used to control the switching state of the N intelligent electronic switches. The signal acquisition circuit is connected to the at least one load path and is used to acquire the connectivity signal on the at least one load path, and determine the aging test result of the set of smart electronic switches under test based on the connectivity signal.

2. The aging test apparatus according to claim 1, characterized in that, In the N intelligent electronic switches, the power supply terminal of the first intelligent electronic switch is connected to the positive terminal of the power supply, its load output terminal is connected to the power supply terminal of the second intelligent electronic switch, and so on. The load output terminal of the (N-1)th intelligent electronic switch is connected to the power supply terminal of the Nth intelligent electronic switch, the load output terminal of the Nth intelligent electronic switch is connected to one end of the load, and the other end of the load and the power ground terminal of the N intelligent electronic switches are all connected to the negative terminal of the power supply.

3. The aging test apparatus according to claim 1, characterized in that, In the N intelligent electronic switches, the power supply terminal of each of the N intelligent electronic switches and one end of the load are both connected to the positive terminal of the power supply. The other end of the load is connected to the load output terminal of the first intelligent electronic switch. The power ground terminal of the first intelligent electronic switch is connected to the load output terminal of the second intelligent electronic switch, and so on. The power ground terminal of the (N-1)th intelligent electronic switch is connected to the load output terminal of the Nth intelligent electronic switch, and the power ground terminal of the Nth intelligent electronic switch is connected to the negative terminal of the power supply.

4. The aging test apparatus according to claim 1, characterized in that, In the N intelligent electronic switches, the first n intelligent electronic switches are connected in series between the positive terminal of the power supply and the load, and the remaining (Nn) intelligent electronic switches are connected in series between the load and the negative terminal of the power supply, where n is an integer greater than or equal to 1 and less than or equal to N.

5. The aging test apparatus according to claim 1, characterized in that, The number of loads is x, and the N smart electronic switches and the x loads form x load paths. At least one of the x load paths includes at least two smart electronic switches connected in series, where x is an integer greater than or equal to 2 and less than or equal to (N-1).

6. The aging test apparatus according to any one of claims 1 to 5, characterized in that, The signal acquisition circuit is used to acquire the connection signal on each load path, and when the connection signal indicates that there is a load current on the corresponding load path, it determines that the aging test result of the smart electronic switch connected to the load path is normal, and when the connection signal indicates that there is no load current on the corresponding load path, it determines that the aging test result of at least one smart electronic switch connected to the load path is abnormal.

7. The aging test apparatus according to claim 6, characterized in that, The signal acquisition circuit includes an oscilloscope or a multimeter, and the connected signal is obtained by measuring the load output terminal of the intelligent electronic switch using the oscilloscope or the multimeter.

8. The aging test apparatus according to any one of claims 1 to 5, characterized in that, The power consumption of the aging test device is equal to the power supply voltage multiplied by the load current flowing through each load path, and multiplied by the number of load paths.

9. The aging test apparatus according to any one of claims 1 to 5, characterized in that, When the signal source receives a trigger signal, it provides a test signal to the N smart electronic switches to initiate an aging test on the N smart electronic switches.

10. The aging test apparatus according to any one of claims 1 to 5, characterized in that, It also includes a timing circuit, which is connected to the signal source. The timing circuit is used to start timing and output a timing signal when the signal source outputs a test signal, or the timing circuit is used to time the first level in the test signal output by the signal source and output a timing signal. And / or, the aging test apparatus further includes a counting circuit connected to the signal source, the counting circuit being used to count the period of the test signal output by the signal source and output a counting signal.

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