Packaging structure for antistatic semiconductor chip

Abstract

The utility model discloses a packaging structure for an antistatic semiconductor chip, which comprises a base, the top of the base is fixedly connected with an upper sealing cover, two sides of the base are fixedly connected with side sealing covers, the side sealing covers on the two sides are used for sealing a space between the base and the upper sealing cover, and the surfaces of the base and the upper sealing cover are provided with antistatic coatings. A bottom pad is arranged between the base and the upper sealing cover and fixedly connected to the base, a chip is arranged on the bottom pad and located between the base and the upper sealing cover, a plurality of pins distributed at equal intervals are arranged on the two sides of the upper sealing cover, the pins penetrate through the upper sealing cover and extend into the space between the base and the upper sealing cover, and the pins are electrically connected with the chip through leads. According to the packaging structure for the antistatic semiconductor chip, the pins in the packaging structure are protected by arranging the protective sleeves, and the protective sleeves can provide a physical barrier, so that the direct contact between the pins and the external environment is effectively reduced, and the damage risk is reduced.

Description

TECHNICAL FIELD

[0001] The utility model relates to the technical fields of semiconductor devices, in particular to a packaging structure for antistatic semiconductor chip. BACKGROUND

[0002] The semiconductor chip packaging structure is a key component for protecting the chip and realizing the connection between the chip and external circuit. It is usually composed of a packaging shell, pins, solder balls, etc., and has functions of placing, fixing, sealing, protecting and heat conducting. The development trend of packaging technology is towards "light, thin, short and small" to improve packaging efficiency, pin density and reliability. Common packaging technologies include DIP, QFP, BGA, etc.

[0003] The existing packaging structure for antistatic semiconductor chip plays an antistatic role by setting an antistatic coating outside the packaging structure, but the chip pins are usually fragile and prone to physical damage such as bending and breaking during transportation, installation or use. However, the existing packaging structure for chip does not have a protection function for chip pins, which leads to damage to chip pins. Therefore, we propose a packaging structure for antistatic semiconductor chip. SUMMARY

[0004] To solve the defects of the prior art, the utility model provides a packaging structure for antistatic semiconductor chip.

[0005] To solve the above technical problems, the utility model provides the following technical scheme:

[0006] The utility model relates to a packaging structure for antistatic semiconductor chip, which comprises a base, an upper cover fixedly connected to the top of the base, side covers fixedly connected to both sides of the base, the side covers on both sides being used to seal the space between the base and the upper cover, and an antistatic coating provided on the surface of the base and the upper cover.

[0007] A bottom pad is provided between the base and the upper cover, the bottom pad is fixedly connected to the base, a chip is provided on the bottom pad, the chip is located between the base and the upper cover, a plurality of pins equally distributed are provided on both sides of the upper cover, the pins pass through the upper cover and extend into the space between the base and the upper cover, the pins and the chip are electrically connected through lead wires, a protective sleeve is provided on both sides of the base, the lower end of the pin extends into the protective sleeve, a bottom plate is fixedly installed between the two protective sleeves, the base is placed on the bottom plate, a sealing mechanism is provided in the protective sleeve, and the sealing mechanism is used to seal the gap between the protective sleeve and the plurality of pins.

[0008] As a preferred technical scheme of the utility model, the base, the upper cover and the side covers are all made of ceramic material.

[0009] As a preferred technical scheme of the utility model, the bottom pad is of epoxy resin material, and the bottom pad is arranged in an inverted U shape.

[0010] As a preferred technical scheme of the utility model, a groove is formed in the bottom of the base, and the groove penetrates the two side covers at both ends.

[0011] As a preferred technical scheme of the utility model, a sealing ring is arranged between the upper cover and the pins.

[0012] As a preferred technical scheme of the utility model, heat-conducting silicone grease is arranged between the chip and the upper cover.

[0013] As a preferred technical scheme of the utility model, the sealing mechanism comprises a sealing strip, the sealing strip is arranged in the protective sleeve and surrounds the plurality of pins, the two ends of the sealing strip are spliced together, a plurality of filling blocks are fixedly connected to the sealing strip at equal intervals, the filling blocks are arranged between adjacent pins, and the sealing strip and the plurality of filling blocks cooperate to seal the gap between the protective sleeve and the plurality of pins.

[0014] As a preferred technical scheme of the utility model, the two ends of the sealing strip are fixedly connected with protrusions at the top.

[0015] As a preferred technical scheme of the utility model, dryers are attached to the bottom of the filling blocks, and the dryers are fiber dryers.

[0016] The utility model has the advantages of:

[0017] The packaging structure for the antistatic semiconductor chip protects the pins in the protective sleeve, the protective sleeve provides a physical barrier, effectively reduces the direct contact of the pins with the external environment, and reduces the risk of damage. The upper port of the protective sleeve is sealed by the sealing strip and the plurality of filling blocks, which can prevent external dust, water vapor or other impurities from entering the protective sleeve. In addition, the bottom of the filling blocks is attached with dryers, the dryers can absorb the moisture in the air in the protective sleeve, keep the protective sleeve dry, slow down the oxidation and corrosion process of the pins, prolong the service life of the pins, and keep the pins in good conductivity. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings are used to provide a further understanding of the utility model, and constitute a part of the specification, are used to explain the utility model together with embodiments of the utility model, and do not constitute a limitation to the utility model. In the drawings:

[0019] Figure 1 It is a structure schematic view of the packaging structure for the antistatic semiconductor chip of the utility model;

[0020] Figure 2 is a sectional view of the packaging structure for the anti-static semiconductor chip of the utility model,

[0021] Figure 3 is a partial structure enlarged schematic view of the protective sleeve and the pin of the packaging structure for the anti-static semiconductor chip of the utility model,

[0022] Figure 4 is an explosion schematic view of the pin, the sealing strip and the protective sleeve of the packaging structure for the anti-static semiconductor chip of the utility model.

[0023] In the drawing: base 1, upper cover 2, side cover 3, bottom pad 4, chip 5, pin 6, lead 7, protective sleeve 8, bottom plate 9, groove 10, sealing ring 11, heat-conducting silicone grease 12, sealing strip 13, filling block 14, protruding block 15, desiccant 16. DETAILED DESCRIPTION

[0024] The preferred embodiments of the utility model are described below in combination with the drawings, and it should be understood that the preferred embodiments described here are only used for illustrating and explaining the utility model, and are not used for limiting the utility model.

[0025] Embodiment: as shown in Figure 1 , Figure 2 , Figure 3 and Figure 4 indicated, the packaging structure for the anti-static semiconductor chip of the utility model comprises a base 1, the top of the base 1 is fixedly connected with an upper cover 2, both sides of the base 1 are fixedly connected with side covers 3, and the side covers 3 on both sides are used for sealing the space between the base 1 and the upper cover 2; the surfaces of the base 1 and the upper cover 2 are provided with anti-static coatings. A bottom pad 4 is arranged between the base 1 and the upper cover 2, the bottom pad 4 is fixedly connected to the base 1, a chip 5 is arranged on the bottom pad 4, and the chip 5 is located between the base 1 and the upper cover 2; by arranging the anti-static coating, the chip 5 can be prevented from being damaged by static electricity. The anti-static coating is an aluminum oxide anti-static coating 2, the aluminum oxide coating has a certain conductivity, can effectively prevent the accumulation of static electricity on the surface of the chip, and thus reduces the risk of damage to the chip due to static electricity.

[0026] The upper cover 2 is provided with a plurality of equally distributed pins 6 on both sides, the pins 6 pass through the upper cover 2 and extend into the space between the base 1 and the upper cover 2, the pins 6 are electrically connected with the chip 5 through the lead wires 7, the base 1 is provided with a protective sleeve 8 on both sides, the lower end of the pin 6 extends into the protective sleeve 8, the two protective sleeves 8 are fixedly installed with a bottom plate 9, the base 1 is placed on the bottom plate 9, and the protective sleeve 8 is provided with a sealing mechanism. The protective sleeve 8 can provide a physical barrier to effectively reduce the direct contact of the pins 6 with the external environment, thereby reducing the risk of damage. When the chip 5 is stored, the base 1 is placed on the bottom plate 9, and the bottom plate 9 is used to bear the overall gravity of the structure, so that the bottom end of the pin 6 is not bent under stress.

[0027] The base 1, the upper cover 2 and the side cover 3 are all made of ceramic material, which has good heat conductivity and helps to improve the heat dissipation efficiency of the chip 5 inside. The bottom pad 4 is made of epoxy resin material and is in an inverted U shape. The epoxy resin material is a kind of high molecular material, which can effectively conduct heat from high temperature area to low temperature area. The epoxy resin with high thermal conductivity serves as a support structure for the chip 5, which helps to improve the heat dissipation effect. At the same time, the U-shaped bottom pad 4 has a gap below for air circulation, which helps to dissipate heat from the bottom pad 4.

[0028] The base 1 is provided with a groove 10 at the bottom, and the groove 10 penetrates the two side covers 3 at both ends. When the chip 5 is installed on the PCB, the groove 10 is arranged between the base 1 and the PCB, so that air can flow through the gap between the PCB and the base 1, thereby improving the heat dissipation rate of the PCB and the base 1.

[0029] The sealing ring 11 is arranged between the upper cover 2 and the pins 6 to enhance the sealing performance between the upper cover 2 and the pins 6. The heat-conducting silicone grease 12 is arranged between the chip 5 and the upper cover 2, which can absorb the heat of the chip 5 and accelerate the heat dissipation of the chip 5.

[0030] The sealing mechanism includes a sealing strip 13, which is arranged in the protective sleeve 8 and surrounds the plurality of pins 6. The two ends of the sealing strip 13 are spliced together, and a plurality of equally distributed filling blocks 14 are fixedly connected to the sealing strip 13. The filling blocks 14 are arranged between adjacent pins 6, and the sealing strip 13 and the plurality of filling blocks 14 cooperate to seal the gap between the protective sleeve 8 and the plurality of pins 6. The two ends of the sealing strip 13 are fixedly connected with the protrusions 15.

[0031] When the chip 5 is stored, the sealing strip 13 cooperates with the plurality of filling blocks 14 to seal the upper port of the protective sleeve 8, so that external dust, water vapor or other impurities cannot enter the protective sleeve 8, and meanwhile, the bottom of each filling block 14 is adhered with a desiccant 16, which is a fiber desiccant. The desiccant 16 can absorb the moisture in the air in the protective sleeve 8, so that the protective sleeve 8 is kept dry, the oxidation and corrosion process of the lead 6 is slowed down, the service life of the lead 6 is prolonged, and the lead 6 is kept in good electric conductivity.

[0032] When the chip 5 needs to be used, the sealing strip 13 is taken out of the protective sleeve 8, the two ends of the sealing strip 13 are pulled out of the protective sleeve 8 by pulling the protruding block 15 upward, the sealing strip 13 is unfolded and taken out, and then the protective sleeve 8 can be separated from the chip 5, and meanwhile, the protective sleeve 8 and the sealing strip 13 can be recycled and reused.

[0033] Finally, it should be noted that: the above only for the preferred embodiments of the present application, and not for limiting the present application, although the present application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, it still can modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features. Any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A packaging structure for an antistatic semiconductor chip, comprising a base (1), characterized in that, The base (1) is fixedly connected to the top of the upper cover (2), and the base (1) is fixedly connected to the sides of the sides of the side cover (3). The side cover (3) on both sides is used to seal the space between the base (1) and the upper cover (2). The surfaces of the base (1) and the upper cover (2) are provided with an antistatic coating. A base pad (4) is provided between the base (1) and the upper cover (2). The base pad (4) is fixedly connected to the base (1). A chip (5) is provided on the base pad (4). The chip (5) is located between the base (1) and the upper cover (2). Multiple pins (6) are provided on both sides of the upper cover (2). The pins (6) pass through the upper cover (2) and extend into the space between the base (1) and the upper cover (2). The pins (6) and the chip (5) are electrically connected by leads (7). Protective sleeves (8) are provided on both sides of the base (1). The lower ends of the pins (6) extend into the protective sleeves (8). A base plate (9) is fixedly installed between the two protective sleeves (8). The base (1) is placed on the base plate (9). A sealing mechanism is provided inside each protective sleeve (8). The sealing mechanism is used to seal the gap between the protective sleeve (8) and the multiple pins (6).

2. The antistatic semiconductor chip packaging structure according to claim 1, characterized in that, The base (1), the upper cover (2) and the side cover (3) are all made of ceramic.

3. The antistatic semiconductor chip packaging structure according to claim 2, characterized in that, The base pad (4) is made of epoxy resin and is configured as an inverted U-shape.

4. The antistatic semiconductor chip packaging structure according to claim 3, characterized in that, The base (1) has a groove (10) at the bottom, and the two ends of the groove (10) pass through the side covers (3) on both sides.

5. The antistatic semiconductor chip packaging structure according to claim 4, characterized in that, A sealing ring (11) is provided between the upper cover (2) and the pin (6).

6. The antistatic semiconductor chip packaging structure according to claim 5, characterized in that, Thermal grease (12) is provided between the chip (5) and the upper cover (2).

7. The antistatic semiconductor chip packaging structure according to claim 6, characterized in that, The sealing mechanism includes a sealing strip (13), which is disposed inside the protective sleeve (8) and surrounds multiple pins (6). The two ends of the sealing strip (13) are joined together. Multiple equidistant filler blocks (14) are fixedly connected to the sealing strip (13). The filler blocks (14) are disposed between adjacent pins (6). The sealing strip (13) and the multiple filler blocks (14) cooperate to seal the gap between the protective sleeve (8) and the multiple pins (6).

8. The antistatic semiconductor chip packaging structure according to claim 7, characterized in that, Both ends of the sealing strip (13) are fixedly connected with protrusions (15).

9. The antistatic semiconductor chip packaging structure according to claim 8, characterized in that, The bottom of each filler block (14) is adhered with a desiccant (16), which is a fiber desiccant.

Images