Display substrate and display device

Abstract

The utility model provides a display substrate and a display device, a plurality of sub-pixels are defined through a pixel defining layer, each sub-pixel comprises a light-emitting element, each light-emitting element comprises a first electrode, a spacer region between adjacent first electrodes is filled through a continuous filling layer, and a pixel partition structure is arranged in the filling layer. At least one of a plurality of sub-functional film layers in a light-emitting functional layer can be disconnected, so that transverse electrical crosstalk between pixels is reduced, and the display quality is improved; meanwhile, the first electrode is covered by the first part, overlapped with the first electrode, of the pixel limiting layer, so that after the first electrode is manufactured and when the pixel partition structure is manufactured, the first part can play a role in protecting the surface of the first electrode, and the surface of the first electrode is prevented from being corroded when the pixel partition structure is manufactured.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] With the development of display technology, organic light-emitting diode (OLED) display products have occupied the high-end display product market in recent years due to their excellent picture quality and wide range of applications. As a result, users' demands for the display performance of OLED display products are also increasing. Utility Model Content

[0003] In view of this, the purpose of this application is to provide a display substrate and a display device that can improve display quality.

[0004] To achieve the above objectives, in a first aspect, this application provides a display substrate, comprising:

[0005] Substrate;

[0006] A pixel defining layer, located on the substrate, includes multiple pixel openings defining multiple sub-pixels;

[0007] Multiple sub-pixels are located on the substrate. Each sub-pixel includes a light-emitting element. The light-emitting element includes a light-emitting functional layer and a first electrode located between the light-emitting functional layer and the substrate. Adjacent first electrodes are separated by a spacer region. The light-emitting functional layer includes multiple sub-functional film layers.

[0008] The pixel defining layer includes a first portion overlapping the first electrode, the first portion being located on the side of the first electrode away from the substrate.

[0009] A filling layer, located on the substrate, includes a third portion and a fourth portion. The third portion fills the spacer region, and the fourth portion is located on the side of the third portion away from the substrate. The orthographic projection of the fourth portion on the substrate overlaps with the orthographic projection of the first portion on the substrate.

[0010] The pixel defining layer further includes a second portion, which is located on the side of the first portion and the fourth portion away from the substrate, and the orthographic projections of the first portion and the fourth portion on the substrate are located within the orthographic projections of the second portion on the substrate.

[0011] A pixel partition structure is located between the second part and the third part, wherein the orthographic projection of the pixel partition structure on the substrate is located within the orthographic projection of the filling layer on the substrate, and at least one of the plurality of sub-functional film layers in the light-emitting functional layer is disconnected at the location of the pixel partition structure.

[0012] In a second aspect, this application provides a display device including a display substrate as described in the first aspect.

[0013] As can be seen from the above description, the display substrate and display device provided in this application define a plurality of sub-pixels by a pixel defining layer. Each sub-pixel includes a light-emitting element, and the light-emitting element includes a first electrode. The gap between adjacent first electrodes is filled by a continuous filling layer, and a pixel isolation structure is provided in the filling layer. This can disconnect at least one of the plurality of sub-functional film layers in the light-emitting functional layer, thereby reducing lateral electrical crosstalk between pixels and improving display quality. At the same time, the first part of the pixel defining layer overlapping with the first electrode covers the first electrode. In this way, after the first electrode is fabricated, when the pixel isolation structure is fabricated, the first part can protect the surface of the first electrode and prevent the surface of the first electrode from being eroded during the fabrication of the pixel isolation structure. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1A A schematic diagram of an exemplary Single structure light-emitting element according to an embodiment of this application is shown.

[0016] Figure 1B A schematic diagram of a light-emitting element with an exemplary Tandem structure according to an embodiment of this application is shown.

[0017] Figure 2A A schematic diagram of an exemplary display substrate according to an embodiment of this application is shown.

[0018] Figure 2B A schematic diagram of an exemplary display substrate according to an embodiment of this application is shown.

[0019] Figure 2C A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0020] Figure 2DA schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0021] Figure 2E A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0022] Figure 2F A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0023] Figure 2G A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0024] Figure 2H A schematic diagram showing the change in grain height on the surface of an exemplary first electrode according to an embodiment of this application after being eroded by a pharmaceutical solution.

[0025] Figure 2I A schematic diagram of the initial lattice morphology of an exemplary first electrode surface according to an embodiment of this application is shown.

[0026] Figure 2J A schematic diagram of the morphology of the surface lattice of an exemplary first electrode according to an embodiment of this application after being eroded by a chemical solution is shown.

[0027] Figure 3A A schematic diagram of an exemplary display substrate according to an embodiment of this application is shown.

[0028] Figure 3B A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0029] Figure 3C A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0030] Figure 3D A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0031] Figure 3E A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0032] Figure 3F A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0033] Figure 4A A schematic diagram of an exemplary display substrate according to an embodiment of this application is shown.

[0034] Figure 4B A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0035] Figure 4CA schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0036] Figure 4D A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0037] Figure 4E A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0038] Figure 4F A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0039] Figure 5A A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0040] Figure 5B A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0041] Figure 5C A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0042] Figure 5D A schematic diagram of yet another exemplary display substrate according to an embodiment of this application is shown.

[0043] Figure 6 A schematic diagram of an exemplary display device according to an embodiment of this application is shown.

[0044] Figure 7 A schematic flowchart of an exemplary display substrate fabrication method according to an embodiment of this application is shown. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0046] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0047] As described in the background section, with the development of display technology, organic light-emitting diode (OLED) display products have occupied the high-end display product market in recent years due to their excellent picture quality and wide range of applications. Consequently, users' demands for the display performance of OLED display products are also increasing.

[0048] However, OLED displays suffer from electrical crosstalk. OLED devices contain functional material layers with high lateral carrier mobility, such as the charge generation layer (CGL). During OLED fabrication, open masks are typically used to create these CGLs. Because these functional material layers have a continuous planar structure, charges can move freely within the plane. This can easily lead to abnormal emission from pixels surrounding the currently emitting pixel, resulting in poor color gamut and impacting display quality.

[0049] To improve the current utilization efficiency of OLEDs and reduce power consumption, compared to traditional single-layer pixel structures, tandem OLED pixel structures connect multiple OLED devices in series through organic material layers to form high-efficiency OLED devices. These structures are characterized by higher efficiency, lower current consumption, and longer lifespan. However, tandem OLED displays suffer from more severe electrical crosstalk.

[0050] Figure 1A A schematic diagram of an exemplary Single structure light-emitting element 100a according to an embodiment of this application is shown.

[0051] like Figure 1AAs shown, the light-emitting element 100a includes a first electrode 102, a light-emitting functional layer 104, and a second electrode 106. The light-emitting functional layer 104 is located between the first electrode 102 and the second electrode 106. When the first electrode 102 and the second electrode 106 are working, an electric field is generated between them, and the light-emitting functional layer 104 emits light under the action of the electric field. The first electrode 102 can be an anode, and the second electrode 106 can be a cathode (CTD).

[0052] In the light-emitting element 100a, the light-emitting functional layer 104 includes multiple sub-functional film layers 1042, including a hole injection layer (HTL) 1042, a light emitting layer (EL) 1044, and an electron transport layer (ETL) 1046. When current passes through, the first electrode 102 emits holes, and the second electrode 106 emits electrons. These holes and electrons meet and recombine in the light emitting layer 1044 to generate light.

[0053] Figure 1B A schematic diagram of an exemplary tandem structure light-emitting element 100b according to an embodiment of this application is shown.

[0054] like Figure 1B As shown, compared to the single-structure light-emitting element 100a, the tandem-structure light-emitting element 100b utilizes a charge-generating layer 1048 to connect the upper and lower light-emitting layers (e.g., the first light-emitting layer 1044 and the second light-emitting layer 1050) in series, forming a series-structured light-emitting element. When current flows, some holes and electrons recombine and emit light in one of the two light-emitting layers (e.g., the first light-emitting layer 1044), while other holes and electrons pass through the charge-generating layer 1048 and recombine and emit light again in the other light-emitting layer (e.g., the second light-emitting layer 1050). Therefore, compared to the single-structure light-emitting element 100a, the tandem-structure light-emitting element 100b significantly reduces the luminous current of the light-emitting element at the same luminous intensity, thus improving the lifespan of the light-emitting element. Therefore, the tandem-structure light-emitting element has advantages such as long lifespan, low power consumption, and high brightness.

[0055] However, for products using tandem structure light-emitting elements, the charge generation layer has strong conductivity and the light-emitting functional layers of adjacent sub-pixels are connected. Therefore, the charge generation layer is prone to crosstalk between adjacent sub-pixels, which seriously affects the display quality.

[0056] Figure 2AA schematic diagram of an exemplary display substrate 200a according to an embodiment of this application is shown.

[0057] like Figure 2A As shown, the display substrate 200a includes a substrate 202, a pixel defining layer 204, and a plurality of sub-pixels located on the substrate 202. The pixel defining layer 204 defines a plurality of pixel openings 206 for the plurality of sub-pixels. The pixel defining layer 204 may include a plurality of sub-layers sequentially stacked along a direction away from the substrate 202, and the plurality of sub-layers can be formed simultaneously on the substrate 202 in a single patterning process.

[0058] Each of the multiple sub-pixels includes a light-emitting element (e.g., light-emitting element 208a and light-emitting element 208b), the light-emitting element including a light-emitting functional layer 210 and a first electrode 212 located between the light-emitting functional layer 210 and the substrate 202, the first electrode 212 may be an anode.

[0059] The light-emitting functional layer 210 includes multiple sub-functional film layers, including a charge-generating layer 2102 and light-emitting layers (e.g., a first light-emitting layer 2104 and a second light-emitting layer 2106) located on the upper and lower sides of the charge-generating layer 2102. The charge-generating layer 2102 of the light-emitting element can be an integral structure, fabricated using an open mask.

[0060] In the display substrate 200a, the light-emitting functional layers 210 of adjacent sub-pixels are connected, while the charge-generating layer 2102 has strong conductivity, allowing charges to move freely within a planar range. Therefore, the charge-generating layer 2102 easily leads to lateral crosstalk between adjacent sub-pixels. For example, crosstalk between adjacent sub-pixels refers to the situation where a light-emitting element that should not emit light emits light. Figure 2A As shown, if the desired situation is that the light-emitting element 208a emits light while the light-emitting element 208b does not emit light, but due to the conductivity of the charge generation layer 2102, the light-emitting element 208b also emits light, thus forming crosstalk and affecting the display quality.

[0061] To solve the crosstalk problem between adjacent sub-pixels, a pixel isolation structure can be set between adjacent sub-pixels, and at least one of the multiple sub-functional film layers in the light-emitting functional layer can be disconnected at the location of the pixel isolation structure, thereby avoiding crosstalk between adjacent sub-pixels caused by the highly conductive charge generation layer.

[0062] Figure 2B A schematic diagram of an exemplary display substrate 200b according to an embodiment of this application is shown.

[0063] like Figure 2BAs shown, in some embodiments, when fabricating the pixel separation structure, the materials for fabricating the first electrode 212 and the protective layer 214 of the first electrode 212 can be deposited on one side of the substrate 202. The materials for fabricating the first electrode 212 may include a TAT stacked structure (Ti / TiN / Al / TiN, titanium / titanium nitride / aluminum / titanium nitride) and indium tin oxide (ITO), while the materials for fabricating the protective layer 214 may include silicon nitride (SiN). x ) and silicon dioxide (SiO) x ).

[0064] Figure 2C A schematic diagram of yet another exemplary display substrate 200b according to an embodiment of this application is shown.

[0065] like Figure 2C As shown, after depositing the materials for the first electrode 212 and the protective layer 214 of the first electrode 212, in some embodiments, the first electrode 212 can be formed by a single patterning process, wherein the single patterning process may include an etching process.

[0066] Figure 2D A schematic diagram of yet another exemplary display substrate 200b according to an embodiment of this application is shown.

[0067] like Figure 2D As shown, in some embodiments, the substrate 202 after the formation of the first electrode 212 can be filled with silicon oxide, and then the spacing region 220 of the first electrode 212 can be flattened by a dry etching lateral height coverage (LHC) process to form a filling layer 216. The filling layer 216 can be formed in a single patterning process. During the formation of the filling layer 216, the protective layer 214 is etched away, thereby exposing the surface of the first electrode 212.

[0068] Figure 2E A schematic diagram of yet another exemplary display substrate 200b according to an embodiment of this application is shown.

[0069] like Figure 2E As shown, in some embodiments, after forming the fill layer 216, a pixel defining layer 204 can be formed on the substrate 202. The pixel defining layer 204 may include multiple sublayers sequentially stacked along a direction away from the substrate 202, and these multiple sublayers can be formed simultaneously on the substrate 202 in a single patterning process. The materials used to fabricate the multiple sublayers along the direction away from the substrate 202 may sequentially include silicon oxide, silicon nitride, and silicon oxide.

[0070] Figure 2FA schematic diagram of yet another exemplary display substrate 200b according to an embodiment of this application is shown.

[0071] like Figure 2F As shown, in some embodiments, after forming the pixel definition layer 204, a pixel separation structure 218 can be formed between adjacent sub-pixels.

[0072] Figure 2G A schematic diagram of yet another exemplary display substrate 200b according to an embodiment of this application is shown.

[0073] like Figure 2G As shown, at least one of the multiple sub-functional film layers in the light-emitting functional layer 210 (e.g., the charge generation layer 2102) can be disconnected at the pixel separation structure 218, thereby improving the lateral crosstalk problem between adjacent sub-pixels and improving display quality.

[0074] As described above, during the formation of the filler layer 216, the protective layer 214 is etched away, thereby exposing the surface of the first electrode 212. Simultaneously, wet stripping is required during the formation of the filler layer 216, the pixel defining layer 204, and the pixel separation structure 218. Because the surface of the first electrode 212 is exposed, the stripping solution will repeatedly erode the anode surface during multiple stripping processes.

[0075] Figure 2H A schematic diagram showing the change in grain height on the surface of an exemplary first electrode 212 according to an embodiment of this application after being eroded by a chemical solution.

[0076] like Figure 2H As shown, the initial grain height of the surface of the first electrode 212 is 1.11 micrometers. During the formation of the filling layer 216, after the first chemical etch, the grain height of the surface of the first electrode 212 is 1.01 micrometers. During the formation of the pixel defining layer 204, after the second chemical etch, the grain height of the surface of the first electrode 212 is 0.97 micrometers. During the formation of the pixel partition structure 218, after the third chemical etch, the grain height of the surface of the first electrode 212 is 0.77 micrometers. It can be seen that after multiple chemical etches, the grain height of the surface of the first electrode 212 gradually decreases, resulting in a decrease in the surface roughness of the first electrode 212.

[0077] Figure 2I A schematic diagram of the initial lattice morphology of an exemplary first electrode 212 according to an embodiment of this application is shown. Figure 2J A schematic diagram of the morphology of the surface lattice of an exemplary first electrode 212 according to an embodiment of this application after being eroded by a chemical solution is shown.

[0078] Combining 2I and Figure 2JAs can be seen, the initial lattice morphology of the first electrode 212 surface is relatively large. After three etching processes with the chemical solution, the lattice becomes smaller, and the surface lattice of the first electrode 212 becomes blurred. A larger lattice results in better electrical conductivity. Conversely, a smaller lattice leads to increased inter-lattice spacing, which in turn reduces the carrier migration rate and consequently increases the resistance of the first electrode 212. This increased resistance causes the first electrode 212 to heat up during OLED light emission, potentially leading to short circuits and melting of the anode and cathode. This further contributes to display defects such as foreign objects and line spots, ultimately reducing the display quality.

[0079] To at least address the aforementioned problems, this application provides a display substrate and a display device. A pixel defining layer defines multiple sub-pixels, each sub-pixel including a light-emitting element. The light-emitting element includes a first electrode. A continuous filling layer fills the gap between adjacent first electrodes, and a pixel isolation structure is provided in the filling layer. This allows at least one of the multiple sub-functional film layers in the light-emitting functional layer to be disconnected, thereby reducing lateral electrical crosstalk between pixels and improving display quality. Simultaneously, a first portion overlapping the pixel defining layer and the first electrode covers the first electrode. Thus, after the first electrode is fabricated, when the pixel isolation structure is fabricated, the first portion can protect the surface of the first electrode, preventing erosion of the first electrode surface during the fabrication of the pixel isolation structure.

[0080] Figure 3A A schematic diagram of an exemplary display substrate 300 according to an embodiment of this application is shown.

[0081] like Figure 3A As shown, in some embodiments, the display substrate 300 may include a substrate 302 and a pixel defining layer 304 and a plurality of sub-pixels located on the substrate 302. The display substrate 300 may also include a pixel separation structure 306.

[0082] The pixel defining layer 304 may further include a plurality of pixel openings 3042 defining a plurality of sub-pixels. Each of the plurality of sub-pixels may further include a light-emitting element (e.g., light-emitting element 312a and light-emitting element 312b), which may include a light-emitting functional layer 308 and a first electrode 310 located between the light-emitting functional layer 308 and the substrate 302. The first electrode 310 may be an anode. The plurality of pixel openings 3042 are used to expose the first electrode 310, so that the first electrode 310 contacts the light-emitting functional layer 308.

[0083] The light-emitting functional layer 308 may further include multiple sub-functional film layers, which may include a charge-generating layer 3082 and light-emitting layers located on the upper and lower sides of the charge-generating layer 3082 (e.g., a first light-emitting layer 3084 and a second light-emitting layer 3086). The charge-generating layer 3082 may be a monolithic structure, fabricated using an open mask.

[0084] The pixel partition structure 306 can be located between adjacent sub-pixels. The orthographic projection of the pixel partition structure 306 on the substrate 302 can be located within the orthographic projection of the pixel defining layer 304 on the substrate 302. At least one of the multiple sub-functional film layers in the light-emitting functional layer 308 (e.g., charge generation layer 3082) is disconnected at the location of the pixel partition structure 306.

[0085] like Figure 3A As shown, in some embodiments, the pixel defining layer 304 may include a first portion 3044 overlapping with the first electrode 310, and the first portion 3044 may be located on the side of the first electrode 310 away from the substrate 302. Thus, in the display substrate 300 provided in this application embodiment, multiple sub-pixels are defined by the pixel defining layer, and a pixel separation structure is provided between adjacent sub-pixels. This can disconnect at least one of the multiple sub-functional film layers in the light-emitting functional layer, thereby reducing lateral electrical crosstalk between pixels and improving display quality. Simultaneously, by covering the first electrode with the first portion overlapping the pixel defining layer, the first portion can protect the surface of the first electrode when the pixel separation structure is fabricated after the first electrode is fabricated, preventing the surface of the first electrode from being eroded during the fabrication of the pixel separation structure.

[0086] like Figure 3A As shown, the display substrate 300 may further include a second electrode 314, which may be a cathode. The light-emitting functional layer 308 is located between the first electrode 310 and the second electrode 314. By protecting the surface of the first electrode 310 through the first portion 3044, the problem of increased resistance of the first electrode 310 after repeated erosion of the surface of the first electrode 310 can be improved, thereby improving the problem of short circuit caused by the melting of the anode and cathode due to the heat of the first electrode 310 during the light emission process.

[0087] like Figure 3A As shown, in some embodiments, the pixel defining layer 304 may further include a second portion 3048 and a third portion 3046, wherein the orthographic projection of the second portion 3048 on the substrate 302 does not overlap with the orthographic projection of the first electrode 310 on the substrate 302. The third portion 3046 may be located on the side of the first portion 3044 and the second portion 3048 away from the substrate 302, and the orthographic projections of the first portion 3044 and the second portion 3048 on the substrate 302 are located within the orthographic projection of the third portion 3046 on the substrate 302. In this way, the protruding portion 3050 of the third portion 3046 can play a certain role in blocking the flow of the light-emitting functional layer 308 into the pixel isolation structure 306, so that at least one sub-functional film layer in the light-emitting functional layer 308 is broken at the pixel isolation structure 306.

[0088] like Figure 3A As shown, in some embodiments, the pixel separation structure 306 may include a groove 3052 formed in the second portion 3048, and a third portion 3046 includes an opening 3054 in the groove 3052, the orthographic projection of the opening 3054 on the substrate 302 being located within the orthographic projection of the groove 3052 on the substrate 302. In this way, a portion of the material of at least one sub-functional film layer in the light-emitting functional layer 308 can flow into the groove 3052 through the opening 3054.

[0089] like Figure 3A As shown, in some embodiments, the distance 'a' between the orthographic projection edge of the opening 3054 on the substrate 302 and the orthographic projection edge of the groove 3052 on the substrate can be greater than or equal to 0.1 micrometers. Too short a distance is detrimental to the breaking of the light-emitting functional layer 308 at the pixel separation structure 306.

[0090] like Figure 3A As shown, in some embodiments, multiple pixel openings 3042 and pixel partition structures 306 can be formed simultaneously in a single patterning process. This avoids the problem of exposing the surface of the first electrode 310 and causing it to be eroded by opening multiple pixel openings 3042 first.

[0091] like Figure 3A As shown, in some embodiments, the display substrate 300 may further include a filler layer 316 located between the pixel defining layer 304 and the substrate 302 to fill the gap region of the first electrode 310.

[0092] Figure 3B A schematic diagram of yet another exemplary display substrate 300 according to an embodiment of this application is shown.

[0093] like Figure 3B As shown, in some embodiments, during the fabrication of the display substrate 300, the materials for fabricating the first electrode 310 and the materials for fabricating the first portion 3044 can be deposited on one side of the substrate 302. The materials for fabricating the first electrode 310 may include a TAT stack structure and indium tin oxide (ITO), and the thicknesses of the TAT stack structure and ITO along the direction away from the substrate 302 can be approximately [value missing]. Optionally, the thickness of indium tin oxide can be In some embodiments, the material used to fabricate the first portion 3044 may include silicon nitride. As an optional embodiment, the first portion 3044 may also employ a stacked structure of silicon nitride and silicon oxide sequentially arranged along a direction away from the substrate 302. Since the first portion 3044 will be located between the pixel defining layer 304 and the substrate 302 after the display substrate 300 is fabricated, excessively high or low thickness of the first portion 3044 can create a discontinuity, causing distortion of the vapor-deposited material during the vapor deposition process. Therefore, in some embodiments, the thickness of the first portion 3044 can be [missing information - likely a value or specification]. For example, the thickness of the film layer made of silicon nitride can be The thickness of the film made of silicon oxide can be

[0094] Figure 3C A schematic diagram of yet another exemplary display substrate 300 according to an embodiment of this application is shown.

[0095] like Figure 3C As shown, after depositing the materials for the first electrode 310 and the first portion 3044, in some embodiments, the first electrode 310 can be formed by a single patterning process, wherein the single patterning process may include an etching process.

[0096] Figure 3D A schematic diagram of yet another exemplary display substrate 300 according to an embodiment of this application is shown.

[0097] like Figure 3D As shown, in some embodiments, the substrate 302 after the formation of the first electrode 310 can be filled with silicon oxide over its entire surface, and then the spacer region 320 of the first electrode 310 can be flattened using an LHC process to form a filling layer 316. Given the flattening effect of the filling layer 316 on the spacer region 320, in some embodiments, the thickness of the filling layer 316 can be... To match the thickness of the first electrode 310.

[0098] The fill layer 316 can be formed in a single patterning process. In some embodiments, during the formation of the fill layer 316, an End Point Detector (EPD) can be used to stop etching when the silicon nitride material used to fabricate the first portion 3044 is detected. In this way, while forming the fill layer 316, the first portion 3044, which is used to protect the surface of the first electrode 310, can be retained.

[0099] Figure 3E A schematic diagram of yet another exemplary display substrate 300 according to an embodiment of this application is shown.

[0100] like Figure 3EAs shown, in some embodiments, after forming the fill layer 316, the material for fabricating the pixel defining layer 304 can be deposited on the substrate 302. The pixel defining layer 304 may include multiple sub-layers sequentially stacked along a direction away from the substrate 302. In this embodiment, since the first portion 3044 is retained, it can be used as part of the pixel defining layer 304. Therefore, when fabricating the pixel defining layer 304, silicon nitride and silicon oxide, the materials for fabricating the pixel defining layer 304, can be deposited simultaneously on the substrate 302, wherein the silicon nitride film is located between the silicon oxide film and the first portion 3044. The thickness of the silicon nitride film can be... The thickness of the silicon oxide film can be By incorporating the first part 3044 as part of the pixel limiting layer 304, a three-layer pixel limiting layer 304 structure can still be formed while protecting the surface of the first electrode 310.

[0101] Figure 3F A schematic diagram of yet another exemplary display substrate 300 according to an embodiment of this application is shown.

[0102] like Figure 3F As shown, in some embodiments, after depositing the material for the pixel defining layer 304, a pixel partition structure 306 can be fabricated using a single patterning process. After fabricating the pixel partition structure 306, the surface of the first electrode 310 is opened using another patterning process to form multiple pixel openings 3042, while simultaneously forming... Figure 3A The display substrate 300 is shown. By fabricating the pixel isolation structure 306 first and then opening the multiple pixel openings 3042, the surface of the first electrode 310 can be protected. This avoids exposing the surface of the first electrode 310 by first fabricating the multiple pixel openings 3042, preventing the surface of the first electrode 310 from being etched by the etching solution used to fabricate the pixel isolation structure 306. Furthermore, since the entire third portion 3048 of the pixel defining layer 304 is made of the same material (e.g., silicon oxide), there is no problem of different etching rates when fabricating the pixel isolation structure 306, resulting in a smooth opening of the pixel isolation structure 306 formed on the third portion 3048.

[0103] In addition, the surface of the first electrode can be prevented from being eroded by forming multiple pixel openings and pixel partition structures at the same time.

[0104] Figure 4A A schematic diagram of an exemplary display substrate 400 according to an embodiment of this application is shown.

[0105] like Figure 4AAs shown, in some embodiments, the display substrate 400 may include a substrate 402 and a pixel defining layer 404 and a plurality of sub-pixels located on the substrate 402.

[0106] The pixel defining layer 404 may further include a plurality of pixel openings 4042 defining a plurality of sub-pixels. Each of the plurality of sub-pixels may further include a light-emitting element, which may include a light-emitting functional layer 408 and a first electrode 410 located between the light-emitting functional layer 408 and the substrate 402, wherein adjacent first electrodes 410 are separated by a spacing region 420, wherein the first electrode 410 may be an anode.

[0107] The light-emitting functional layer 408 may include multiple sub-functional film layers, which may include a charge-generating layer 4082 and light-emitting layers located above and below the charge-generating layer 4082 (e.g., a first light-emitting layer 4084 and a second light-emitting layer 4086). The charge-generating layer 4082 may be a single structure and fabricated using an open mask.

[0108] like Figure 4A As shown, in some embodiments, the pixel defining layer 404 may include a first portion 4044 overlapping with the first electrode 410, and the first portion 4044 may be located on the side of the first electrode 410 away from the substrate 402. Thus, in the display substrate 400 provided in this application embodiment, multiple sub-pixels are defined by the pixel defining layer, and a pixel separation structure is provided between adjacent sub-pixels. This can disconnect at least one of the multiple sub-functional film layers in the light-emitting functional layer, thereby reducing lateral electrical crosstalk between pixels and improving display quality. Simultaneously, by covering the first electrode with the first portion overlapping the pixel defining layer, the first portion can protect the surface of the first electrode when the pixel separation structure is fabricated after the first electrode is fabricated, preventing the surface of the first electrode from being eroded during the fabrication of the pixel separation structure.

[0109] like Figure 4A As shown, the display substrate 400 may further include a second electrode 414, which may be a cathode, and the light-emitting functional layer 408 may be located between the first electrode 410 and the second electrode 414. By protecting the surface of the first electrode 410 through the first portion 4044, the problem of increased resistance of the first electrode 410 after repeated erosion of the surface of the first electrode 410 can be improved, thereby improving the problem of short circuit caused by the melting of the anode and cathode due to the heat of the first electrode 410 during the light emission process.

[0110] like Figure 4AAs shown, in some embodiments, the display substrate 400 may further include a filling layer 416 located on the substrate 402. The filling layer 416 may further include a third portion 4164 and a fourth portion 4166. The third portion 4164 may fill the spacer region 420. The fourth portion 4166 may be located on the side of the third portion 4164 away from the substrate 402. The orthographic projection of the fourth portion 4166 on the substrate 402 overlaps with the orthographic projection of the first portion 4044 on the substrate 402.

[0111] like Figure 4A As shown, in some embodiments, the pixel defining layer 404 may further include a second portion 4046. The second portion 4046 may be located on the side of the first portion 4044 and the fourth portion 4166 away from the substrate 402, and the orthographic projections of the first portion 4044 and the fourth portion 4166 on the substrate 402 may lie within the orthographic projection of the second portion 4046 on the substrate 402. In this way, the protruding portion 4050 of the second portion 4046 can play a certain role in blocking the flow of the light-emitting functional layer 408 into the pixel isolation structure 406, so that at least one sub-functional film layer in the light-emitting functional layer 408 is broken at the pixel isolation structure 406.

[0112] The pixel isolation structure 406 may be located between the second part 4046 and the third part 4164. The orthographic projection of the pixel isolation structure 406 on the substrate 402 may be located within the orthographic projection of the filling layer 416 on the substrate 402. At least one of the multiple sub-functional film layers in the light-emitting functional layer 408 (e.g., the charge generation layer 4082) is disconnected at the location of the pixel isolation structure 406.

[0113] like Figure 4A As shown, in some embodiments, the first portion 4044 may include a first material, and the fourth portion 4166 may include a second material, with an etching rate ratio between the second material and the first material that can be from 5:1 to 10:1. In some embodiments, the first material may be silicon oxide, and the second material may be silicon nitride. This utilizes the etching rate ratio of the first and second materials within a certain range to ensure the simultaneous fabrication of multiple pixel openings 4042 and pixel partition structures 406. Figure 4A As shown, in some embodiments, the pixel separation structure 406 may include a third portion 4164 and a fourth portion 4166 forming a groove 4052, and a second portion 4046 includes an opening 4054 in the groove 4052. The orthographic projection of the opening 4054 onto the substrate 402 may lie within the orthographic projection of the groove 4052 onto the substrate 402. In this way, a portion of the material of at least one sub-functional film layer in the light-emitting functional layer 408 can flow into the groove 4052 through the opening 4054.

[0114] like Figure 4A As shown, in some embodiments, the first distance b between the orthographic projection edge of the opening 4054 on the substrate 402 and the orthographic projection edge of the groove 4052 on the substrate can be greater than or equal to 0.1 micrometers. Too short a distance is detrimental to the breaking of the light-emitting functional layer 408 at the pixel separation structure 406.

[0115] like Figure 4A As shown, in some embodiments, multiple pixel openings 4042 and pixel partition structures 406 can be formed simultaneously in a single patterning process. This avoids the problem that opening multiple pixel openings 4042 first would expose the surface of the first electrode 410, thus causing the surface of the first electrode 410 to be eroded.

[0116] Figure 4B A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0117] like Figure 4B As shown, in some embodiments, during the fabrication of the display substrate 400, the materials for fabricating the first electrode 410 and the materials for fabricating the first portion 4044 can be deposited on one side of the substrate 402. The materials for fabricating the first electrode 410 may include a TAT stack structure and indium tin oxide (ITO), and the thickness of the TAT stack structure and ITO may be approximately [missing information - likely related to thickness]. Optionally, the thickness of indium tin oxide can be In some embodiments, the material used to fabricate the first portion 4044 may include silicon oxide. Since the first portion 4044 is located between the pixel defining layer 404 and the substrate 402 after the display substrate 400 is fabricated, excessively high or low thickness of the first portion 4044 can create a discontinuity, causing distortion of the vapor-deposited material during the vapor deposition process. Therefore, in some embodiments, the thickness of the first portion 4044 can be [missing information - likely a value or specification]. For example, the thickness of the first portion 4044 can be

[0118] Figure 4C A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0119] like Figure 4C As shown, after depositing the materials for the first electrode 410 and the first portion 4044, in some embodiments, the first electrode 410 can be formed by a single patterning process, wherein the single patterning process may include an etching process.

[0120] Figure 4D A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0121] like Figure 4D As shown, in some embodiments, the substrate 402 after the formation of the first electrode 410 can be filled with silicon nitride across its entire surface, and then the spacer regions 420 between adjacent first electrodes 410 can be flattened using an LHC process to form a full-layer filler layer 4162. Given the flattening effect of the full-layer filler layer 4162 on the spacer regions 420, in some embodiments, the thickness of the full-layer filler layer 4162 can be [missing information]. To match the sum of the thicknesses of the first electrode 410 and the first portion 4044. For example, the thickness of the entire fill layer 4162 can be...

[0122] Figure 4E A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0123] like Figure 4E As shown, in some embodiments, after forming the entire fill layer 4162, the portion of the entire fill layer 4162 located on the side of the first portion 4044 away from the substrate 402 needs to be etched away, while retaining the other portion of the entire fill layer 4162 located in the spacer region 420, in order to fabricate the second portion 4046 of the pixel defining layer 404 in subsequent process flows. In some embodiments, during the etching process, an endpoint detection device can be used to stop etching when silicon oxide, the material used to fabricate the first portion 4044, is detected. In this way, while etching away the portion of the entire fill layer 4162 located on the first portion 4044 away from the substrate 402, the first portion 4044 used to protect the surface of the first electrode 410 can be retained.

[0124] Figure 4F A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0125] like Figure 4F As shown, in some embodiments, after etching away the portion of the fill layer 4162 located away from the substrate 402 in the first portion 4044, the material for fabricating the second portion 4046 of the pixel defining layer 404 can be deposited on the substrate 402. The material for fabricating the second portion 4046 may include silicon oxide, and the thickness of the second portion 4046 may be approximately [missing information - likely related to thickness]. This thickness ensures that the second part 4046 will not collapse during subsequent vapor deposition, thus preventing it from losing its insulating function.

[0126] Back Figure 4AAfter the second portion 4046 is deposited, in some embodiments, multiple pixel openings 4042 and pixel partition structures 406 can be formed simultaneously in a single patterning process. Since the entire second portion 4046 is made of the same material (e.g., silicon oxide), there will be no difference in etching rates when fabricating the pixel partition structures 406, resulting in smooth openings in the pixel partition structures 406 formed on the second portion 4046. Simultaneously, when etching multiple pixel openings 4042 and pixel partition structures 406 simultaneously, an endpoint detection device can be used to control the stopping of etching when the material used to fabricate the first electrode 410 is detected. As an optional embodiment, etching can also be stopped by setting an etching time. Since the first portion 4044 is made of the same material as the second portion 4046 (e.g., silicon oxide) and the film thickness of the first portion 4044 is... The thickness of the 4046 film in Part Two is... The entire filler layer 4162 is made of silicon nitride and the film thickness of the entire filler layer 4162 is [missing information]. With the etching rates of silicon oxide and silicon nitride at a ratio of 1:9, and in conjunction with the aforementioned film thickness, it is possible to simultaneously etch multiple pixel openings 4042 and pixel isolation structures 406, ensuring that multiple pixel openings 4042 and pixel isolation structures 406 are formed simultaneously when etching stops.

[0127] It is understood that the thickness of each film layer and the material used to fabricate the film layers in the embodiments of this application are merely exemplary. Other film layer thicknesses that can simultaneously form multiple pixel openings and pixel isolation structures, combined with etching rate ratios of materials in the range of 5:1 to 10:1, should all be included in the protection scope of this application.

[0128] It should be noted that, as Figure 4AAs shown, a pixel isolation structure 406, a third portion 4164, and a fourth portion 4166 of the filling layer 416 are formed by forming a groove 4052 on the entire filling layer 4162. In some embodiments, the thickness h1 of the third portion 4164 located between the groove 4052 and the substrate 402 can be greater than the thickness of the first electrode 410, and / or the thickness h1 of the third portion 4164 can be greater than or equal to the thickness h2 of the fourth portion 4166. In this way, the reserved portion of the third portion 4164 can ensure that even if the groove 4052 is over-etched, the gap between adjacent first electrodes 410 can be filled. In some embodiments, the thickness of the first portion 4044 can be greater than or equal to the thickness of the second portion 4046 to ensure that the first portion 4044 has sufficient thickness to prevent over-etching. The sum of the thicknesses of the third portion 4164 and the fourth portion 4166 is equal to the thickness of the entire filler layer 4162. In some embodiments, the sum of the thicknesses of the third portion 4164 and the fourth portion 4166 (h1+h2) can be... The first part 4044 and the second part 4046 can form a pixel-limiting layer, eliminating the need to form a separate pixel-limiting layer.

[0129] Since part 4166 overlaps part 4044, such as Figure 4A As shown, in some embodiments, the second distance L between the orthographic projection edge of the fourth portion 4166 on the substrate 402 away from the groove 4052 and the orthographic projection edge of the first portion 4044 on the substrate away from the groove 4052 can be greater than or equal to the first distance b.

[0130] The etching depth of the groove 4052 is affected by the etching time, which in turn is affected by the size of the first spacing b. When the first spacing b is greater than or equal to 0.15 micrometers, the etching time is longer, resulting in a deeper groove 4052. This leads to an insufficient thickness h1 of the third portion 4164 of the fill layer 416, thus failing to fill the gap between adjacent first electrodes 410. Therefore, a sublayer can be provided in the fill layer 416 to prevent excessive etching of the fill layer 416.

[0131] Figure 5A A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0132] like Figure 5AAs shown, in some embodiments, the film structure of the filling layer 416 can be changed to a filling layer 516, which may include a third portion 4164 and a fourth portion 4166. The third portion 4164 sequentially comprises a first sublayer 502 and a second sublayer 504 along a direction away from the substrate 402, with the thickness of the second sublayer 504 being less than the thickness of the first sublayer 502. With the obstruction of the second sublayer 504, the etching solution can flow laterally within the second sublayer 504, thereby increasing the size of the spacing b while ensuring that the thickness of the first sublayer 502 matches the thickness of the first electrode 410.

[0133] like Figure 5A As shown, in some embodiments, the thickness of the first sublayer 502 can be greater than or equal to the thickness of the first electrode 410 to ensure that the first sublayer 502 fills the gap 420 of the first electrode 410. In some embodiments, the first sublayer 502 may include a second material, and the second sublayer may include the first material. For example, the first material may be silicon oxide, and the second material may be silicon nitride. Silicon oxide, with its slower etching rate, can act as the second sublayer to provide some resistance to the etching solution.

[0134] It is understood that the first material being silicon oxide and the second material being silicon nitride in the embodiments of this application are merely exemplary, and other etching materials with similar etching rates to silicon oxide and silicon nitride should be included in the protection scope of this application.

[0135] Figure 5B A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0136] like Figure 5B As shown, in some embodiments, when fabricating the fill layer 516, the substrate 402 after the formation of the first electrode 410 can be completely filled with a first sublayer 502, a second sublayer 504, and a third sublayer 506. The materials used to fabricate the first sublayer 502, the second sublayer 504, and the third sublayer 506 can be silicon nitride, silicon oxide, and silicon nitride, respectively. Then, the spacer region 420 of the first electrode 410 is flattened using an LHC process, thereby forming a complete fill layer 5162. Given the flattening effect of the complete fill layer 5162 on the spacer region 420, in some embodiments, the thickness of the complete fill layer 5162 can be [missing information]. To match the sum of the thicknesses of the first electrode 410 and the first portion 4044. For example, the thickness of the entire fill layer 5162 can be... The thicknesses of the first sublayer 502, the second sublayer 504, and the third sublayer 506 in the fill layer 5162 can be, in sequence, as follows: and

[0137] Figure 5CA schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0138] like Figure 5C As shown, in some embodiments, after forming the entire fill layer 5162, the portion of the entire fill layer 5162 located on the side of the first portion 4044 away from the substrate 402 needs to be etched away, while retaining the other portion of the entire fill layer 5162 located in the spacer region 420, so as to fabricate the second portion 4046 of the pixel defining layer 404 in subsequent process flows. In some embodiments, an endpoint detection device can be used to set the etching to stop when the silicon oxide material of the first portion 4044 is detected. In this way, while etching away the portion of the entire fill layer 4162 located on the first portion 4044 away from the substrate 402, the first portion 4044 used to protect the surface of the first electrode 410 can be retained.

[0139] Figure 5D A schematic diagram of yet another exemplary display substrate 400 according to an embodiment of this application is shown.

[0140] like Figure 5D As shown, in some embodiments, after the portion of the fill layer 5162 located in the first portion 4044 away from the substrate 402 is etched away, the material for the second portion 4046 of the pixel defining layer 404 can be deposited on the substrate 402.

[0141] Back Figure 5A After the second portion 4046 is deposited, in some embodiments, multiple pixel openings 4042 and pixel partition structures 406 can be formed simultaneously in a single patterning process. Since the entire second portion 4046 is made of the same material, there will be no difference in the etching rate of the etching solution when fabricating the pixel partition structure 406, resulting in a smooth opening in the pixel partition structure 406 formed on the second portion 4046.

[0142] When simultaneously etching multiple pixel openings 4042 and pixel partition structures 406, in some embodiments, an endpoint detection device can be used to stop etching when both the fabrication material of the first electrode 410 and the fabrication material of the second sublayer 504 are detected. As an optional embodiment, etching can also be stopped by setting an etching time. The thickness of the third sublayer 506 is used as... The thickness of the first part, 4044, is Taking the example of the third sublayer 506 being made of silicon nitride and the first part 4044 being made of silicon oxide, since the thickness of the third sublayer 506 is less than the thickness of the first part 4044, and the etching rate ratio of silicon nitride to silicon oxide is 9:1, the etching rate of the third sublayer 506 is greater than that of the first part 4044. The endpoint detection device will detect the material of the third sublayer 506 first. Etching stops when the endpoint detection device detects the material of the first part 4044. Thus, the etching rate of the third sublayer 506 is fast, and because the film thickness is less than that of the first part 4044, the etching time is longer, resulting in a larger spacing b. Therefore, the film structure of the filling layer 5162 can be used to fabricate display substrates with a spacing b greater than or equal to 0.15 micrometers.

[0143] It is understood that the thickness of each membrane layer and the materials used to manufacture the membrane layers in the embodiments of this application are merely exemplary, and other membrane layer thicknesses and materials that can achieve the same technical effect should be included in the protection scope of this application.

[0144] Things that need to be explained, combined with Figure 5A and Figure 5D After the third sublayer 506 is etched, the fourth part 4166 of the filling layer 516 is formed.

[0145] This application also provides a display device. Figure 6 A schematic diagram of an exemplary display device according to an embodiment of this application is shown.

[0146] like Figure 6 As shown, this embodiment provides a display device 601, including a display substrate 6011. The display substrate 6011 is any embodiment of the aforementioned display substrate or an arrangement or combination of embodiments. The display device is a product with image display function, such as: a monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, home appliance, information query equipment (such as e-government, banking, hospital, power and other departments' business query equipment, monitors, etc.).

[0147] This application also provides a method for preparing a display substrate. Figure 7 A schematic flowchart of an exemplary display substrate fabrication method 700 according to an embodiment of this application is shown. The display substrate may include a substrate, such as... Figure 7 As shown, the preparation method 700 may include the following steps.

[0148] In step 702, a pixel defining layer is formed on the substrate, the pixel defining layer including a plurality of pixel openings defining a plurality of sub-pixels.

[0149] In step 704, a plurality of sub-pixels are formed on the substrate, each sub-pixel including a light-emitting element, the light-emitting element including a light-emitting functional layer and a first electrode located between the light-emitting functional layer and the substrate, adjacent first electrodes including a spacer region, and the light-emitting functional layer including a plurality of sub-functional film layers.

[0150] The pixel defining layer includes a first portion that overlaps with the first electrode.

[0151] In step 706, the first portion is formed on the side of the first electrode away from the substrate.

[0152] In step 708, a filling layer is formed on the substrate, the filling layer comprising a third portion and a fourth portion, the third portion being filled in the spacer region, and the fourth portion being formed on the side of the third portion away from the substrate, wherein the orthographic projection of the fourth portion on the substrate overlaps with the orthographic projection of the first portion on the substrate.

[0153] The pixel-defining layer further includes a second part.

[0154] In step 710, a second portion is formed on the side of the first portion and the fourth portion away from the substrate, wherein the orthographic projections of the first portion and the fourth portion on the substrate lie within the orthographic projection of the second portion on the substrate.

[0155] In step 712, a pixel partition structure is formed between the second part and the third part, wherein the orthographic projection of the pixel partition structure on the substrate is located within the orthographic projection of the filling layer on the substrate, and at least one of the plurality of sub-functional film layers in the light-emitting functional layer is disconnected at the location of the pixel partition structure.

[0156] In some embodiments, the first portion includes a first material, the fourth portion includes a second material, and the etching rate ratio of the second material to the first material is 5:1 to 10:1.

[0157] In some embodiments, the thickness of the third portion is greater than the thickness of the first electrode; and / or the thickness of the third portion is greater than or equal to the thickness of the fourth portion; and / or the thickness of the first portion is greater than or equal to the thickness of the second portion; and / or the thickness of the fourth portion is greater than or equal to the thickness of the first portion.

[0158] In some embodiments, the pixel separation structure includes the third portion and the fourth portion forming a groove, the second portion including an opening of the groove, the orthographic projection of the opening on the substrate being located within the orthographic projection of the groove on the substrate.

[0159] In some embodiments, the first distance between the orthographic projection edge of the opening on the substrate and the orthographic projection edge of the groove on the substrate is greater than or equal to 0.1 micrometers.

[0160] In some embodiments, the second distance between the orthographic projection edge of the fourth portion on the substrate away from the groove and the orthographic projection edge of the first portion on the substrate away from the groove is greater than or equal to the first distance.

[0161] In some embodiments, multiple pixel openings and pixel partition structures are formed simultaneously in a single patterning process.

[0162] In some embodiments, the third portion is provided with a first sublayer and a second sublayer in sequence along a direction away from the substrate, the thickness of the second sublayer being less than the thickness of the first sublayer; and / or the thickness of the first sublayer being greater than or equal to the thickness of the first electrode; and / or the first sublayer comprising the second material, and the second sublayer comprising the first material.

[0163] In some embodiments, the thickness of the first portion is And / or the second portion includes the first material, the thickness of the second portion being... And / or the thickness of the filling layer is

[0164] In some embodiments, the first material is SiO x The second material is SiN x .

[0165] In some embodiments, the plurality of sub-functional layers include a charge generation layer and a first light-emitting layer and a second light-emitting layer located on both sides of the charge generation layer, wherein the charge generation layer is disconnected at the location of the pixel isolation structure.

[0166] The methods described above are used to prepare the corresponding display substrates in any of the foregoing embodiments, and have the beneficial effects of the corresponding display substrate embodiments, which will not be repeated here.

[0167] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0168] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0169] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0170] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display substrate, comprising: Substrate; A pixel defining layer, located on the substrate, includes multiple pixel openings defining multiple sub-pixels; Multiple sub-pixels are located on the substrate. Each sub-pixel includes a light-emitting element. The light-emitting element includes a light-emitting functional layer and a first electrode located between the light-emitting functional layer and the substrate. Adjacent first electrodes are separated by a spacer region. The light-emitting functional layer includes multiple sub-functional film layers. The pixel defining layer includes a first portion overlapping the first electrode, the first portion being located on the side of the first electrode away from the substrate. A filling layer, located on the substrate, includes a third portion and a fourth portion. The third portion fills the spacer region, and the fourth portion is located on the side of the third portion away from the substrate. The orthographic projection of the fourth portion on the substrate overlaps with the orthographic projection of the first portion on the substrate. The pixel defining layer further includes a second portion, which is located on the side of the first portion and the fourth portion away from the substrate, and the orthographic projections of the first portion and the fourth portion on the substrate are located within the orthographic projections of the second portion on the substrate. A pixel partition structure is located between the second part and the third part, wherein the orthographic projection of the pixel partition structure on the substrate is located within the orthographic projection of the filling layer on the substrate, and at least one of the plurality of sub-functional film layers in the light-emitting functional layer is disconnected at the location of the pixel partition structure.

2. The display substrate as claimed in claim 1, wherein, The first part includes a first material, and the fourth part includes a second material, wherein the etching rate ratio of the second material to the first material is 5:1 to 10:

1.

3. The display substrate as described in claim 1, wherein, The thickness of the third portion is greater than the thickness of the first electrode; and / or The thickness of the third part is greater than or equal to the thickness of the fourth part; and / or The thickness of the first part is greater than or equal to the thickness of the second part.

4. The display substrate as claimed in claim 1, wherein, The pixel isolation structure includes a groove formed by the third part and the fourth part, the second part including an opening of the groove, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the groove on the substrate.

5. The display substrate as claimed in claim 4, wherein, The first distance between the orthographic projection edge of the opening on the substrate and the orthographic projection edge of the groove on the substrate is greater than or equal to 0.1 micrometers.

6. The display substrate as claimed in claim 5, wherein, The second distance between the orthographic projection edge of the fourth portion on the substrate away from the groove and the orthographic projection edge of the first portion on the substrate away from the groove is greater than or equal to the first distance.

7. The display substrate as claimed in claim 1, wherein, The multiple pixel openings and the pixel partition structure are formed simultaneously through a single patterning process.

8. The display substrate as claimed in claim 2, wherein, The third part is provided with a first sub-layer and a second sub-layer in sequence along a direction away from the substrate, and the thickness of the second sub-layer is less than the thickness of the first sub-layer. and / or The thickness of the first sublayer is greater than or equal to the thickness of the first electrode; and / or The first sublayer includes the second material, and the second sublayer includes the first material.

9. The display substrate as claimed in claim 2, wherein, The thickness of the first part is and / or The second part includes the first material, and the thickness of the second part is... and / or The thickness of the filler layer is 10. The display substrate as claimed in claim 2, wherein, The first material is SiO x The second material is SiN x .

11. The display substrate as claimed in claim 1, wherein, The plurality of sub-functional layers include a charge generation layer and a first light-emitting layer and a second light-emitting layer located on both sides of the charge generation layer, wherein the charge generation layer is disconnected at the location of the pixel isolation structure.

12. A display device comprising a display substrate as described in any one of claims 1-11.

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