Display device

Abstract

The embodiment of the utility model provides a display device. The display device comprises a clamping voltage stabilizing circuit, a display interface and a time sequence controller, the clamping voltage stabilizing circuit comprises a voltage stabilizing module and a current limiting module; the first end of the current limiting module is connected with the display interface, and the second end of the current limiting module is connected with the voltage stabilizing module and the time schedule controller. The current limiting module comprises a current limiting resistor, and the voltage stabilizing module comprises at least one voltage stabilizing diode; the first end of the current-limiting resistor is connected with the display interface, and the second end of the current-limiting resistor is connected with the first end of the voltage-stabilizing diode and the time schedule controller. The second end of the voltage stabilizing diode is grounded. The voltage stabilizing module and the current limiting module are connected between the display interface and the time schedule controller, under the condition that large voltage invasion exists in the time schedule controller, the current limiting module is used for limiting large current, the voltage stabilizing module is used for clamping the voltage of the time schedule controller, the damage risk of the time schedule controller is weakened, and the time schedule controller is protected. And the display abnormity problem of a display product is improved.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to a display device. Background Technology

[0002] As the functions of notebook display products (notebook display products refer to the LCD displays and display panels used in portable electronic products such as laptops and tablets) gradually increase, such as OD (OverDrive, used to speed up LCD response time) and PSR (Panel Self-Refresh, used for power consumption management), etc., Figure 1 As shown, the implementation of these functions requires the GPU (Graphics Processing Unit) to train with the LCD (Liquid Crystal Display) display panel. Due to the limited number of pins on the interface connector, there is a problem that there is no ground pin to isolate the high voltage transmission pins (such as the backlight power-on voltage transmission pin VLED_IN) from the aforementioned functional pins. This may cause the backlight power-on voltage to be introduced into the adjacent functional pins, damaging the timing controller board (TCON), and thus causing display abnormalities in the display product. Utility Model Content

[0003] The purpose of this utility model embodiment is to provide a display device to improve the display abnormality problem of display products. The specific technical solution is as follows:

[0004] In a first aspect, the present invention provides a display device, the display device including a clamping voltage regulator circuit, a display interface, and a timing controller;

[0005] The clamping voltage regulator circuit includes a voltage regulator module and a current limiting module;

[0006] The first end of the current limiting module is connected to the display interface, and the second end of the current limiting module is connected to the voltage regulator module and the timing controller respectively.

[0007] The current limiting module includes a current limiting resistor, and the voltage regulating module includes at least one Zener diode;

[0008] The first end of the current-limiting resistor is connected to the display interface, and the second end of the current-limiting resistor is connected to the first end of the Zener diode and the timing controller, respectively.

[0009] The second terminal of the Zener diode is grounded.

[0010] In one possible implementation, the first end of the current-limiting resistor is connected to the power consumption control pin of the display interface, and the second end of the current-limiting resistor is connected to the first general-purpose input / output pin of the timing controller and the first end of the Zener diode, respectively.

[0011] In one possible implementation, the first end of the current-limiting resistor is connected to the display delay control pin of the display interface, and the second end of the current-limiting resistor is connected to the second general-purpose input / output pin of the timing controller and the first end of the Zener diode, respectively.

[0012] In one possible implementation, the first end of the current-limiting resistor is connected to the serial data transmission pin of the display interface, and the second end of the current-limiting resistor is connected to the serial data transmission pin of the timing controller and the first end of the Zener diode, respectively.

[0013] In one possible implementation, the current-limiting resistor has a resistance value ranging from 1kΩ to 2kΩ.

[0014] In one possible implementation, the resistance value of the current-limiting resistor is in the range of 100Ω to 200Ω.

[0015] In one possible implementation, the display device further includes a graphics processor and a first pull-up resistor; the voltage regulator module includes a first Zener diode and a second Zener diode.

[0016] The power control pin of the graphics processor is connected to the power control pin of the display interface.

[0017] The first end of the current-limiting resistor is connected to the power consumption control pin of the display interface, and the second end of the current-limiting resistor is connected to the first general-purpose input / output pin of the timing controller, the first end of the first Zener diode, the first end of the second Zener diode, and the second end of the first pull-up resistor, respectively.

[0018] The first end of the first pull-up resistor is connected to the first power supply voltage terminal;

[0019] The second terminal of the first Zener diode is grounded, and the second terminal of the second Zener diode is also grounded.

[0020] In one possible implementation, the display device further includes a graphics processor and a second pull-up resistor; the voltage regulator module includes a first Zener diode and a second Zener diode.

[0021] The display delay control pin of the graphics processor is connected to the display delay control pin of the display interface;

[0022] The first end of the current-limiting resistor is connected to the display delay control pin of the display interface, and the second end of the current-limiting resistor is connected to the second general-purpose input / output pin of the timing controller, the first end of the first Zener diode, the first end of the second Zener diode, and the second end of the second pull-up resistor, respectively.

[0023] The first end of the second pull-up resistor is connected to the first power supply voltage terminal;

[0024] The second terminal of the first Zener diode is grounded, and the second terminal of the second Zener diode is also grounded.

[0025] In one possible implementation, the display device further includes a graphics processor, a third pull-up resistor, and a fourth pull-up resistor;

[0026] The voltage regulator module includes a first voltage regulator diode and a second voltage regulator diode;

[0027] The serial data transmission pin of the graphics processor is connected to the serial data transmission pin of the display interface and the second end of the third pull-up resistor, respectively, and the first end of the third pull-up resistor is connected to the second power supply voltage terminal.

[0028] The first end of the current-limiting resistor is connected to the serial data transmission pin of the display interface, and the second end of the current-limiting resistor is connected to the serial data transmission pin of the timing controller, the first end of the first Zener diode, the first end of the second Zener diode, and the second end of the fourth pull-up resistor.

[0029] The first end of the fourth pull-up resistor is connected to the first power supply voltage terminal;

[0030] The second terminal of the first Zener diode is grounded, and the second terminal of the second Zener diode is also grounded.

[0031] In one possible implementation, the display device further includes a display panel, a driver, and a power board;

[0032] The display panel is connected to the timing controller;

[0033] The backlight power-on voltage output pin of the power board is connected to the backlight power-on voltage transmission pin of the display interface, the backlight power-on voltage transmission pin of the display interface is connected to the backlight power-on voltage input pin of the driver, and the backlight power-on voltage output pin of the driver is connected to the display panel.

[0034] This utility model provides a display device including a clamping voltage regulator circuit, a display interface, and a timing controller. The clamping voltage regulator circuit includes a voltage regulator module and a current limiting module. A first terminal of the current limiting module is connected to the display interface, and a second terminal is connected to both the voltage regulator module and the timing controller. The current limiting module includes a current-limiting resistor, and the voltage regulator module includes at least one Zener diode. A first terminal of the current-limiting resistor is connected to the display interface, and a second terminal is connected to both the first terminal of the Zener diode and the timing controller. The second terminal of the Zener diode is grounded. By connecting the voltage regulator module and the current limiting module between the display interface and the timing controller, in the event of a large voltage intrusion into the timing controller, the current limiting module limits the large current, and the voltage regulator module clamps the voltage of the timing controller, reducing the risk of damage to the timing controller and improving display abnormality issues in the display product. Of course, any product implementing this utility model does not necessarily need to simultaneously achieve all the advantages described above. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.

[0036] Figure 1 This is a schematic diagram of a display product in related technologies;

[0037] Figure 2 This is a schematic diagram of a first structure of a display device provided in an embodiment of the present utility model;

[0038] Figure 3 This is a second structural schematic diagram of the display device provided in an embodiment of the present utility model;

[0039] Figure 4 This is a third structural schematic diagram of the display device provided in an embodiment of the present utility model;

[0040] Figure 5 This is a fourth structural schematic diagram of the display device provided in an embodiment of the present utility model;

[0041] Figure 6 This is a fifth structural schematic diagram of the display device provided in an embodiment of the present utility model;

[0042] Figure 7 This is a sixth structural schematic diagram of the display device provided in the embodiments of the present utility model;

[0043] Figure 8 A seventh structural schematic diagram of the display device provided in this embodiment of the utility model;

[0044] Figure 9 This is an eighth structural schematic diagram of the display device provided in the embodiments of the present utility model;

[0045] Figure 10 A ninth structural schematic diagram of the display device provided in this embodiment of the utility model;

[0046] Figure 11 This is a tenth structural schematic diagram of the display device provided in an embodiment of the present utility model;

[0047] Figure 12 This is an eleventh structural schematic diagram of the display device provided in an embodiment of the present utility model;

[0048] Figure 13 A schematic diagram of the twelfth structure of the display device provided in this embodiment of the utility model;

[0049] Figure 14 This is a thirteenth structural schematic diagram of the display device provided in this embodiment of the utility model;

[0050] Figure 15 This is a schematic diagram of the fourteenth structure of the display device provided in this embodiment of the utility model;

[0051] Figure 16 This is a schematic diagram of the fifteenth structure of the display device provided in the embodiment of the present utility model. Detailed Implementation

[0052] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art based on the present utility model are within the protection scope of the present utility model.

[0053] First, the technical terms that may be used in the embodiments of this utility model will be explained:

[0054] Notebook display products: Notebook display products refer to the LCD displays and display panels used in portable electronic products such as laptops and tablets.

[0055] PSR (Panel Self-Refresh) is a power management technology used to reduce power consumption when the display is inactive. With PSR, the timing controller (TCON) can enter a low-power mode when display updates are not required, waking up and updating the display content only when needed, thus significantly reducing power consumption.

[0056] Overdrive (OD) function: Used to accelerate the response time of liquid crystal molecules, reducing ghosting and image retention. By increasing the amplitude and frequency of the driving voltage, the OD function can improve the dynamic sharpness and response speed of the LCD screen, thus improving image quality.

[0057] MSDA (Memory Serial Data Access) is a serial data access interface used for communication between the timing controller and external memory. It allows the timing controller to efficiently read and write data to memory, thereby improving overall system performance and response speed. The MSDA interface is typically used in conjunction with the IIC communication protocol to achieve serial data transmission.

[0058] IIC (Inter-Integrated Circuit) communication protocol: It is a serial communication protocol that is widely used for data transmission between various electronic devices.

[0059] EDP ​​(Embedded DisplayPort): is an internal digital interface based on the DisplayPort (a digital video interface standard) architecture and protocol. It is mainly used to connect LCD screens, supports high-resolution video signal transmission, and can transmit audio and control signals simultaneously.

[0060] A Zener diode is a diode that uses the reverse breakdown state of a PN junction, where the current can vary over a wide range while the voltage remains essentially constant, to regulate voltage. A Zener diode can maintain a stable voltage when the reverse voltage exceeds a certain value.

[0061] Clamping: Clamping refers to the measure of limiting the potential of a certain point to a specified potential, and is an overvoltage protection technology.

[0062] For a structural diagram of notebook-type display products, please refer to [link / reference]. Figure 1 The interface connector is used to connect with the front-end system to realize the transmission of various signals. The main functions of the timing controller TCON are as follows: The timing controller TCON communicates directly with the front-end system through the interface connector to realize functions such as PSR, MSDA, and OD; the timing controller TCON receives the EDP signal from the front-end system, decodes it, outputs the Data to the source driver, and transmits the GOA (Gate Driven on Array) signal to the signal amplifier, which then transmits the amplified GOA signal to the GOA module. The source driver receives the Data and transmits it to the pixel unit. The GOA module receives the GOA signal and outputs the gate scan signal to the pixel unit based on the GOA signal.

[0063] As notebook display products increasingly feature more functions, such as OD (Optical Disk Response) and PSR (Pressure Sensitivity) functions, etc. Figure 1 As shown, the implementation of these functions requires the GPU of the front-end system to train with the LCD display panel. Due to the limited number of pins on the interface connector, there is a problem that there is no ground pin to isolate the high voltage transmission pins (such as the backlight illumination voltage transmission pin VLED_IN, the typical value of the backlight illumination voltage VLED is 12V, and the maximum value is 21V) from the above-mentioned functional pins. This may cause the backlight illumination voltage to be introduced into the adjacent functional pins, damaging the timing controller TCON (the withstand voltage of the timing controller is about 5V), which in turn leads to display abnormalities in the display product.

[0064] To address the aforementioned problems, this utility model provides a display device, which will be described in detail below.

[0065] See Figure 2 This is a schematic diagram of a first structure of a display device provided in an embodiment of the present utility model. The display device 1 includes a clamping voltage regulator circuit 11, a display interface 12, and a timing controller 13.

[0066] The clamping voltage regulator circuit 11 includes a voltage regulator module 111 and a current limiting module 112;

[0067] The first end of the current limiting module 112 is connected to the display interface 12, and the second end of the current limiting module 112 is connected to the voltage regulator module 111 and the timing controller 13 respectively.

[0068] The current limiting module 112 is used to limit the large current when there is a large voltage intrusion in the timing controller 13.

[0069] The voltage regulator module 111 is used to clamp the voltage of the timing controller 13 within its own withstand voltage range when a large voltage intrusion occurs.

[0070] The current limiting module 112 and the voltage regulating module 111 work together to protect the timing controller 13. The specific working process will be explained in detail below.

[0071] In one example, when the backlight voltage VLED is serially connected from the backlight voltage transmission pin VLED_IN of the display interface 12 to the adjacent pin of the timing controller 13, that is, when the large backlight voltage VLED enters the timing controller 13, the current limiting module 112 and the voltage regulator module 111 work together to protect the timing controller 13 and reduce the risk of damage to the timing controller 13.

[0072] The voltage regulator module 111 can be a module that only includes a Zener diode, or it can be a module that combines a Zener diode with other devices. This utility model does not specifically limit it in this way.

[0073] The display interface 12 can be an LVDS interface (Low Voltage Differential Signaling) or other types of display interfaces. This utility model does not specifically limit it in this regard.

[0074] In this embodiment of the utility model, by connecting a voltage regulator module 111 and a current limiting module 112 between the display interface 12 and the timing controller 13, when a large voltage intrusion occurs in the timing controller 13, the current limiting module 112 is used to limit the large current, and the voltage regulator module 111 is used to clamp the voltage of the timing controller 13, thereby reducing the risk of damage to the timing controller 13, improving the display abnormality problem of the display product, increasing the service life of the display product, and enhancing the quality and competitiveness of the display product.

[0075] In one possible implementation, see Figure 3 The current limiting module 112 includes a current limiting resistor R, and the voltage regulating module 111 includes at least one Zener diode D;

[0076] The first end of the current limiting resistor R is connected to the display interface 12, and the second end of the current limiting resistor R is connected to the first end of the Zener diode D and the timing controller 13, respectively.

[0077] The second terminal of the Zener diode D is grounded to GND.

[0078] The voltage regulator module 111 may include only one Zener diode or multiple Zener diodes. This invention does not specifically limit the number of Zener diodes.

[0079] The current limiting module 112 may include one current limiting resistor or multiple current limiting resistors. This utility model does not specifically limit the number of current limiting resistors.

[0080] Understandable Figure 3 The current limiting module 112 includes a current limiting resistor R, and the voltage regulating module 111 includes a voltage regulating diode D, as illustrated in the diagram.

[0081] Multiple Zener diodes D connected in parallel can shunt the current after it has been limited by the current-limiting resistor R, thereby increasing the upper limit of the voltage withstand capability of the clamping voltage regulator circuit 11. In other words, the more Zener diodes D connected in parallel, the higher the clamping voltage can be.

[0082] In this embodiment of the invention, by connecting a Zener diode D and a current-limiting resistor R between the display interface 12 and the timing controller 13, the current-limiting resistor R limits the large current when there is a large voltage intrusion into the timing controller 13, and the Zener diode D clamps the voltage of the timing controller 13, thereby reducing the risk of damage to the timing controller 13, improving display abnormality problems of the display product, increasing the service life of the display product, and enhancing the quality and competitiveness of the display product.

[0083] In one possible implementation, see Figure 4 The first end of the current limiting resistor R is connected to the power consumption control pin PSR pin of the display interface 12, and the second end of the current limiting resistor R is connected to the first general purpose input / output pin GPIO1 pin of the timing controller 13 and the first end of the Zener diode D.

[0084] In one example, the backlight illumination voltage VLED is 12V, and the timing controller 13 has a withstand voltage of 5V. When this large backlight illumination voltage VLED is connected in series with the power consumption control pin PSR of the display interface 12, consider limiting (clamping) the voltage level of the first general-purpose input / output pin GPIO1 of the timing controller 13 to 3.3V. At this time, the current value in the circuit is I = (12V - 3.3V) / R, and the power consumption of the Zener diode D is 3.3 × I. However, when selecting the Zener diode D, its power consumption P needs to satisfy P > 3.3 × I, that is, the rated power of the Zener diode D needs to be greater than its operating power to ensure that the Zener diode D can work normally. Due to the limitations of its own materials and cost, the power consumption of the Zener diode D is limited. Therefore, the smaller the current in the circuit, the better, that is, the larger the current limiting resistor R, the better. In one possible implementation, Figure 4 The current-limiting resistor R shown has a resistance range of 1kΩ to 2kΩ. In one example, Figure 4 The current-limiting resistor R shown can be 1kΩ.

[0085] Understandable Figure 4 The current limiting module 112 includes a current limiting resistor R, and the voltage regulating module 111 includes a voltage regulating diode D, as illustrated in the diagram.

[0086] In this embodiment of the invention, by setting a current-limiting resistor R and a Zener diode D between the power consumption control pin PSR of the display interface 12 and the first general-purpose input / output pin GPIO1 of the timing controller 13, when the backlight illumination voltage VLED is connected in series with the PSR pin of the display interface 12, the current is limited by the current-limiting resistor R, and the voltage of the GPIO1 pin of the timing controller 13 is clamped by the Zener diode D. Compared with the related technology in which "the PSR pin of the display interface is directly connected to the GPIO1 pin of the timing controller, without the current-limiting resistor R and without the Zener diode D, when the backlight illumination voltage VLED is connected in series with the PSR pin of the display interface, the backlight illumination voltage VLED will enter the timing controller through the PSR pin, causing damage to the timing controller and thus causing abnormal display of the display product", the risk of damage to the timing controller 13 is reduced, and the display abnormality problem of the display product is improved.

[0087] In one possible implementation, based on Figure 4 The circuit structure shown is described in the following example. Figure 5 The display device 1 also includes a first pull-up resistor R1. The first end of the first pull-up resistor R1 is connected to the first power supply voltage terminal VDD1, and the second end of the first pull-up resistor R1 is connected to the second end of the current limiting resistor R, the first end of the Zener diode D, and the first general-purpose input / output pin GPIO1 of the timing controller 13.

[0088] In one example, the power supply voltage of the first power supply voltage terminal VDD1 can be 1.8V.

[0089] In one possible implementation, based on Figure 4 The circuit structure shown is described in the following example. Figure 6 The display device 1 further includes a graphics processor 14;

[0090] The power control pin PSR of the graphics processor 14 is connected to the power control pin PSR of the display interface 12.

[0091] The graphics processor 14 is used to transmit power control signals to the display interface 12.

[0092] In one possible implementation, see Figure 7 The first end of the current limiting resistor R is connected to the display delay control pin OD of the display interface 12, and the second end of the current limiting resistor R is connected to the second general purpose input / output pin GPIO2 of the timing controller 13 and the first end of the Zener diode D.

[0093] In one example, the backlight illumination voltage VLED is 12V, and the timing controller 13 has a withstand voltage of 5V. When this large backlight illumination voltage VLED is connected in series with the display delay control pin OD of the display interface 12, consider limiting (clamping) the voltage level of the second general-purpose input / output pin GPIO2 of the timing controller 13 to 3.3V. At this time, the current value in the circuit is I = (12V - 3.3V) / R, and the power consumption of the Zener diode D is 3.3 × I. However, when selecting the Zener diode D, its power consumption P needs to satisfy P > 3.3 × I, that is, the rated power of the Zener diode D needs to be greater than its operating power to ensure that the Zener diode D can work normally. Due to the limitations of its own materials and cost, the power consumption of the Zener diode D is limited. Therefore, the smaller the current in the circuit, the better, that is, the larger the current limiting resistor R, the better. In one possible implementation, Figure 7 The current-limiting resistor R shown has a resistance range of 1kΩ to 2kΩ. In one example, Figure 7 The current-limiting resistor R shown can be 1kΩ.

[0094] Understandable Figure 7 The current limiting module 112 includes a current limiting resistor R, and the voltage regulating module 111 includes a voltage regulating diode D, as illustrated in the diagram.

[0095] In this embodiment of the invention, by setting a current-limiting resistor R and a Zener diode D between the display delay control pin (OD pin) of the display interface 12 and the second general-purpose input / output pin (GPIO2 pin) of the timing controller 13, when the backlight illumination voltage VLED is connected in series with the OD pin of the display interface 12, the current-limiting resistor R limits the current, and the Zener diode D clamps the voltage of the GPIO2 pin of the timing controller 13. Compared with related technologies where "the OD pin of the display interface is directly connected to the GPIO2 pin of the timing controller, without a current-limiting resistor R or a Zener diode D, and the backlight illumination voltage VLED enters the timing controller through the OD pin, causing damage to the timing controller and consequently leading to abnormal display of the display product," the risk of damage to the timing controller 13 is reduced, and the display abnormality problem of the display product is improved.

[0096] In one possible implementation, based on Figure 7 The circuit structure shown is described in the following example. Figure 8 The display device 1 also includes a second pull-up resistor R2. The first end of the second pull-up resistor R2 is connected to the first power supply voltage terminal VDD1, and the second end of the second pull-up resistor R2 is connected to the second end of the current limiting resistor R, the first end of the Zener diode D, and the second general-purpose input / output pin GPIO2 of the timing controller 13.

[0097] In one example, the power supply voltage of the first power supply voltage terminal VDD1 can be 1.8V.

[0098] In one possible implementation, based on Figure 7 The circuit structure shown is described in the following example. Figure 9 The display device 1 further includes a graphics processor 14;

[0099] The display delay control pin OD of the graphics processor 14 is connected to the display delay control pin OD of the display interface 12.

[0100] The graphics processor 14 is used to transmit display delay control signals to the display interface 12.

[0101] In one possible implementation, Figures 4-9 The current-limiting resistor R shown has a resistance range of 1kΩ to 2kΩ. In one example, Figures 4-9 The current-limiting resistor R shown can be 1kΩ.

[0102] In one possible implementation, see Figure 10 The first end of the current limiting resistor R is connected to the serial data transmission pin MSDA1 of the display interface 12, and the second end of the current limiting resistor R is connected to the serial data transmission pin MSDA2 of the timing controller 13 and the first end of the Zener diode D.

[0103] Understandable Figure 10 The current limiting module 112 includes a current limiting resistor R, and the voltage regulating module 111 includes a voltage regulating diode D, as illustrated in the diagram.

[0104] In this embodiment of the invention, by setting a current-limiting resistor R and a Zener diode D between the serial data transmission pin MSDA1 of the display interface 12 and the serial data transmission pin MSDA2 of the timing controller 13, when the backlight lighting voltage VLED is connected in series to the MSDA1 pin of the display interface 12, the current-limiting resistor R limits the current, and the Zener diode D clamps the voltage of the MSDA2 pin of the timing controller 13, thereby reducing the risk of damage to the timing controller 13 and improving the display abnormality problem of the display product.

[0105] In one possible implementation, based on Figure 10 The circuit structure shown is described in the following example. Figure 11The display device 1 also includes a graphics processor 14, a third pull-up resistor R3, and a fourth pull-up resistor R4. The serial data transmission pin MSDA3 of the graphics processor 14 is connected to the serial data transmission pin MSDA1 of the display interface 12 and the second end of the third pull-up resistor R3, respectively. The first end of the third pull-up resistor R3 is connected to the second power supply voltage terminal VDD2.

[0106] The first end of the fourth pull-up resistor R4 is connected to the first power supply voltage terminal VDD1, and the second end of the fourth pull-up resistor R4 is connected to the second end of the current limiting resistor R, the first end of the Zener diode D, and the serial data transmission pin MSDA2 of the timing controller 13.

[0107] Where Va is the voltage level of the serial data transmission pin MSDA3 of the graphics processor 14, Vb is the voltage level of the serial data transmission pin MSDA2 of the timing controller 13, L1 represents the first voltage divider circuit, and L2 represents the second voltage divider circuit.

[0108] The graphics processor 14 is used to transmit serial data signals to the display interface 12.

[0109] In one example, the power supply voltage at the first power supply terminal VDD1 can be 1.8V. In another example, the power supply voltage at the second power supply terminal VDD2 can be 3.3V.

[0110] The serial data signal (IIC communication protocol) is a bidirectional serial bus signal that enables the mutual transmission of serial data signals between the graphics processor 14 and the timing controller 13. When designing a clamping and regulating circuit for digital communication signals such as serial data signals, it is necessary to fully consider the signal integrity to ensure that the graphics processor 14 and the timing controller 13 can recognize the serial data signal and ensure the reliability of the circuit.

[0111] The impact of the current-limiting resistor R on the integrity of the serial data signal is as follows: When the output of the timing controller 13 is Vb=0V, referring to the voltage divider circuit of the first voltage divider circuit L1, Va=3.3V×R / (R3+R). Similarly, when the output of the graphics processor 14 is Va=0V, referring to the voltage divider circuit of the second voltage divider circuit L2, Vb=1.8V×R / (R4+R). From the above logic, it can be seen that the smaller the value of the current-limiting resistor R, the better the signal integrity of the serial data signal.

[0112] As mentioned earlier, in one example, the backlight illumination voltage VLED is 12V, and the timing controller 13 has a withstand voltage of 5V. When this large backlight illumination voltage VLED is connected in series to the serial data transmission pin MSDA1 of the display interface 12, the voltage level of the serial data transmission pin MSDA2 of the timing controller 13 is considered to be limited (clamped) to 3.3V. At this time, the current value in the circuit is I = (12V - 3.3V) / R, and the power consumption of the Zener diode D is 3.3 × I. However, when selecting the Zener diode D, its power consumption P needs to satisfy P > 3.3 × I, that is, the rated power of the Zener diode D needs to be greater than its operating power to ensure that the Zener diode D can work normally. Due to the limitations of its own materials and cost, the power consumption of the Zener diode D is limited. Therefore, the smaller the current in the circuit, the better, that is, the larger the current limiting resistor R, the better. From the above logic, it can be seen that from the perspective of current limiting, the larger the resistance value of the current limiting resistor R, the better.

[0113] In summary, in one possible implementation, Figure 10 and Figure 11 The current-limiting resistor R shown has a resistance range of 100Ω to 200Ω. In one example, Figure 10 and Figure 11 The resistance value of the current-limiting resistor R shown can be 100Ω.

[0114] In this embodiment of the invention, by setting a current-limiting resistor R and a Zener diode D between the serial data transmission pin MSDA1 of the display interface 12 and the serial data transmission pin MSDA2 of the timing controller 13, when the backlight illumination voltage VLED is connected in series with the MSDA1 pin of the display interface 12, the current-limiting resistor R limits the current, and the Zener diode D clamps the voltage of the MSDA2 pin of the timing controller 13. Compared with the related technology where "the MSDA1 pin of the display interface is directly connected to the MSDA2 pin of the timing controller, without a current-limiting resistor R or a Zener diode D, when the backlight illumination voltage VLED is connected in series with the MSDA1 pin of the display interface, the backlight illumination voltage VLED will enter the timing controller through the MSDA1 pin, causing damage to the timing controller and thus causing abnormal display of the display product," the risk of damage to the timing controller 13 is reduced, and the display abnormality problem of the display product is improved.

[0115] In one possible implementation, see Figure 12 The display device 1 includes a current-limiting resistor R, a first Zener diode D1, a second Zener diode D2, a first pull-up resistor R1, a display interface 12, a graphics processor 14, and a timing controller 13.

[0116] The power control pin PSR of the graphics processor 14 is connected to the power control pin PSR of the display interface 12.

[0117] The first end of the current limiting resistor R is connected to the power consumption control pin PSR pin of the display interface 12, and the second end of the current limiting resistor R is connected to the first general purpose input / output pin GPIO1 pin of the timing controller 13, the first end of the first Zener diode D1, the first end of the second Zener diode D2, and the second end of the first pull-up resistor R1.

[0118] The first terminal of the first pull-up resistor R1 is connected to the first power supply voltage terminal VDD1;

[0119] The second terminal of the first Zener diode D1 is grounded to GND, and the second terminal of the second Zener diode D2 is grounded to GND.

[0120] As mentioned earlier, due to limitations in materials and cost, the power consumption of the Zener diode D is limited, thus restricting the upper limit of the clamping voltage regulator circuit. Connecting two Zener diodes D (first Zener diode D1 and second Zener diode D2) in parallel can shunt the current limited by the current-limiting resistor R, thereby increasing the upper limit of the clamping voltage regulator circuit's withstand voltage. In one example, with one Zener diode D in the circuit, the clamping voltage regulator circuit can withstand a maximum voltage of 12V; by connecting another Zener diode D in parallel, the clamping voltage regulator circuit can withstand a maximum voltage of 24V.

[0121] In one possible implementation, see Figure 13 The display device 1 includes a current-limiting resistor R, a first Zener diode D1, a second Zener diode D2, a second pull-up resistor R2, a display interface 12, a graphics processor 14, and a timing controller 13.

[0122] The display delay control pin OD of the graphics processor 14 is connected to the display delay control pin OD of the display interface 12;

[0123] The first end of the current limiting resistor R is connected to the display delay control pin OD of the display interface 12, and the second end of the current limiting resistor R is connected to the second general-purpose input / output pin GPIO2 of the timing controller 13, the first end of the first Zener diode D1, the first end of the second Zener diode D2, and the second end of the second pull-up resistor R2.

[0124] The first terminal of the second pull-up resistor R2 is connected to the first power supply voltage terminal VDD1;

[0125] The second terminal of the first Zener diode D1 is grounded to GND, and the second terminal of the second Zener diode D2 is grounded to GND.

[0126] As mentioned earlier, due to limitations in materials and cost, the power consumption of the Zener diode D is limited, thus restricting the upper limit of the clamping voltage regulator circuit. Connecting two Zener diodes D (first Zener diode D1 and second Zener diode D2) in parallel can shunt the current limited by the current-limiting resistor R, thereby increasing the upper limit of the clamping voltage regulator circuit's withstand voltage. In one example, with one Zener diode D in the circuit, the clamping voltage regulator circuit can withstand a maximum voltage of 12V; by connecting another Zener diode D in parallel, the clamping voltage regulator circuit can withstand a maximum voltage of 24V.

[0127] In one possible implementation, see Figure 14 The display device 1 includes a current-limiting resistor R, a first Zener diode D1, a second Zener diode D2, a third pull-up resistor R3, a fourth pull-up resistor R4, a display interface 12, a graphics processor 14, and a timing controller 13.

[0128] The serial data transmission pin MSDA3 of the graphics processor 14 is connected to the serial data transmission pin MSDA1 of the display interface 12 and the second end of the third pull-up resistor R3, respectively. The first end of the third pull-up resistor R3 is connected to the second power supply voltage terminal VDD2.

[0129] The first end of the current limiting resistor R is connected to the serial data transmission pin MSDA1 of the display interface 12, and the second end of the current limiting resistor R is connected to the serial data transmission pin MSDA2 of the timing controller 13, the first end of the first Zener diode D1, the first end of the second Zener diode D2, and the second end of the fourth pull-up resistor R4.

[0130] The first terminal of the fourth pull-up resistor R4 is connected to the first power supply voltage terminal VDD1;

[0131] The second terminal of the first Zener diode D1 is grounded to GND, and the second terminal of the second Zener diode D2 is grounded to GND.

[0132] As mentioned earlier, due to limitations in materials and cost, the power consumption of the Zener diode D is limited, thus restricting the upper limit of the clamping voltage regulator circuit. Connecting two Zener diodes D (first Zener diode D1 and second Zener diode D2) in parallel can shunt the current limited by the current-limiting resistor R, thereby increasing the upper limit of the clamping voltage regulator circuit's withstand voltage. In one example, with one Zener diode D in the circuit, the clamping voltage regulator circuit can withstand a maximum voltage of 12V; by connecting another Zener diode D in parallel, the clamping voltage regulator circuit can withstand a maximum voltage of 24V.

[0133] In one possible implementation, see Figure 15 The display device 1 further includes a display panel 15;

[0134] The display panel 15 is connected to the timing controller 13.

[0135] In one possible implementation, see Figure 16 The display device 1 also includes a driver 16 and a power board 17;

[0136] The backlight illumination voltage output pin VLED1 of the power board 17 is connected to the backlight illumination voltage transmission pin VLED_IN of the display interface 12, the backlight illumination voltage transmission pin VLED_IN of the display interface 12 is connected to the backlight illumination voltage input pin VLED2 of the driver 16, and the backlight illumination voltage output pin VLED3 of the driver 16 is connected to the display panel 15.

[0137] In one possible implementation, the clamping voltage regulator circuit 11 provided by this invention can also be applied to other functional pins of the display interface 12.

[0138] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model are included within the scope of protection of this utility model.

Claims

1. A display device, characterized in that, The display device includes a clamping voltage regulator circuit, a display interface, and a timing controller. The clamping voltage regulator circuit includes a voltage regulator module and a current limiting module; The first end of the current limiting module is connected to the display interface, and the second end of the current limiting module is connected to the voltage regulator module and the timing controller respectively. The current limiting module includes a current limiting resistor, and the voltage regulating module includes at least one voltage regulating diode; The first end of the current-limiting resistor is connected to the display interface, and the second end of the current-limiting resistor is connected to the first end of the Zener diode and the timing controller, respectively. The second terminal of the Zener diode is grounded.

2. The display device according to claim 1, characterized in that, The first end of the current-limiting resistor is connected to the power consumption control pin of the display interface, and the second end of the current-limiting resistor is connected to the first general-purpose input / output pin of the timing controller and the first end of the Zener diode.

3. The display device according to claim 1, characterized in that, The first end of the current-limiting resistor is connected to the display delay control pin of the display interface, and the second end of the current-limiting resistor is connected to the second general-purpose input / output pin of the timing controller and the first end of the Zener diode.

4. The display device according to claim 1, characterized in that, The first end of the current-limiting resistor is connected to the serial data transmission pin of the display interface, and the second end of the current-limiting resistor is connected to the serial data transmission pin of the timing controller and the first end of the Zener diode, respectively.

5. The display device according to claim 2 or 3, characterized in that, The resistance value of the current-limiting resistor is in the range of 1kΩ to 2kΩ.

6. The display device according to claim 4, characterized in that, The resistance value of the current-limiting resistor ranges from 100Ω to 200Ω.

7. The display device according to claim 1, characterized in that, The display device further includes a graphics processor and a first pull-up resistor; the voltage regulator module includes a first Zener diode and a second Zener diode. The power control pin of the graphics processor is connected to the power control pin of the display interface. The first end of the current-limiting resistor is connected to the power consumption control pin of the display interface, and the second end of the current-limiting resistor is connected to the first general-purpose input / output pin of the timing controller, the first end of the first Zener diode, the first end of the second Zener diode, and the second end of the first pull-up resistor, respectively. The first end of the first pull-up resistor is connected to the first power supply voltage terminal; The second terminal of the first Zener diode is grounded, and the second terminal of the second Zener diode is also grounded.

8. The display device according to claim 1, characterized in that, The display device further includes a graphics processor and a second pull-up resistor; the voltage regulator module includes a first Zener diode and a second Zener diode. The display delay control pin of the graphics processor is connected to the display delay control pin of the display interface; The first end of the current-limiting resistor is connected to the display delay control pin of the display interface, and the second end of the current-limiting resistor is connected to the second general-purpose input / output pin of the timing controller, the first end of the first Zener diode, the first end of the second Zener diode, and the second end of the second pull-up resistor, respectively. The first terminal of the second pull-up resistor is connected to the first power supply voltage terminal; The second terminal of the first Zener diode is grounded, and the second terminal of the second Zener diode is also grounded.

9. The display device according to claim 1, characterized in that, The display device also includes a graphics processor, a third pull-up resistor, and a fourth pull-up resistor; The voltage regulator module includes a first voltage regulator diode and a second voltage regulator diode; The serial data transmission pin of the graphics processor is connected to the serial data transmission pin of the display interface and the second end of the third pull-up resistor, respectively, and the first end of the third pull-up resistor is connected to the second power supply voltage terminal. The first end of the current-limiting resistor is connected to the serial data transmission pin of the display interface, and the second end of the current-limiting resistor is connected to the serial data transmission pin of the timing controller, the first end of the first Zener diode, the first end of the second Zener diode, and the second end of the fourth pull-up resistor. The first end of the fourth pull-up resistor is connected to the first power supply voltage terminal; The second terminal of the first Zener diode is grounded, and the second terminal of the second Zener diode is also grounded.

10. The display device according to claim 1, characterized in that, The display device also includes a display panel, a driver, and a power board; The display panel is connected to the timing controller; The backlight power-on voltage output pin of the power board is connected to the backlight power-on voltage transmission pin of the display interface, the backlight power-on voltage transmission pin of the display interface is connected to the backlight power-on voltage input pin of the driver, and the backlight power-on voltage output pin of the driver is connected to the display panel.

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