Power management chip packaging structure

Abstract

The utility model provides a power management chip packaging structure. The power management chip packaging structure comprises at least two wafer bare chips and a control circuit, an upper tube and a lower tube are arranged in the at least two wafer bare chips, at least one of the upper tube and the lower tube and the control circuit are separately arranged in different wafer bare chips, and both the upper tube and the lower tube are LDMOS (Laterally Diffused Metal Oxide Semiconductor). Therefore, the number of mask plates used during manufacturing of the bare wafer can be reduced, the manufacturing cost of the bare wafer is reduced, the number and types of devices integrated in the same bare wafer are reduced, the mutual limitation between different devices in the same bare wafer is reduced, the manufacturing process of the bare wafer is convenient to optimize, and the production efficiency of the bare wafer is improved. Therefore, both the packaging cost and the performance of the packaging structure can be considered.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a power management chip packaging structure. Background Technology

[0002] Power management chips are responsible for the conversion, distribution, detection, and other power management functions of electrical energy in electronic equipment systems. Power management chips are indispensable to electronic systems, and their performance directly impacts the overall performance of the device.

[0003] Traditional power management chip packaging structures typically consist of a single-wafer die, using BCD (Bipolar-CMOS-DMOS) technology to integrate the control circuitry, upper-side transistor (PST), and lower-side transistor (PST) onto the same die. However, manufacturing the die using BCD technology requires a high number of mask layers, resulting in high manufacturing costs. Furthermore, due to structural limitations between different components, the processing of the PST and PST within the die cannot be optimized, impacting the overall performance of the die and the package structure.

[0004] Furthermore, traditional power management chip packaging structures typically mount the bare wafer onto a lead frame and use wire bonding technology to create bonding wires to achieve electrical connections between the bare wafer and the lead frame. Due to the need for lead frames and wire bonding technology, packaging costs are high, and the relatively long bonding wires formed between the bare wafer and the lead frame result in slower circuit transmission speeds, thus affecting the performance of the power management chip packaging structure. Utility Model Content

[0005] One of the objectives of this invention is to provide a power management chip packaging structure that can at least reduce the manufacturing cost of bare wafers, facilitate the optimization of the manufacturing process of bare wafers, and help to balance packaging cost and packaging structure performance.

[0006] To achieve the above objectives, the power management chip packaging structure provided by this utility model includes at least two wafer dies, which are integrated into a package. A control circuit, an upper transistor, and a lower transistor are disposed within the at least two wafer dies. At least one of the upper transistor and the lower transistor is disposed separately from the control circuit in a different wafer die. Both the upper transistor and the lower transistor are LDMOS.

[0007] Optionally, the at least two wafer dies include a first wafer die, a second wafer die, and a third wafer die, the control circuit is disposed in the first wafer die, the upper transistor is disposed in the second wafer die, and the lower transistor is disposed in the third wafer die.

[0008] Optionally, the at least two wafer dies include a first wafer die and a second wafer die, the control circuit is disposed in the first wafer die, and the upper transistor and the lower transistor are disposed in the second wafer die.

[0009] Optionally, the at least two wafer dies include a first wafer die and a second wafer die, the control circuit is disposed in the first wafer die, and one of the upper transistor and the lower transistor is disposed in the second wafer die and the other is disposed in the first wafer die.

[0010] Optionally, the power management chip packaging structure further includes a substrate, on which the at least two wafer dies are mounted.

[0011] Optionally, the substrate has one or more metal trace layers, and the substrate surface has exposed pads, which are electrically connected to the metal trace layers.

[0012] Optionally, the at least two wafer dies are flip chips, and the bumps on the front side of each wafer die are soldered to the corresponding pads on the substrate surface.

[0013] Optionally, some of the wafer dies are flip chips, and other wafer dies are wire bonded chips. The bumps on the front side of the flip chip are soldered to the corresponding pads on the substrate surface, and the wire bonded chips are electrically connected to the corresponding pads on the substrate surface via bonding wires.

[0014] Optionally, the at least two wafer dies are laid flat on the substrate.

[0015] Optionally, the power management chip package structure further includes a decoupling capacitor, which is mounted on the substrate.

[0016] The power management chip packaging structure provided by this utility model includes at least two wafer dies. The control circuit, upper transistor, and lower transistor are disposed within the at least two wafer dies. The upper transistor and the lower transistor are laterally diffused metal-oxide-semiconductor (LDMOS) transistors, thus both the upper transistor and the lower transistor have high voltage withstand capability and high power handling capability. In this application, at least one of the upper transistor and the lower transistor is disposed separately from the control circuit in different wafer dies. This can reduce the number of masks used in wafer die manufacturing, reduce wafer die manufacturing cost, and reduce the number and types of devices integrated in the same wafer die. The mutual constraints between different devices in the same wafer die are reduced, which facilitates the optimization of wafer die manufacturing process, thereby balancing packaging cost and packaging structure performance.

[0017] Furthermore, the power management chip packaging structure also includes a substrate, on which the at least two bare wafers are mounted, thus avoiding the use of expensive lead frames and helping to reduce packaging costs.

[0018] Furthermore, at least some of the wafer dies are flip chips, and the bumps on the front side of the flip chip are soldered to the corresponding pads on the substrate surface. That is, the flip chip is directly connected to the substrate pads through the surface bumps, which reduces or even avoids the use of bonding wires (when all wafer dies are flip chips). This can improve the speed of electrical signal transmission and help improve the performance of the power management chip packaging structure. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a power management chip package structure in an embodiment of the present invention, in which the upper transistor, lower transistor, and control circuit are respectively disposed on different wafer dies.

[0020] Figure 2 This is a schematic diagram of a power management chip package structure in an embodiment of the present invention, in which the upper and lower transistors are separately disposed on the same wafer die.

[0021] Figure 3 This is a schematic diagram of a power management chip package structure in which one of the upper and lower transistors is integrated with the control circuit on the same wafer as an embodiment of the present invention.

[0022] Explanation of reference numerals in the attached drawings: 100-substrate; 201-first wafer die; 202-second wafer die; 203-third wafer die; 204-bump. Detailed Implementation

[0023] The power management chip packaging structure proposed in this utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this utility model will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this utility model.

[0024] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "at least two" or "more than" means two or more, and "at least one" can mean one, two, or more, unless otherwise explicitly specified.

[0025] It should be understood that the various embodiments are merely exemplary specific implementations of the manufacturing and application embodiments, and do not constitute a limitation on the scope of the manufacture and application of this utility model. Furthermore, the description of multiple embodiments is only for the purpose of more clearly illustrating the connotation of this utility model; however, the technical features of each embodiment are not unique to that embodiment, and all the features of each embodiment can also be considered as the features of a general embodiment. In some implementations, the technical features of the following multiple embodiments can also be related to and inspired by each other to constitute new embodiments.

[0026] In order to reduce the manufacturing cost of bare wafers, facilitate the optimization of the manufacturing process of bare wafers, and balance packaging cost and packaging structure performance, this utility model provides a power management chip packaging structure.

[0027] Figure 1 This is a schematic diagram of a power management chip package structure in an embodiment of the present invention, in which the upper transistor, lower transistor, and control circuit are respectively disposed on different wafer dies. Figure 2 This is a schematic diagram of a power management chip package structure in an embodiment of the present invention, in which the upper and lower transistors are separately disposed on the same wafer die. Figure 3 This is a schematic diagram of a power management chip package structure in which one of the upper and lower transistors is integrated with the control circuit on the same wafer as an embodiment of the present invention.

[0028] refer to Figures 1 to 3 As shown, the power management chip packaging structure provided in this application includes at least two wafer dies, which are integrated into a package. The control circuit, the upper transistor, and the lower transistor are disposed within the at least two wafer dies. At least one of the upper transistor and the lower transistor is disposed separately from the control circuit in a different wafer die. The upper transistor and the lower transistor are LDMOS.

[0029] In power management chips, the high-side and low-side transistors typically work in tandem to control current flow and energy conversion. Their operating principle depends on the specific circuit structure of the application. For example, in a common buck converter circuit, when the high-side transistor is on and the low-side transistor is off, the input power is stored in an energy storage element, simultaneously providing energy to the output. When the high-side transistor is off and the low-side transistor is on, the energy stored in the energy storage element is released to the output. By controlling the duty cycle of the high-side transistor, the output voltage can be controlled. A control circuit is used to control the alternating conduction of the high-side and low-side transistors.

[0030] In one embodiment of this application, as Figure 1As shown, the power management chip package structure includes a first wafer die 201, a second wafer die 202, and a third wafer die 203. The control circuit is located in the first wafer die 201, the upper transistor is located in the second wafer die 202, and the lower transistor is located in the third wafer die 203. By separately arranging the control circuit, the upper transistor, and the lower transistor in different wafer dies, the use of BCD process is avoided. This allows for optimal settings of the manufacturing process, performance, and cost of each wafer die, which helps to reduce manufacturing costs and improve wafer die performance.

[0031] In one embodiment of this application, as Figure 2 As shown, the power management chip package structure includes a first wafer die 201 and a second wafer die 202. The control circuit is disposed within the first wafer die 201, and both the upper and lower transistors are disposed within the second wafer die 202. Since both the upper and lower transistors are LDMOS, their processes are easily compatible, allowing the second wafer die 202 to be manufactured at a lower cost and with a more efficient process. Furthermore, the manufacturing of the first wafer die 201, which includes the control circuit, is not limited by LDMOS, and the fabrication process, performance, and cost of the first wafer die 201 can still be optimally configured. In addition, integrating the same type of upper and lower transistors into the same wafer die also helps to reduce the package size.

[0032] In one embodiment of this application, reference is made to... Figure 3 As shown, the power management chip package structure includes a first wafer die 201 and a second wafer die 202. The control circuit is disposed within the first wafer die 201. One of the upper transistor and the lower transistor is disposed within the second wafer die 202, and the other is disposed within the first wafer die 201. That is, the upper transistor or the lower transistor is integrated with the control circuit within the same wafer die. This integration can be chosen by comprehensively considering manufacturing costs, manufacturing processes, and wafer die performance. Specifically, in one embodiment, the upper transistor and the control circuit are integrated within the first wafer die 201, and the lower transistor is disposed within the second wafer die 202, which facilitates device arrangement and reduces manufacturing costs. In another embodiment, the lower transistor and the control circuit can also be integrated within the first wafer die 201, and the upper transistor is disposed within the second wafer die 202.

[0033] refer to Figures 1 to 3 As shown, the power management chip package structure also includes a substrate 100, on which the wafer dies in the power management chip package structure are mounted. Since the manufacturing cost of the substrate 100 is lower than that of the lead frame, using the substrate 100 to carry the wafer dies and to realize wafer die interconnection and wafer die lead-out through the substrate 100 helps to reduce the manufacturing cost of the package structure.

[0034] In some embodiments of this application, the wafer bare die within the packaging structure is laid flat on the substrate 100, such as... Figure 1 As shown, the first wafer die 201, the second wafer die 202, and the third wafer die 203 are laid flat on the substrate 100. In some other embodiments of this application, some wafer dies may also be stacked on top of other wafer dies.

[0035] The substrate 100 may include, but is not limited to, a printed circuit board. The substrate 100 may have one or more metal trace layers, and its surface may have multiple exposed pads that are electrically connected to the metal trace layers. Specifically, the multiple metal trace layers of the substrate 100 may be separated by dielectric layers, including but not limited to resin layers, and the multiple metal trace layers of the substrate 100 may be electrically connected through vias.

[0036] In some embodiments of this application, reference is made to Figures 1 to 3 As shown, the wafers in the power management chip package structure can all be flip chips, and the bumps 204 on the front side of each wafer are soldered to the corresponding pads on the surface of the substrate 100.

[0037] In some other embodiments of this application, a portion of the wafer dies within the power management chip packaging structure are flip chips, and another portion of the wafer dies are wire-bonded chips. The bumps on the front side of the flip chip are soldered to the corresponding pads on the surface of the substrate 100, and the wire-bonded chips are electrically connected to the corresponding pads on the surface of the substrate 100 via bonding wires.

[0038] Specifically, the flip chip is mounted face down on the substrate 100. The back side of the wire-bonded chip can be adhered to the corresponding pads on the substrate 100 using silver paste or similar materials. The front side of the wire-bonded chip can have multiple chip pads, which can be arranged along the edge area of ​​the front side of the wafer. One end of the bonding wire can be attached to the chip pad, and the other end can be attached to the corresponding pad on the surface of the substrate 100 to achieve electrical connection between the wafer and the substrate 100.

[0039] For example, the bump 204 on the front side of the wafer die can be a solder ball connected to the chip pad, or an externally protruding pad with an external solder layer, or a copper pillar, but is not limited to these.

[0040] For example, the front side of the wafer die for setting the LDMOS can have multiple bumps 204 that respectively lead out the source, drain and signal terminals of the LDMOS.

[0041] In some embodiments of this application, a portion of the pads in the edge region of the substrate 100 serve as lead pads. These lead pads are electrically connected to the bumps 204 of the wafer die or to the pads connected to the bonding wires via metal traces in the substrate, thereby enabling the wafer die to be led out. Exemplarily, the lead pads may be arranged along the four sides of the substrate 100, but are not limited thereto.

[0042] It should be noted that at least part of the wafer bare die in the power management chip packaging structure is a flip chip. The bumps 204 on the front side of the flip chip are soldered to the corresponding pads on the surface of the substrate 100. That is, the flip chip is directly connected to the pads of the substrate 100 through the surface bumps, which reduces the use of bonding wires, can improve the speed of electrical signal transmission, and helps to improve the performance of the power management chip packaging structure.

[0043] When some of the wafer dies in the power management chip package structure are wire-bonded chips, the pads on the surface of the corresponding substrate 100 can be arranged close to the wire-bonded chips. This allows for electrical connection between the wafer die and the substrate 100 with shorter bonding wires, which helps to improve signal transmission speed and the electrical performance of the package structure.

[0044] In some embodiments of this application, the wafer dies within the power management chip package structure can also be wire-bonded wafer dies.

[0045] refer to Figures 1 to 3 As shown, the power management chip package structure may further include decoupling capacitors (i.e., C1 and C2), which are mounted on the substrate 100. The decoupling capacitors can be capacitors installed at the power supply terminals of components in a circuit. These capacitors can provide a more stable power supply and reduce noise coupled from the component to the power supply terminal, indirectly reducing the impact of this component's noise on other components. The number of decoupling capacitors in the power management chip package structure includes, but is not limited to, two, and can be set as needed.

[0046] The power management chip packaging structure of this application may further include a molding layer (not shown), which is located on the substrate 100 and molds the at least two wafer dies, i.e., molds the wafer dies on the substrate 100; when the substrate 100 is also provided with bonding lines, the molding layer also wraps the bonding lines.

[0047] The power management chip packaging structure provided by this utility model includes at least two wafer dies. The control circuit, upper transistor, and lower transistor are disposed within the at least two wafer dies. The upper transistor and the lower transistor are LDMOS, which gives both the upper transistor and the lower transistor high voltage withstand capability, high power handling capability, and high reliability. In this application, at least one of the upper transistor and the lower transistor is disposed separately from the control circuit in different wafer dies. This reduces the number of photomasks used in wafer die manufacturing, reduces wafer die manufacturing costs, and reduces the number and types of devices integrated in the same wafer die. It also reduces the mutual constraints between different devices in the same wafer die, making it easier to optimize the wafer die manufacturing process, thereby balancing packaging cost and packaging structure performance.

[0048] Furthermore, the power management chip packaging structure also includes a substrate 100, on which the at least two bare wafers are mounted, thus avoiding the use of expensive lead frames and helping to reduce packaging costs.

[0049] Furthermore, at least some of the wafer dies are flip chips, and the bumps 204 on the front side of the flip chip are soldered to the corresponding pads on the surface of the substrate 100. That is, the flip chip is directly connected to the pads of the substrate 100 through the surface bumps, which reduces or even avoids the use of bonding wires (when all wafer dies are flip chips), which can improve the speed of electrical signal transmission and help improve the performance of the power management chip packaging structure.

[0050] The above description is only a description of the preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and techniques disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model shall fall within the protection scope of the technical solution of the present utility model.

Claims

1. A power management chip packaging structure, characterized in that, The device includes at least two wafer dies integrated into a package. A control circuit, an upper transistor, and a lower transistor are disposed within the at least two wafer dies. At least one of the upper transistor and the lower transistor is disposed separately from the control circuit in a different wafer die. Both the upper transistor and the lower transistor are LDMOS.

2. The power management chip packaging structure as described in claim 1, characterized in that, The at least two wafer dies include a first wafer die, a second wafer die, and a third wafer die. The control circuit is disposed in the first wafer die, the upper transistor is disposed in the second wafer die, and the lower transistor is disposed in the third wafer die.

3. The power management chip packaging structure as described in claim 1, characterized in that, The at least two wafer dies include a first wafer die and a second wafer die, the control circuit is disposed in the first wafer die, and the upper transistor and the lower transistor are disposed in the second wafer die.

4. The power management chip packaging structure as described in claim 1, characterized in that, The at least two wafer dies include a first wafer die and a second wafer die, the control circuit is disposed in the first wafer die, and one of the upper transistor and the lower transistor is disposed in the second wafer die and the other is disposed in the first wafer die.

5. The power management chip packaging structure as described in claim 1, characterized in that, It also includes a substrate, on which the at least two wafer dies are mounted.

6. The power management chip packaging structure as described in claim 5, characterized in that, The substrate has one or more metal trace layers, and the surface of the substrate has exposed pads, which are electrically connected to the metal trace layers.

7. The power management chip packaging structure as described in claim 5, characterized in that, The at least two wafer dies are flip chips, and the bumps on the front side of each wafer die are soldered to the corresponding pads on the substrate surface.

8. The power management chip packaging structure as described in claim 5, characterized in that, One part of the wafer dies are flip chips, and the other part of the wafer dies are wire bonded chips. The bumps on the front side of the flip chips are soldered to the corresponding pads on the surface of the substrate, and the wire bonded chips are electrically connected to the corresponding pads on the surface of the substrate through bonding wires.

9. The power management chip packaging structure as described in claim 5, characterized in that, The at least two wafers are laid flat on the substrate.

10. The power management chip packaging structure as described in claim 5, characterized in that, It also includes a decoupling capacitor mounted on the substrate.

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