Display device

Abstract

The utility model relates to a display device. According to the embodiment of the invention, the display device comprises a first sub-pixel and a second sub-pixel, a first initialization transistor including a voltage supplying initialization power to an anode electrode of the first light emitting element when a first scan signal is supplied to the first scan line, and a first boost capacitor connected between the first scan line and the anode electrode of the first light emitting element; and a second sub-pixel including a second initialization transistor that supplies a voltage of initialization power to the anode electrode of the second light emitting element when the first scan signal is supplied to the first scan line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0006916, filed on January 16, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to pixels and display devices including pixels. Background Technology

[0004] With the development of information technology, the importance of display devices as the connection medium between users and information has become increasingly prominent. In response, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) is increasing.

[0005] Display devices use pixels to display images. A pixel can include a first subpixel, a second subpixel, and a third subpixel that emit different colors of light, and each of the subpixels can be connected to various power lines. To ensure design freedom for subpixels or to apply subpixels to high-resolution (and high pixels per inch (PPI)) display panels, it is necessary to minimize the number of power lines connected to the subpixels. Utility Model Content

[0006] The purpose of this disclosure is to provide pixels and display devices including pixels that can minimize the number of power lines connected to subpixels.

[0007] According to an embodiment of the present disclosure, a pixel includes: a first transistor connected between a first electric field line and a second electric field line and having a gate electrode connected to a first node; a light-emitting element connected between the first electric field line and the second electric field line; an initialization transistor connected between a third electric field line and an anode electrode of the light-emitting element and having a gate electrode connected to a first scan line; and a boost capacitor connected between the first scan line and the anode electrode of the light-emitting element.

[0008] According to an embodiment, the pixel further includes: a second transistor connected between the data line and a second node to which the first electrode of the first transistor is connected and having a gate electrode connected to the second scan line; a third transistor connected between the first node and a third node to which the second electrode of the first transistor is connected and having a gate electrode connected to the third scan line; a fourth transistor connected between the first node and the fourth power line and having a gate electrode connected to the fourth scan line; a fifth transistor connected between the first power line and the second node and having a gate electrode connected to the emission control line; a sixth transistor connected between the third node and the anode electrode of the light emitting element and having a gate electrode connected to the emission control line; and a storage capacitor connected between the first power line and the first node.

[0009] According to an embodiment, the third transistor and the fourth transistor are N-type transistors, and the first transistor, the second transistor, the fifth transistor, the sixth transistor, and the initialization transistor are P-type transistors.

[0010] According to an embodiment, the first transistor further includes a second gate electrode electrically connected to the first power line.

[0011] According to an embodiment of the disclosure, the display apparatus includes: a first sub-pixel including a first initialization transistor providing a voltage of an initialization power to an anode electrode of a first light emitting element when a first scan signal is provided to a first scan line, and a first boost capacitor connected between the first scan line and the anode electrode of the first light emitting element; and a second sub-pixel including a second initialization transistor providing a voltage of an initialization power to an anode electrode of a second light emitting element when the first scan signal is provided to the first scan line.

[0012] According to an embodiment, the second sub-pixel does not include a boost capacitor connected between the first scan line and the anode electrode of the second light emitting element.

[0013] According to an embodiment, the second light emitting element emits red light, and the first light emitting element emits light of a color different from the red light.

[0014] According to an embodiment, the display apparatus further includes: a third sub-pixel including a third initialization transistor providing a voltage of an initialization power to an anode electrode of a third light emitting element when the first scan signal is provided to the first scan line, and a second boost capacitor connected between the first scan line and the anode electrode of the third light emitting element.

[0015] According to an embodiment, the first boost capacitor and the second boost capacitor have the same capacitance.

[0016] According to an embodiment, the first boost capacitor and the second boost capacitor have different capacitances.

[0017] According to an embodiment, the display apparatus includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel including a first pixel electrode layer, the second sub-pixel including a second pixel electrode layer, and the third sub-pixel including a third pixel electrode layer, and a first scan line extending in a first direction and electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel. The first pixel electrode layer and the third pixel electrode layer overlap at least a portion of the first scan line, and the second pixel electrode layer does not overlap the first scan line.

[0018] According to an embodiment, the first scan line includes a first protrusion protruding in a second direction different from the first direction and at least partially overlapping the first pixel electrode layer, and a second protrusion protruding in the second direction and at least partially overlapping the third pixel electrode layer.

[0019] According to an embodiment, the display apparatus further includes a first branch branched from the first pixel electrode layer and at least partially overlapping the first protrusion.

[0020] According to an embodiment, the display apparatus further includes a second branch branched from the third pixel electrode layer and at least partially overlapping the second protrusion.

[0021] According to an embodiment, the first sub-pixel is a green sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a blue sub-pixel.

[0022] According to an embodiment, the pixel electrode layers including the first pixel electrode layer, the second pixel electrode layer, and the third pixel electrode layer are located in different layers from the first scan line.

[0023] According to an embodiment, the pixel electrode layers are located above the first scan line in a cross-sectional view.

[0024] The objects of the present disclosure are not limited to the above-mentioned objects, and other technical objects not described will be clearly understood by those skilled in the art from the following description.

[0025] According to the pixel and the display apparatus including the same according to the embodiments of the present disclosure, an anode electrode of a light emitting element included in each of the sub-pixels can receive a voltage of an initialization power from one power line. Further, in the present disclosure, a boost capacitor can be used to differently set anode electrode voltages of the light emitting elements included in each of the sub-pixels.

[0026] However, the effects of the present disclosure are not limited to the above-mentioned effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0027] The above and other features of this disclosure will become more apparent from a more detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0029] Figure 2 It is shown that it includes Figure 1 A diagram illustrating an implementation of a scan driver in a display device;

[0030] Figure 3A and Figure 3B It is shown that it includes Figure 1 A diagram illustrating an implementation of the first sub-pixel in a display device;

[0031] Figure 4A and Figure 4B It is shown that it includes Figure 1 A diagram illustrating an implementation of the second sub-pixel in a display device;

[0032] Figure 5 This is a diagram illustrating sub-pixels according to embodiments of the present disclosure;

[0033] Figure 6A and Figure 6B This is a diagram illustrating an implementation of the signal provided to a sub-pixel during a frame period;

[0034] Figure 7 It is a diagram showing the voltage of the fourth node in each of the sub-pixels corresponding to the first scan signal;

[0035] Figure 8A This is a schematic cross-sectional view showing the first sub-pixel;

[0036] Figure 8B This is a diagram showing a schematic cross-sectional view of the second sub-pixel; and

[0037] Figure 9 It is a schematic planar view showing the first to third sub-pixels. Detailed Implementation

[0038] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the embodiments described herein.

[0039] For clarity in describing this disclosure, parts irrelevant to the description have been omitted, and throughout the specification, the same or similar elements are indicated by the same reference numerals. Therefore, the aforementioned reference numerals may be used in other figures.

[0040] Further, the size and thickness of each component shown in the drawings are arbitrarily shown for ease of description, and thus the present disclosure is not necessarily limited to those shown in the drawings. In the drawings, the thickness can be exaggerated for clarity.

[0041] Further, the expression "is the same" in the specification can mean "is substantially the same". That is, the expression "is the same" can be sufficiently the same for the person of ordinary skill to understand it as the same. Other expressions can also be expressions in which "substantially" is omitted.

[0042] Some embodiments are described in the drawings about functional blocks, units and / or modules. Those skilled in the art will understand that such blocks, units and / or modules are physically implemented by logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, line connectors and other electronic circuitry. This can be formed using semiconductor-based manufacturing technology or other manufacturing technology. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform various functions discussed herein, and selectively can be driven by firmware and / or software. Further, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically separated into two or more separate blocks, units and / or modules that interact, without departing from the scope of the present disclosure. Further, in some embodiments, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules, without departing from the scope of the present disclosure.

[0043] The term "connection" between two configurations can mean that both electrical connection and physical connection are included for use, but is not limited thereto. For example, "connection" used based on a circuit diagram can mean electrical connection, and "connection" used based on a sectional view and a plan view can mean physical connection.

[0044] Although first, second, etc. are used to describe various components, the components are not limited by these terms. These terms are used only to distinguish one component from another component. Thus, the first component described below can be the second component within the technical spirit of the present disclosure. The singular expression includes the plural expression, unless the context clearly indicates otherwise.

[0045] Meanwhile, the present disclosure is not limited to the embodiments disclosed below and can be variously modified and implemented. Also, each of the embodiments disclosed below can be implemented alone or in combination with at least one of the other embodiments.

[0046] Figure 1 FIG. 1 is a diagram illustrating a display apparatus according to an embodiment of the present disclosure.

[0047] Referring to Figure 1 The display apparatus 10 can include a pixel unit 100, a scan driver 200, an emission driver 300, a data driver 400, and a timing controller 500.

[0048] The display apparatus 10 can display an image at various frame frequencies (driving frequencies, refresh rates, or picture reproduction rates) according to driving conditions. The frame frequency is a frequency at which a data voltage is substantially written to a driving transistor of a sub-pixel PX (or a pixel) per second. For example, the frame frequency is also referred to as a picture scanning rate or a picture reproduction frequency, and indicates a frequency at which a picture is reproduced per second.

[0049] In an embodiment, an output frequency of a second scan signal provided from a second scan line SL2 and / or a data signal provided from the data driver 400 can be changed in response to a frame frequency. For example, the frame frequency for a moving image driving can be a frequency of about 60 Hz or more (e.g., 120 Hz or 240 Hz). When the frame frequency is 60 Hz, the second scan signal can be provided to each horizontal line (or pixel row) 60 times per second.

[0050] In an embodiment, the display apparatus 10 can adjust output frequencies of the scan driver 200 and the emission driver 300 and an output frequency of the data driver 400 corresponding to the output frequencies of the scan driver 200 and the emission driver 300 according to driving conditions. For example, the display apparatus 10 can display an image in response to various frame frequencies of 1 Hz to 120 Hz. However, this is an example, and the display apparatus 10 can display an image at a frame frequency of 120 Hz or more (e.g., 240 Hz or 480 Hz).

[0051] The pixel unit 100 can include scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n, emission control lines EL1 to ELn, and data lines DL1 to DLm, and can include sub-pixels PX connected to the scan lines SL11 to SL1n, SL21 to SL2n, SL31 to SL3n, and SL41 to SL4n, the emission control lines EL1 to ELn, and the data lines DL1 to DLm (here, m and n are natural numbers greater than 2). Each of the sub-pixels PX can include a driving transistor and a plurality of switching transistors.

[0052] Each of the sub-pixels PX can externally emit one of a first color of light, a second color of light, and a third color of light. The first color, the second color, and the third color can be different colors. For example, the first color can be set as green, the second color can be set as red, and the third color can be set as blue. In another embodiment, the first color can be set as magenta, the second color can be set as cyan, and the third color can be set as yellow.

[0053] The timing controller 500 can receive input data Din and a control signal CS from a host system such as an application processor (AP) through a predetermined interface. The timing controller 500 can control driving timing of the scan driver 200, the emission driver 300, and the data driver 400. For example, the timing controller 500 can generate scan driving signals SCS, emission driving signals ECS, and data driving signals DCS, and provide the scan driving signals SCS, the emission driving signals ECS, and the data driving signals DCS to the scan driver 200, the emission driver 300, and the data driver 400, respectively. In addition, the timing controller 500 can correct (and / or rearrange) the input data Din to generate output data Dout, and provide the output data Dout to the data driver 400.

[0054] The scan driver 200 can receive the scan driving signals SCS from the timing controller 500, and provide a first scan signal, a second scan signal, a third scan signal, and a fourth scan signal to the first scan line SL1, the second scan line SL2, the third scan line SL3, and the fourth scan line SL4, respectively, based on the scan driving signals SCS.

[0055] Each of the first scan signal to the fourth scan signal can be set as a gate-on voltage corresponding to a type of a transistor to which a corresponding scan signal is provided. When the scan signal is provided, a transistor receiving the scan signal can be turned on. For example, a gate-on voltage of a scan signal provided to a P-channel metal oxide semiconductor (PMOS) transistor can be a logic low level, and a gate-on voltage of a scan signal provided to an N-channel metal oxide semiconductor (NMOS) transistor can be a logic high level. Hereinafter, the meaning of "providing a scan signal" can be understood as providing the scan signal in a logic level such that a transistor controlled thereby is turned on.

[0056] The emission driver 300 can receive an emission driving signal ECS from the timing controller 500, and provide an emission control signal to the emission control lines EL1 to ELn based on the emission driving signal ECS. For example, the emission driver 300 can generate the emission control signal by shifting an emission start signal included in the emission driving signal ECS using a clock signal. To this end, the emission driver 300 can include a shift register, and can sequentially provide the emission control signal to the emission control lines EL1 to ELn.

[0057] The emission control signal can be a gate-off voltage (e.g., a high voltage). When the emission control signal is provided, a transistor receiving the emission control signal can be turned off, and can be turned on in other cases. Hereinafter, the meaning of "providing the emission control signal" can be understood as providing the emission control signal in a logic level such that a transistor controlled thereby is turned off.

[0058] In Figure 1 , for convenience of description, each of the scan driver 200 and the emission driver 300 is illustrated as a single configuration, but the present disclosure is not limited thereto. According to design, the scan driver 200 can include a plurality of scan drivers each providing at least one of the first to fourth scan signals. Further, at least a part of the scan driver 200 and the emission driver 300 can be integrated into one driving circuit, module, or the like.

[0059] The data driver 400 can receive a data driving signal DCS and output data Dout from the timing controller 500. The data driver 400 can convert the output data Dout into an analog data signal (or a data voltage) in response to the data driving signal DCS. The data driver 400 can provide the data signal to the data lines DL1 to DLm. For example, the data driver 400 can provide the data signal to the data lines DL1 to DLm in synchronization with the second scan signals provided from the second scan lines SL21 to SL2n.

[0060] In an embodiment, the display apparatus 10 can further include a power supply. The power supply can provide a voltage of a first driving power VDD, a voltage of a second driving power VSS, a voltage of a first initialization power Vint1, and a voltage of a second initialization power Vint2 for driving the sub-pixel PX to the pixel unit 100.

[0061] Figure 2 is a view illustrating an embodiment of a scan driver included in a display apparatus of Figure 1 .

[0062] Referring to Figure 2 , the scan driver 200 can include a first scan driver 220, a second scan driver 240, a third scan driver 260, and a fourth scan driver 280.

[0063] The scan driving signal SCS can include first to fourth scan start signals FLM1 to FLM4. The first to fourth scan start signals FLM1 to FLM4 can be respectively provided to the first to fourth scan drivers 220 to 280. The width, the timing of the provision, etc. of the first to fourth scan start signals FLM1 to FLM4 can be determined according to the driving conditions of the sub-pixel PX and the frame frequency.

[0064] The first scan driver 220 can sequentially provide the first scan signal to the first scan lines SL11 to SL1n in response to the first scan start signal FLM1. The second scan driver 240 can sequentially provide the second scan signal to the second scan lines SL21 to SL2n in response to the second scan start signal FLM2. The third scan driver 260 can sequentially provide the third scan signal to the third scan lines SL31 to SL3n in response to the third scan start signal FLM3. The fourth scan driver 280 can sequentially provide the fourth scan signal to the fourth scan lines SL41 to SL4n in response to the fourth scan start signal FLM4.

[0065] Figure 3A and Figure 3B is a diagram illustrating an embodiment of a first sub-pixel included in a display apparatus of Figure 1 is a diagram illustrating an embodiment of a first sub-pixel included in a display apparatus of Figure 3A and Figure 3B In

[0066] Referring to Figure 3A and Figure 3B The first sub-pixel PX1 according to an embodiment of the disclosure includes a first light emitting element LD1 and a pixel circuit for controlling the amount of current supplied to the first light emitting element LD1.

[0067] The first electrode (or anode electrode) of the first light emitting element LD1 can be connected to the fourth node N4, and the second electrode (or cathode electrode) of the first light emitting element LD1 can be connected to the second power line PL2 to which the second driving power VSS is supplied. The first light emitting element LD1 can generate light of a predetermined brightness in response to the amount of current supplied from the first transistor M1.

[0068] The first light emitting element LD1 can be an organic light emitting diode. Also, the first light emitting element LD1 can be an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode. Also, the first light emitting element LD1 can be an element in which an organic material and an inorganic material are combined. Figure 3A andFigure 3B In particular, the first sub-pixel PX1 includes a single first light emitting element LD1, but in another embodiment, the first sub-pixel PX1 can include a plurality of light emitting elements connected in series, in parallel, or in series-parallel with each other.

[0069] The pixel circuit can include first to seventh transistors M1 to M7, a storage capacitor Cst, and a boost capacitor Cb.

[0070] A first electrode of the first transistor M1 (or a driving transistor) can be connected to a second node N2, and a second electrode can be connected to a third node N3. In addition, a gate electrode of the first transistor M1 can be connected to a first node N1. The first transistor M1 can control an amount of current provided from a first driving power VDD to a second driving power VSS via the first light emitting element LD1 in response to a voltage of the first node N1. To this end, a voltage of the first driving power VDD can be set to be higher than a voltage of the second driving power VSS.

[0071] The second transistor M2 can be connected between the jth data line DLj and the second node N2. In addition, a gate electrode of the second transistor M2 can be connected to a second scan line SL2i. When a second scan signal is provided from the second scan line SL2i, the second transistor M2 can be turned on to electrically connect the jth data line DLj and the second node N2.

[0072] The third transistor M3 can be connected between the first node N1 and the third node N3. In addition, a gate electrode of the third transistor M3 can be connected to a third scan line SL3i. When a third scan signal is provided to the third scan line SL3i, the third transistor M3 can be turned on to electrically connect the first node N1 and the third node N3. When the third transistor M3 is turned on, the first transistor M1 is diode-connected.

[0073] The fourth transistor M4 is connected between the first node N1 and a fourth power line PL4 provided with a second initialization power Vint2. In addition, a gate electrode of the fourth transistor M4 is connected to a fourth scan line SL4i. When a fourth scan signal is provided from the fourth scan line SL4i, the fourth transistor M4 can be turned on to provide a voltage of the second initialization power Vint2 to the first node N1. Here, the voltage of the second initialization power Vint2 can be set to be lower than a voltage of a data signal provided from the jth data line DLj.

[0074] The fifth transistor M5 is connected between a first power line PL1 provided with the first driving power VDD and the second node N2. In addition, a gate electrode of the fifth transistor M5 can be connected to an emission control line ELi. When an emission control signal is provided to the emission control line ELi, the fifth transistor M5 can be turned off, and in other cases, can be turned on.

[0075] The sixth transistor M6 is connected between the third node N3 and the fourth node N4. In addition, a gate electrode of the sixth transistor M6 can be connected to the emission control line ELi. When an emission control signal is supplied from the emission control line ELi, the sixth transistor M6 can be turned off, and in other cases, can be turned on. Meanwhile, in Figure 3A and Figure 3B In the fifth transistor M5 and the sixth transistor M6 are connected to the same emission control line ELi, but the present disclosure is not limited thereto. In an embodiment, the fifth transistor M5 and the sixth transistor M6 can be connected to different emission control lines.

[0076] The seventh transistor M7 (an initialization transistor or a first initialization transistor) is connected between the fourth node N4 (i.e., the first electrode of the first light emitting element LD1) and the third power line PL3 to which the first initialization power Vint1 is supplied. In addition, a gate electrode of the seventh transistor M7 can be connected to the first scan line SL1i. When a first scan signal is supplied from the first scan line SL1i, the seventh transistor M7 can be turned on to supply a voltage of the first initialization power Vint1 to the fourth node N4.

[0077] When the voltage of the first initialization power Vint1 is supplied to the fourth node N4, a parasitic capacitor of the first light emitting element LD1 can be discharged. When a remaining voltage charged in the parasitic capacitor of the first light emitting element LD1 is discharged (or removed), unintended emission of the first light emitting element LD1 can be prevented. Accordingly, a black presentation ability of the first sub-pixel PX1 can be improved.

[0078] Meanwhile, the first initialization power Vint1 and the second initialization power Vint2 can be set to different voltages from each other. That is, a voltage for initializing the first node N1 and a voltage for initializing the fourth node N4 can be differently set. However, this is an example, and the voltage of the first initialization power Vint1 and the voltage of the second initialization power Vint2 can be substantially the same.

[0079] The storage capacitor Cst is connected between the first power line PL1 and the first node N1. The storage capacitor Cst can store a voltage applied to the first node N1.

[0080] The boost capacitor Cb is connected between the first scan line SL1i and the fourth node N4. The boost capacitor Cb can control a voltage of the fourth node N4 in response to a voltage of the first scan line SL1i. That is, the boost capacitor Cb can be driven as a coupling capacitor.

[0081] In this implementation, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be formed from polysilicon semiconductor transistors. For example, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 may include a polysilicon semiconductor layer formed by a low-temperature polysilicon (LTPS) process as an active layer (channel). Furthermore, the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be P-type transistors (e.g., PMOS transistors). Therefore, the gate on-state voltage that turns on the first transistor M1, the second transistor M2, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 can be a logic low level.

[0082] Because polysilicon semiconductor transistors have the advantage of fast response speed, they can be used as switching elements that require rapid switching.

[0083] In this implementation, the third transistor M3 and the fourth transistor M4 can be formed of oxide semiconductor transistors. For example, the third transistor M3 and the fourth transistor M4 can be N-type oxide semiconductor transistors (e.g., NMOS transistors) and can include an oxide semiconductor layer as an active layer. Therefore, the gate on-state voltage for turning on the third transistor M3 and the fourth transistor M4 can be a logic high level.

[0084] Oxide-semiconductor transistors (OSTs) can be formed at low temperatures and have a lower charge mobility than polysilicon transistors (PSTs). In other words, OSTs exhibit excellent cutoff current characteristics. Therefore, when the third transistor M3 and the fourth transistor M4 are formed from OSTs, the leakage current from the first node N1 when the sub-pixel PX is driven at a low frequency can be minimized, thus improving display quality.

[0085] At the same time, such as Figure 3B As shown, the first transistor M1 may include a first gate electrode and a second gate electrode. The first gate electrode may be connected to a first node N1, and the second gate electrode may be connected to a first power line PL1. When the first transistor M1 includes a second gate electrode, the on-current may increase.

[0086] The first light-emitting element LD1, included in the first sub-pixel PX1, can emit green light. For example... Figure 5 As shown, the third light-emitting element LD3, included in the third sub-pixel PX3 that emits blue light, can emit blue light. The circuit structure of the third sub-pixel PX3 is the same as that of the first sub-pixel PX1, and a detailed description related to this is omitted.

[0087] Figure 4A and Figure 4B is a diagram illustrating an embodiment of a second sub-pixel included in a display device of Figure 1 When Figure 4A and Figure 4B are described, the same reference numerals are assigned to configurations performing the same functions as those of Figure 3A and Figure 3B , and repetitive descriptions are omitted. In Figure 4A and Figure 4B , it is assumed that the second sub-pixel PX2 is located on an i-th horizontal line (or i-th pixel row) and is connected to an (j-1)-th data line DLj-1.

[0088] Referring to Figure 4A and Figure 4B , the second sub-pixel PX2 according to an embodiment of the disclosure includes a second light emitting element LD2 and a pixel circuit for controlling an amount of current supplied to the second light emitting element LD2.

[0089] A first electrode (or an anode electrode) of the second light emitting element LD2 can be connected to the fourth node N4, and a second electrode (or a cathode electrode) of the second light emitting element LD2 can be connected to a second power line PL2 provided with a second driving power VSS. The second light emitting element LD2 can generate light of a predetermined brightness in response to an amount of current supplied from the first transistor M1. For example, the second light emitting element LD2 can generate red light.

[0090] The second light emitting element LD2 can be an organic light emitting diode. Further, the second light emitting element LD2 can be an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode. Further, the second light emitting element LD2 can be an element in which an organic material and an inorganic material are combined. In Figure 4A and Figure 4B , the second sub-pixel PX2 includes a single second light emitting element LD2, but in another embodiment, the second sub-pixel PX2 can include a plurality of light emitting elements connected in series with each other, connected in parallel, or connected in series-parallel.

[0091] The pixel circuit can include the first to seventh transistors M1 to M7 and a storage capacitor Cst.

[0092] The seventh transistor M7 (second initialization transistor) is connected to the fourth node N4 (i.e., the first electrode of the second light emitting element LD2) and a third power line PL3 provided with a first initialization power Vint1. Further, a gate electrode of the seventh transistor M7 can be connected to the first scan line SL1i. When a first scan signal is provided from the first scan line SL1i, the seventh transistor M7 can be turned on to provide a voltage of the first initialization power Vint1 to the fourth node N4.

[0093] In comparison with the first sub-pixel PX1, the second sub-pixel PX2 does not include the boost capacitor Cb. That is, the structure of the second sub-pixel PX2 can be identical to that of the first sub-pixel PX1 except for the boost capacitor Cb.

[0094] As shown in Figure 4A , the gate electrode (or first gate electrode) of the first transistor M1 included in the second sub-pixel PX2 can be connected to the first node N1. Further, as shown in Figure 4B , the first transistor M1 can further include a second gate electrode, and the second gate electrode can be electrically connected to the first power line PL1 to which the first driving power VDD is supplied.

[0095] Figure 5 FIG. 1 is a diagram illustrating a sub-pixel according to an embodiment of the present disclosure.

[0096] Referring to Figure 5 , in an embodiment of the present disclosure, the display apparatus 10 can include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3.

[0097] As described with reference to Figures 3A to 4B , each of the first sub-pixel PX1 and the third sub-pixel PX3 includes the boost capacitor Cb, and the second sub-pixel PX2 does not include the boost capacitor Cb. In this case, even if one power line (i.e., the third power line PL3) is used to supply the first initialization power Vint1 to the fourth nodes N4 (i.e., the anode electrodes of the light emitting elements LD1, LD2, and LD3) of the respective sub-pixels PX1 to PX3, the voltages of the fourth nodes N4 included in the first sub-pixel PX1 (and the third sub-pixel PX3) and the fourth nodes N4 included in the second sub-pixel PX2 can be differently set.

[0098] More specifically, the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 can be formed of different materials. Further, the areas occupied by the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 in the respective areas of the sub-pixels PX1 to PX3 can be different.

[0099] In this case, the capacitances of the parasitic capacitors Cel1, Cel2, and Cel3 formed in the respective light emitting elements LD1 to LD3 can be differently set. For example, the capacitance of the second parasitic capacitor Cel2 included in the second sub-pixel PX2 can be greater than the capacitances of the first parasitic capacitor Cel1 and the third parasitic capacitor Cel3 included in the first sub-pixel PX1 and the third sub-pixel PX3.

[0100] The voltage of the first initialization power Vint1 provided to the fourth node N4 of each of the sub-pixels PX1 to PX3 from the third power line PL3 can initialize the voltage stored in the parasitic capacitors Cel1, Cel2, and Cel3. In this case, it is necessary to provide a lower voltage to the fourth node N4 of the second sub-pixel PX2 compared to the first sub-pixel PX1 and the third sub-pixel PX3.

[0101] To this end, a method of providing the first initialization power Vint1 of different voltages to the first sub-pixel PX1 and the third sub-pixel PX3 and the second sub-pixel PX2 can be proposed. For example, the first sub-pixel PX1 and the third sub-pixel PX3 and the second sub-pixel PX2 can be provided with different voltages via different power lines. However, when the power lines are increased, it can be difficult to apply them to a high-resolution (and high pixels per inch (PPI)) display panel. In addition, a check pad or the like for checking whether the increased power lines are abnormal needs to be increased.

[0102] To prevent this, in an embodiment of the disclosure, the voltage of the fourth node N4 of each of the first sub-pixel PX1 and the third sub-pixel PX3 and the fourth node N4 of the second sub-pixel PX2 can be differently set by adding a boost capacitor Cb to the first sub-pixel PX1 and the third sub-pixel PX3. For example, the boost capacitor Cb included in each of the first sub-pixel PX1 and the third sub-pixel PX3 can increase the voltage of the fourth node N4 included in each of the first sub-pixel PX1 and the third sub-pixel PX3. This will be described later with reference to Figure 7 A detailed description related thereto is provided.

[0103] Figure 6A and Figure 6B is a diagram illustrating an embodiment of a signal provided to a sub-pixel in one frame period. For convenience of description, the operation process corresponding to Figure 4A is described with reference to the second sub-pixel PX2 shown in Figure 6A and Figure 6B . Figure 7 is a diagram illustrating the voltage of the fourth node included in each of the sub-pixels corresponding to the first scan signal.

[0104] Referring to Figures 6A to 7 , one frame period can include an emission period EP, a first non-emission period NEP1, and a second non-emission period NEP2. The emission period EP can be adjacent to each of the first non-emission period NEP1 and the second non-emission period NEP2.

[0105] In Figure 6A and Figure 6BIn the embodiment, two non-emission periods NEP1 and NEP2 are included in one frame period, but the disclosure is not limited thereto. For example, the number of non-emission periods NEP1 and NEP2 included in one frame period can be variously set according to the frame frequency and / or setting of the display device 10.

[0106] The first non-emission period NEP1 can refer to a period in which a data signal is written. The second non-emission period NEP2 can refer to a period in which a previous data signal is maintained and the sub-pixels PX1 to PX3 do not emit light. When a plurality of non-emission periods are included in one frame period, motion blur or the like can be reduced, and thus the image quality can be improved.

[0107] The emission control signal EM can be provided a plurality of times during one frame period. That is, the emission control signal EM can have an off period corresponding to the first non-emission period NEP1 and the second non-emission period NEP2. Here, the off period of the emission control signal EM can refer to a period in which the emission control signal EM is provided and thus the fifth transistor M5 and the sixth transistor M6 are turned off. The off period can include a first off period corresponding to the first non-emission period NEP1 and a second off period corresponding to the second non-emission period NEP2.

[0108] The operation procedure is described, first, the fifth transistor M5 and the sixth transistor M6 are turned off by the emission control signal EM provided to the emission control line ELi during the first non-emission period NEP1. When the fifth transistor M5 and the sixth transistor M6 are turned off, the electrical connection between the first power line PL1 and the second light emitting element LD2 is blocked, and thus the second light emitting element LD2 is set to a non-emission state.

[0109] Thereafter, the fourth scan signal GI is provided to the fourth scan line SL4i and the first scan signal GB is provided to the first scan line SL1i. When the fourth scan signal GI is provided to the fourth scan line SL4i, the fourth transistor M4 is turned on, and when the first scan signal GB is provided to the first scan line SL1i, the seventh transistor M7 is turned on.

[0110] When the fourth transistor M4 is turned on, the voltage of the second initialization power Vint2 is provided to the first node N1, and thus the first node N1 is initialized to the voltage of the second initialization power Vint2. When the seventh transistor M7 is turned on, the voltage of the first initialization power Vint1 is provided to the fourth node N4, and thus the anode electrode of the second light emitting element LD2 is initialized to the voltage of the first initialization power Vint1.

[0111] Thereafter, the second scan signal GW is supplied to the second scan line SL2i, and the third scan signal GC is supplied to the third scan line SL3i. When the second scan signal GW is supplied to the second scan line SL2i, the second transistor M2 is turned on. When the third scan signal GC is supplied to the third scan line SL3i, the third transistor M3 is turned on.

[0112] When the second transistor M2 is turned on, the (j-1)th data line DLj-1 and the second node N2 are electrically connected, and thus a data signal is supplied from the (j-1)th data line DLj-1 to the second node N2. When the third transistor M3 is turned on, the first transistor M1 is connected in a diode form. In this case, the data signal supplied to the second node N2 is supplied to the first node N1 via the first transistor M1 connected in a diode form and the turned-on third transistor M3. Thus, a voltage corresponding to the data signal and a threshold voltage of the first transistor M1 can be applied to the first node N1. The storage capacitor Cst stores the voltage applied to the first node N1.

[0113] After the voltage corresponding to the data signal and the threshold voltage of the first transistor M1 are stored in the storage capacitor Cst, the emission control signal EM is stopped being supplied. When the emission control signal EM is stopped being supplied, the fifth transistor M5 and the sixth transistor M6 are turned on. When the fifth transistor M5 and the sixth transistor M6 are turned on, the first power line PL1 can be electrically connected to the anode electrode of the second light emitting element LD2 via the fifth transistor M5, the first transistor M1, and the sixth transistor M6. The first transistor M1 supplies a driving current corresponding to the voltage applied to the first node N1 to the second light emitting element LD2, and the second light emitting element LD2 emits light having a brightness corresponding to the driving current. That is, during an emission period EP after the first non-emission period NEP1, the second light emitting element LD2 can emit light having a brightness corresponding to the driving current.

[0114] In the second non-emission period NEP2, the emission control signal EM is supplied to the emission control line ELi, and thus the fifth transistor M5 and the sixth transistor M6 are cut off. When the fifth transistor M5 and the sixth transistor M6 are cut off, the electrical connection between the first power line PL1 and the second light emitting element LD2 is blocked, and thus the second light emitting element LD2 is set to a non-emission state.

[0115] In the second non-emission period NEP2, the scan signals GW, GC, GI, and GB are not provided. Accordingly, the storage capacitor Cst maintains the voltage stored in the first non-emission period NEP1. During the emission period EP after the second non-emission period NEP2, the emission control signal EM is stopped from being provided, and thus the fifth transistor M5 and the sixth transistor M6 are turned on. Then, during the emission period EP after the second non-emission period NEP2, the second light emitting element LD2 can emit light having a luminance corresponding to the driving current.

[0116] Meanwhile, in the embodiment of the disclosure, the provision waveform of the scan signal for driving the sub-pixels PX1 to PX3 can be variously changed. For example, as shown in FIG. 10, after the second scan signal GW is provided to the second scan line SL2i during the first non-emission period NEP1, the first scan signal GB can be provided to the first scan line SL1i. Further, the first scan signal GB can be provided to the first scan line SL1i during the second non-emission period NEP2. Figure 6B

[0117] When the first scan signal GB is provided to the first scan line SL1i during the second non-emission period NEP2, the seventh transistor M7 can be turned on, and thus the anode electrode of the second light emitting element LD2 can be initialized to the voltage of the first initialization power Vint1. When the voltage of the first initialization power Vint1 is provided to the anode electrode of the second light emitting element LD2 in the second non-emission period NEP2, an increase in the luminance of the second light emitting element LD2 can be prevented.

[0118] Meanwhile, when the first scan signal GB is provided, the first scan line SL1i can be set to a low-level voltage, and when the provision of the first scan signal GB is stopped, the first scan line SL1i can be set to a high-level voltage. When the first scan signal GB is provided to the first scan line SL1i (i.e., a low-level voltage), the voltage of the fourth node N4 of each of the sub-pixels PX1 to PX3 can be set to the voltage of the first initialization power Vint1.

[0119] Further, when the provision of the first scan signal GB is stopped (i.e., a high-level voltage), the fourth node N4 of the second sub-pixel PX2 can maintain the voltage of the first initialization power Vint1, as shown in FIG. 10. On the other hand, when the provision of the first scan signal GB is stopped, the voltage of the fourth node N4 of each of the first sub-pixel PX1 and the third sub-pixel PX3 can be set to a voltage (e.g., Vint1+α) higher than the voltage of the first initialization power Vint1, by the coupling of the boost capacitor Cb included in each of the first sub-pixel PX1 and the third sub-pixel PX3. Figure 7

[0120] ​​That is, in the embodiment of the disclosure, the first to third sub-pixels PX1 to PX3 can receive the same voltage (i.e., Vint1) from the third power line PL3, and the voltage of the fourth node N4 of the first and third sub-pixels PX1 and PX3 can be set to a higher voltage than the voltage of the fourth node N4 of the second sub-pixel PX2 by the boost capacitor Cb.

[0121] Further, the capacitances of the boost capacitors Cb included in the respective first and third sub-pixels PX1 and PX3 can be set to be the same as or different from each other. For example, the capacitance of the boost capacitor Cb included in each of the first and third sub-pixels PX1 and PX3 can be set according to the characteristics of each of the sub-pixels PX1 and PX3.

[0122] Figure 8A FIG. 1 is a schematic cross-sectional view illustrating a first sub-pixel. Figure 8B FIG. 2 is a schematic cross-sectional view of a second sub-pixel. Figure 9 FIG. 3 is a plan view schematically illustrating first to third sub-pixels.

[0123] Since the cross-sectional view of the third sub-pixel PX3 is similar (or identical) to that of the first sub-pixel PX1, a separate description is omitted. In Figure 9 In FIG. 1, only the first electrodes E1a, E1b, and E1c formed of the pixel electrode layer and the first scan lines SL1i and the emission control lines ELi in the arrangement formed of the gate electrode layer are illustrated. In Figure 9 In FIG. 2, the electrodes GEL positioned under the emission control lines ELi at intervals can serve as gate electrodes of the transistors.

[0124] Referring to Figures 8A to 9 , each of the sub-pixels PX1 and PX2 can include an emission area EA and a peripheral area NEA.

[0125] The display device 10 can include a substrate 1, a lower structure including at least one transistor TFT for driving the sub-pixels PX1 and PX2, and a light-emitting structure. A touch sensor, a color filter, a window, etc. can be further included on the light-emitting structure, but they are not separately illustrated in Figure 8A and Figure 8B .

[0126] The substrate 1 can be a rigid substrate or a flexible substrate. The rigid substrate can include a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystal glass substrate. The flexible substrate can include a film substrate including a polymer organic material and a plastic substrate.

[0127] A buffer layer 2 can be provided on the substrate 1. The buffer layer 2 can prevent impurities from diffusing into the transistor TFT. The buffer layer 2 can be provided as a single layer, but can also be provided as a multi-layer of at least two layers.

[0128] A lower structure including a transistor TFT and a plurality of conductive lines can be provided over the buffer layer 2.

[0129] In an embodiment, an active pattern ACT can be provided over the buffer layer 2. The active pattern ACT can be formed of a semiconductor material. For example, the active pattern ACT can include polysilicon, amorphous silicon, an oxide semiconductor, or the like. A gate insulating layer 3 can be provided over the buffer layer 2 over which the active pattern ACT is provided. The gate insulating layer 3 can be an inorganic insulating layer including an inorganic material.

[0130] In the case of the first sub-pixel PX1, a gate electrode GE and a lower electrode LE of the boost capacitor Cb can be provided over the gate insulating layer 3, and a first insulating layer 4 can be provided over the gate insulating layer 3 over which the gate electrode GE and the lower electrode LE are provided. A source electrode SE and a drain electrode DE can be provided over the first insulating layer 4. The source electrode SE and the drain electrode DE can be connected to the active pattern ACT through contact holes formed in the gate insulating layer 3 and the first insulating layer 4.

[0131] In the case of the second sub-pixel PX2, a gate electrode GE can be provided over the gate insulating layer 3, and a first insulating layer 4 can be provided over the gate insulating layer 3 over which the gate electrode GE is provided. A source electrode SE and a drain electrode DE can be provided over the first insulating layer 4. The source electrode SE and the drain electrode DE can be connected to the active pattern ACT through contact holes formed in the gate insulating layer 3 and the first insulating layer 4. That is, a lower electrode LE of the boost capacitor Cb is not provided in the second sub-pixel PX2.

[0132] The gate electrode GE and the lower electrode LE can be formed of a conductive material forming a gate electrode layer. The gate electrode layer can be formed as a single layer or a plurality of layers formed of molybdenum (Mo), copper (Cu), chromium (Cr), gold (Au), silver (Ag), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), and oxides or alloys thereof. For example, the gate electrode layer can be formed of a plurality of layers in which titanium, copper, and / or indium tin oxide are sequentially or repeatedly stacked, but is not limited thereto. The gate electrode GE can overlap with one region of the active pattern ACT. The region of the active pattern ACT overlapping with the gate electrode GE can be a channel region.

[0133] A second insulating layer 5 can be provided over the first insulating layer 4 over which the source electrode SE and the drain electrode DE are provided. The second insulating layer 5 can be a planarization layer.

[0134] The light emitting elements LD1 and LD2 (or light emitting structures) can include first electrodes E1a and E1b, light emitting layers ELa and ELb, and a second electrode E2. Further, the third light emitting element LD3 can also include a first electrode E1c, a light emitting layer, and the second electrode E2.

[0135] The upper electrodes UE of the first electrodes E1a and E1b of the light emitting elements LD1 and LD2 and the boost capacitor Cb can be disposed on the second insulating layer 5. Here, the upper electrodes UE of the boost capacitor Cb are disposed in the first sub-pixel PX1 (and the third sub-pixel PX3), and not disposed in the second sub-pixel PX2.

[0136] In an embodiment, the first electrodes E1a, E1b, and E1c can be disposed as anode electrodes of the light emitting elements LD1, LD2, and LD3. The first electrodes E1a, E1b, and E1c can be formed to pass through the second insulating layer 5 to be connected to the drain electrodes DE of the transistors TFT. The first electrodes E1a, E1b, and E1c can be patterned for each of the sub-pixels PX1, PX2, and PX3. The first electrodes E1a, E1b, and E1c can be disposed in a portion of the peripheral region NEA and the emission region EA on the second insulating layer 5.

[0137] The first electrodes E1a, E1b, and E1c and the upper electrodes UE can be formed of a conductive material forming a pixel electrode layer. The pixel electrode layer can be formed of a metal layer of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), and (Cr), an alloy thereof, or the like, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like, but is not limited thereto.

[0138] The upper electrodes UE overlap the lower electrodes LE to form the boost capacitor Cb. More specifically, as shown in FIG. 1B, the first scan line SL1i can be formed of a gate electrode layer. The first scan line SL1i can be disposed to extend in the first direction DR1. The first protrusion Pj1 and the second protrusion Pj2 protruding in the second direction DR2 can be formed from the first scan line SL1i. Here, the first protrusion Pj1 and the second protrusion Pj2 can be positioned adjacently, and each of the first protrusion Pj1 and the second protrusion Pj2 can be a lower electrode LE of the boost capacitor Cb. Figure 9 For example, the first protrusion Pj1 can be a lower electrode LE of the boost capacitor Cb included in the first sub-pixel PX1, and the second protrusion Pj2 can be a lower electrode LE of the boost capacitor Cb included in the third sub-pixel PX3.

[0139]

[0140] ​The first sub-pixel PX1 can include a first branch Br1 branched from the first electrode E1a (or branched from a pixel electrode layer of the first sub-pixel PX1). The first branch Br1 can at least partially overlap the first protrusion Pj1. The first branch Br1 can be an upper electrode UE of the boost capacitor Cb. The first branch Br1 can extend in the second direction DR2. Alternatively, the first branch Br1 can extend to at least partially overlap the first protrusion Pj1.

[0141] The third sub-pixel PX3 can include a second branch Br2 branched from the first electrode E1c (or branched from a pixel electrode layer of the third sub-pixel PX3). The second branch Br2 can at least partially overlap the second protrusion Pj2. The second branch Br2 can be an upper electrode UE of the boost capacitor Cb. The second branch Br2 can extend in the first direction DR1. Alternatively, the second branch Br2 can extend to at least partially overlap the second protrusion Pj2.

[0142] The pixel definition layer PDL can be disposed in the peripheral area NEA on the second insulating layer 5 and can expose a portion of the first electrodes E1a, E1b, and E1c. The pixel definition layer PDL can be formed of an organic material and / or an inorganic material. That is, the emission area EA can be defined by the pixel definition layer PDL.

[0143] The light emitting layers ELa and ELb can be disposed on the first electrodes E1a and E1b exposed by the pixel definition layer PDL. The light emitting layers ELa and ELb can be disposed to extend along sidewalls of the pixel definition layer PDL. In an embodiment, the light emitting layer ELa included in the first sub-pixel PX1 can be formed using at least one light emitting material capable of emitting green light. In an embodiment, the light emitting layer ELb included in the second sub-pixel PX2 can be formed using at least one light emitting material capable of emitting red light. In an embodiment, a light emitting layer (not shown) included in the third sub-pixel PX3 can be formed using at least one light emitting material capable of emitting blue light.

[0144] The second electrode E2 is commonly disposed on the pixel definition layer PDL and the light emitting layers ELa and ELb. In an embodiment, the second electrode E2 can be disposed as a cathode electrode of the light emitting elements LD1, LD2, and LD3. The second electrode E2 can be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These can be used alone or in combination with each other.

[0145] A sealing layer TFE covering the second electrode E2 can be formed on the second electrode E2. The sealing layer TFE can include a plurality of insulating layers covering the light emitting elements LD1, LD2, and LD3. For example, the sealing layer TFE can have a structure in which inorganic layers and organic layers are alternately stacked. Also, according to one case, the sealing layer TFE can be a sealing substrate disposed on the light emitting elements LD1, LD2, and LD3 and attached to the substrate 1 by a sealing agent.

[0146] Although the above has been described with reference to the embodiments of the present disclosure, those skilled in the art will appreciate that various corrections and modifications of the present disclosure can be made within the scope without departing from the spirit and scope of the present disclosure described in the claims.

Claims

1. A display device, characterized by The display apparatus includes: a first sub-pixel including a first initialization transistor providing a voltage of an initialization power to an anode electrode of a first light emitting element when a first scan signal is provided to a first scan line, and a first boost capacitor connected between the first scan line and the anode electrode of the first light emitting element; and a second sub-pixel including a second initialization transistor providing the voltage of the initialization power to an anode electrode of a second light emitting element when the first scan signal is provided to the first scan line.

2. The display device of claim 1, wherein, The second sub-pixel does not include a boost capacitor connected between the first scan line and the anode electrode of the second light emitting element.

3. The display device of claim 1, wherein, The second light emitting element emits red light, and the first light emitting element emits light of a color different from the red light.

4. The display device of claim 1, wherein, The display apparatus further includes: a third sub-pixel including a third initialization transistor providing the voltage of the initialization power to an anode electrode of a third light emitting element when the first scan signal is provided to the first scan line, and a second boost capacitor connected between the first scan line and the anode electrode of the third light emitting element.

5. A display device, characterized by The display apparatus includes: a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel including a first pixel electrode layer, the second sub-pixel including a second pixel electrode layer, and the third sub-pixel including a third pixel electrode layer; and a first scan line extending in a first direction and electrically connected to the first sub-pixel, the second sub-pixel, and the third sub-pixel, wherein the first pixel electrode layer and the third pixel electrode layer overlap at least a portion of the first scan line, and the second pixel electrode layer does not overlap the first scan line.

6. The display device of claim 5, wherein, The first scan line includes a first protruding portion protruding in a second direction different from the first direction and at least partially overlapping the first pixel electrode layer, and a second protruding portion protruding in the second direction and at least partially overlapping the third pixel electrode layer.

7. The display device of claim 6, wherein, The display apparatus further includes: a first branch branching from the first pixel electrode layer and at least partially overlapping the first protruding portion.

8. The display device of claim 6, wherein, The display apparatus further includes: a second branch branching from the third pixel electrode layer and at least partially overlapping the second protruding portion.

9. The display device of claim 5, wherein, The first sub-pixel is a green sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a blue sub-pixel.

10. The display device of claim 5, wherein, Pixel electrode layers including the first pixel electrode layer, the second pixel electrode layer, and the third pixel electrode layer are located in different layers from the first scan line, and wherein the pixel electrode layers are located above the first scan line in a cross-sectional view.

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