Wireless local area network module

Abstract

The utility model relates to a wireless local area network module, which belongs to the technical field of communication equipment and comprises a shell and a printed circuit board (PCB) card arranged in the shell, and the PCB card is provided with a ZigBee module, a signal large circuit, a band-pass filter, an analog-to-digital conversion circuit, a signal processing module and a power supply module for supplying power to the whole module. According to the utility model, the designed signal amplification circuit comprises the primary signal amplification sub-circuit, the signal feedback sub-circuit and the secondary signal amplification sub-circuit, so that the signal intensity is effectively enhanced, the attenuation of the signal in the transmission process is reduced, and the signal amplification circuit and the filter act synergistically, so that the signal amplification efficiency is improved. The module can keep stable signal quality in a complex electromagnetic environment, and data transmission errors and packet loss are reduced; and the analog-to-digital conversion circuit adopts a high-precision analog-to-digital conversion chip, so that the accuracy and integrity of the signal in the conversion process are ensured, and the reliability of data transmission is further improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of communication equipment, specifically relates to a wireless local area network module. BACKGROUND

[0002] With the rapid development of wireless communication technology, wireless local area network (WLAN) modules have been widely used in smart home, industrial automation, medical equipment and other fields. These modules not only need to have efficient data transmission capability, but also need to maintain stable signal quality in complex environments. Traditional wireless local area network modules often face problems such as signal interference, limited transmission distance, and high power consumption, especially in complex electromagnetic environments.

[0003] In order to improve the performance of wireless local area network modules, researchers are constantly exploring new technologies and methods. Among them, ZigBee technology has become an important choice for building wireless local area network modules due to its low power consumption, low cost, self-organizing network and other advantages. However, ZigBee signals are prone to be interfered by various factors during transmission, such as signals from other wireless devices and environmental noise, which can reduce signal quality and affect the stability and reliability of data transmission. SUMMARY

[0004] The utility model aims at the defects in the prior art, and provides a wireless local area network module to solve the problems in the prior art.

[0005] To achieve the above-mentioned purpose, the utility model provides the following technical scheme:

[0006] A wireless local area network module, comprising a shell and a PCB card installed in the shell, a ZigBee module, a signal amplifier circuit, a band-pass filter, an analog-to-digital conversion circuit, a signal processing module and a power module for powering the entire module are provided on the PCB card; the ZigBee module is connected to the input end of the signal processing module through the signal amplifier circuit, the band-pass filter and the analog-to-digital conversion circuit in sequence, and the output end of the signal processing module is connected to an external device through the ZigBee module.

[0007] Further improvement of the technical scheme is that the ZigBee module uses a ZigBee module with model SUN-JN5169.

[0008] Further improvement of the technical scheme is that the signal amplifier circuit includes a primary signal amplification sub-circuit, a signal feedback sub-circuit and a secondary signal amplification sub-circuit, the input end of the primary signal amplification sub-circuit is connected to an external device through the ZigBee module, and the output end of the primary signal amplification sub-circuit is connected to the input end of the band-pass filter through the signal feedback sub-circuit and the secondary signal amplification sub-circuit in sequence.

[0009] Further improvements of the technical scheme are that the primary signal amplification sub-circuit comprises a junction field effect transistor Q1, a junction field effect transistor Q2, a junction field effect transistor Q3, a junction field effect transistor Q4, a resistor R1, an adjustable resistor R2, a junction field effect transistor Q5, a resistor R3, an adjustable resistor R4, a junction field effect transistor Q6, a capacitor C1, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a resistor R6 and a resistor R7.

[0010] The gate of the junction field effect transistor Q1 is connected to the first output end of the ZigBee module, the drain of the junction field effect transistor Q1 is connected to the source of the junction field effect transistor Q2, the gate of the junction field effect transistor Q2 is connected to the source of the junction field effect transistor Q1, the drain of the junction field effect transistor Q2 is connected to the first end of the resistor R1, the first end of the adjustable resistor R2 and the gate of the junction field effect transistor Q3, the second end of the resistor R1 is connected to the first end of the capacitor C1 and the first input end of the signal feedback sub-circuit, the second end of the capacitor C1 is grounded, the second end of the adjustable resistor R2 is connected to the source of the junction field effect transistor Q3, the drain of the junction field effect transistor Q3 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the positive pole of the battery in the power module, and the negative pole of the battery is grounded.

[0011] The gate of the junction field effect transistor Q4 is connected to the second output end of the ZigBee module, the drain of the junction field effect transistor Q4 is connected to the source of the junction field effect transistor Q5, the gate of the junction field effect transistor Q5 is connected to the source of the junction field effect transistor Q4, the drain of the junction field effect transistor Q5 is connected to the first end of the resistor R4, the first end of the adjustable resistor R5 and the gate of the junction field effect transistor Q6, the second end of the resistor R4 is connected to the first end of the capacitor C2 and the second input end of the signal feedback sub-circuit, the second end of the capacitor C2 is grounded, the second end of the adjustable resistor R5 is connected to the source of the junction field effect transistor Q6, and the drain of the junction field effect transistor Q6 is connected to the first end of the resistor R3.

[0012] Further improvements of the technical scheme are that the signal feedback sub-circuit comprises an amplifier U1, an amplifier U2, a resistor R6, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R7, a resistor R8, a capacitor C6, a resistor R9, a resistor R10, a resistor R11 and a resistor R12.

[0013] The non-inverting input end of the amplifier U1 is connected to the second end of the resistor R1, the inverting input end of the amplifier U1 is grounded through the parallel connection of the resistor R6, the capacitor C3 and the capacitor C4, the output end of the amplifier U1 is connected to the first input end of the secondary signal amplification sub-circuit, and the output end of the amplifier U1 is connected to the non-inverting input end of the amplifier U1 through the series connection of the capacitor C5 and the resistor R7.

[0014] The noninverting input terminal of the amplifier U2 is connected to the second end of the resistor R4, the inverting input terminal of the amplifier U2 is connected to the positive pole of the battery in the power module through the resistor R8, the output terminal of the amplifier U2 is connected to the second input terminal of the secondary signal amplification subcircuit, the output terminal of the amplifier U2 is connected to the noninverting input terminal of the amplifier U2 through the capacitor C6 and the resistor R9 connected in series, the output terminal of the amplifier U1 is connected to the first end of the resistor R10, the second end of the resistor R10 is connected to the source electrode of the junction field effect transistor Q1, the output terminal of the amplifier U2 is connected to the first end of the resistor R11, the second end of the resistor R11 is connected to the source electrode of the junction field effect transistor Q4, and the resistor R12 is connected between the second end of the resistor R10 and the second end of the resistor R11.

[0015] Further improvement of the technical solution is that the secondary signal amplification subcircuit comprises the amplifier U3, the resistor R13, the resistor R14, the capacitor C7, the resistor R15, the resistor R16, the capacitor C8, the amplifier U4, the resistor R17 and the resistor R18.

[0016] The noninverting input terminal of the amplifier U3 is connected to the output terminal of the amplifier U1 through the resistor R13, the noninverting input terminal of the amplifier U3 is grounded through the resistor R14 and the capacitor C7 connected in parallel, the inverting input terminal of the amplifier U3 is connected to the output terminal of the amplifier U2 through the resistor R15, the output terminal of the amplifier U3 is connected to the inverting input terminal of the amplifier U3 through the resistor R16 and the capacitor C8 connected in parallel, the output terminal of the amplifier U3 is connected to the noninverting input terminal of the amplifier U4, the inverting input terminal of the amplifier U4 is grounded through the resistor R17, the output terminal of the amplifier U4 is connected to the inverting input terminal of the amplifier U4 through the resistor R18, and the output terminal of the amplifier U4 is connected to the input terminal of the band-pass filter.

[0017] Further improvement of the technical solution is that the band-pass filter adopts a band-pass filter with the model ACPF-W060.

[0018] Further improvement of the technical solution is that the analog-digital conversion circuit comprises the analog-digital conversion chip U5, the resistor R19, the resistor R20, the capacitor C9, the capacitor C10, the capacitor C11, the capacitor C11, the capacitor C11, the capacitor C11, the resistor R21, the capacitor C11, the resistor R22, the resistor R23 and the capacitor C16.

[0019] The first pin of the analog-digital conversion chip U5 is connected to the output end of the band-pass filter through the resistor R19, the second pin of the analog-digital conversion chip U5 is connected to the first end of the resistor R20, the second end of the resistor R20 and the third pin of the analog-digital conversion chip U5 are both connected to the first end of the capacitor C9 and the first end of the capacitor C10, the second end of the capacitor C9 and the second end of the capacitor C10 are both grounded, the fourth pin of the analog-digital conversion chip U5 is connected to the first end of the capacitor C11, the fifth pin of the analog-digital conversion chip U5 is connected to the first end of the capacitor C12, the first end of the capacitor C13 and the first end of the capacitor C14, the second end of the capacitor C12 and the second end of the capacitor C13 are both connected to the first end of the capacitor C11, the second end of the capacitor C11 and the second end of the capacitor C14 are both grounded, the sixth pin of the analog-digital conversion chip U5 is grounded through the resistor R21, the seventh pin of the analog-digital conversion chip U5 is connected to the 3.3V power supply in the power module and is grounded through the capacitor C15, the eighth pin of the analog-digital conversion chip U5 is connected to the signal processing module, the ninth pin of the analog-digital conversion chip U5 is connected to the 3.3V power supply in the power module through the resistor R22, the ninth pin of the analog-digital conversion chip U5 is grounded through the resistor R23, and the ninth pin of the analog-digital conversion chip U5 is connected to the signal processing module through the capacitor C16.

[0020] Further improvement of the technical solution is that the signal processing module comprises a single-chip microcomputer with the model of STM32F103C8T6.

[0021] The signal amplification circuit and the filter cooperate to enable the module to maintain stable signal quality in a complex electromagnetic environment, reduce data transmission errors and packet loss phenomena, the analog-digital conversion circuit adopts a high-precision analog-digital conversion chip, and the accuracy and integrity of signals in the conversion process are ensured, and the reliability of data transmission is further improved.

[0022] In addition, the utility model discloses a design principle is reliable, simple structure has very extensive application prospect.

[0023] Therefore, compared with the prior art, the utility model has outstanding substantial characteristics and obvious progress, and the beneficial effects of implementation are also obvious. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a relationship schematic view of the wireless local area network module.

[0025] Figure 2The schematic diagram of the primary signal amplification sub-circuit and the signal feedback sub-circuit.

[0026] Figure 3 The schematic diagram of the secondary signal amplification sub-circuit.

[0027] Figure 4 The schematic diagram of the analog-digital conversion circuit.

[0028] 110 is a shell, 120 is a PCB card, 130 is a ZigBee module, 140 is a signal amplification circuit, 141 is a primary signal amplification sub-circuit, 142 is a signal feedback sub-circuit, 143 is a secondary signal amplification sub-circuit, 150 is a band-pass filter, 160 is an analog-digital conversion circuit, 170 is a signal processing module, and 180 is a power module. DETAILED DESCRIPTION

[0029] In order for those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0031] As shown in Figure 1 The present application provides a wireless local area network module, which comprises a shell and a PCB card installed in the shell. The PCB card is provided with a ZigBee module, a signal amplification circuit, a band-pass filter, an analog-digital conversion circuit, a signal processing module and a power module for supplying power to the entire module. The ZigBee module is connected to the input end of the signal processing module through the signal amplification circuit, the band-pass filter and the analog-digital conversion circuit in sequence. The output end of the signal processing module is connected to an external device through the ZigBee module.

[0032] Specifically, the ZigBee module is of the type SUN-JN5169. The band-pass filter is of the type ACPF-W060. The signal processing module comprises a single-chip microcomputer of the type STM32F103C8T6.

[0033] The signal amplification circuit includes a primary signal amplification sub-circuit, a signal feedback sub-circuit, and a secondary signal amplification sub-circuit. The input terminal of the primary signal amplification sub-circuit is connected to an external device via a ZigBee module, and the output terminal of the primary signal amplification sub-circuit is connected to the input terminal of a bandpass filter via the signal feedback sub-circuit and the secondary signal amplification sub-circuit in sequence.

[0034] like Figure 2 As shown, the primary signal amplification sub-circuit includes junction field-effect transistors (JFETs) Q1, Q2, Q3, and Q4, resistors R1, R2, Q5, R3, R4, Q6, capacitors C1, R5, C2, C3, and C4, and resistors R6 and R7. The gate of JFET Q1 is connected to the first output terminal of the ZigBee module. The drain of JFET Q1 is connected to the source of JFET Q2. The gate of JFET Q2 is connected to the source of JFET Q1. The drain of JFET Q2 is connected to the first terminal of resistor R1, the first terminal of adjustable resistor R2, and the gate of JFET Q3. The second terminal of resistor R1 is connected to the first terminal of capacitor C1 and the first input terminal of the signal feedback sub-circuit. The second terminal of capacitor C1 is connected to... The second terminal of the adjustable resistor R2 is connected to the source of the junction field-effect transistor Q3, the drain of the junction field-effect transistor Q3 is connected to the first terminal of the resistor R3, the second terminal of the resistor R3 is connected to the positive terminal of the battery in the power module, and the negative terminal of the battery is grounded; the gate of the junction field-effect transistor Q4 is connected to the second output terminal of the ZigBee module, the drain of the junction field-effect transistor Q4 is connected to the source of the junction field-effect transistor Q5, the gate of the junction field-effect transistor Q5 is connected to the source of the junction field-effect transistor Q4, the drain of the junction field-effect transistor Q5 is connected to the first terminal of the resistor R4, the first terminal of the adjustable resistor R5, and the gate of the junction field-effect transistor Q6, the second terminal of the resistor R4 is connected to the first terminal of the capacitor C2 and the second input terminal of the signal feedback sub-circuit, the second terminal of the capacitor C2 is grounded, the second terminal of the adjustable resistor R5 is connected to the source of the junction field-effect transistor Q6, and the drain of the junction field-effect transistor Q6 is connected to the first terminal of the resistor R3.

[0035] Further, the signal feedback sub-circuit comprises an amplifier U1, an amplifier U2, a resistor R6, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R7, a resistor R8, a capacitor C6, a resistor R9, a resistor R10, a resistor R11 and a resistor R12; the non-inverting input terminal of the amplifier U1 is connected to the second terminal of the resistor R1, the inverting input terminal of the amplifier U1 is grounded through the resistor R6, the capacitor C3 and the capacitor C4 in parallel, the output terminal of the amplifier U1 is connected to the first input terminal of the secondary signal amplification sub-circuit, and the output terminal of the amplifier U1 is connected to the non-inverting input terminal of the amplifier U1 through the capacitor C5 and the resistor R7 in series; the non-inverting input terminal of the amplifier U2 is connected to the second terminal of the resistor R4, the inverting input terminal of the amplifier U2 is connected to the positive electrode of the battery in the power module through the resistor R8, the output terminal of the amplifier U2 is connected to the second input terminal of the secondary signal amplification sub-circuit, the output terminal of the amplifier U2 is connected to the non-inverting input terminal of the amplifier U2 through the capacitor C6 and the resistor R9 in series, the output terminal of the amplifier U1 is connected to the first terminal of the resistor R10, the second terminal of the resistor R10 is connected to the source electrode of the junction field effect transistor Q1, the output terminal of the amplifier U2 is connected to the first terminal of the resistor R11, the second terminal of the resistor R11 is connected to the source electrode of the junction field effect transistor Q4, and the resistor R12 is connected between the second terminal of the resistor R10 and the second terminal of the resistor R11.

[0036] As shown in Figure 3 The secondary signal amplification sub-circuit comprises an amplifier U3, a resistor R13, a resistor R14, a capacitor C7, a resistor R15, a resistor R16, a capacitor C8, an amplifier U4, a resistor R17 and a resistor R18; the non-inverting input terminal of the amplifier U3 is connected to the output terminal of the amplifier U1 through the resistor R13, the non-inverting input terminal of the amplifier U3 is grounded through the resistor R14 and the capacitor C7 in parallel, the inverting input terminal of the amplifier U3 is connected to the output terminal of the amplifier U2 through the resistor R15, and the output terminal of the amplifier U3 is connected to the inverting input terminal of the amplifier U3 through the resistor R16 and the capacitor C8 in parallel; the output terminal of the amplifier U3 is connected to the non-inverting input terminal of the amplifier U4, the inverting input terminal of the amplifier U4 is grounded through the resistor R17, the output terminal of the amplifier U4 is connected to the inverting input terminal of the amplifier U4 through the resistor R18, and the output terminal of the amplifier U4 is connected to the input terminal of the band-pass filter.

[0037] Specifically, a pair of mutually matched junction field effect transistors Q1 and Q4 are connected in a symmetrical structure to form a differential input (the junction field effect transistors Q1 and Q4 can be of type LSK389), and the source stage of the junction field effect transistor Q1 is connected in cascade with the gate of a junction field effect transistor Q2 (which can be of type U440), so as to reduce the influence of the channel modulation effect of the junction field effect transistor Q1; by adjusting the resistance values of the adjustable resistors R2 and R5, the common mode signal of the stage can be adjusted, so that the outputs of the amplifiers U1 and U2 are equal when the two input terminals are grounded, and the same signals output by the amplifiers U1 and U2 can be eliminated when the same signals are differentially amplified by the amplifier U3.

[0038] As shown in Figure 4 The analog-to-digital conversion circuit includes an analog-to-digital conversion chip U5, a resistor R19, a resistor R20, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C11, a capacitor C11, a capacitor C11, a resistor R21, a capacitor C11, a resistor R22, a resistor R23 and a capacitor C16; a first pin of the analog-to-digital conversion chip U5 is connected to the output terminal of the band-pass filter through the resistor R19, a second pin of the analog-to-digital conversion chip U5 is connected to a first terminal of the resistor R20, a second terminal of the resistor R20 and a third pin of the analog-to-digital conversion chip U5 are both connected to a first terminal of the capacitor C9 and a first terminal of the capacitor C10, a second terminal of the capacitor C9 and a second terminal of the capacitor C10 are both grounded, a fourth pin of the analog-to-digital conversion chip U5 is connected to a first terminal of the capacitor C11, a fifth pin of the analog-to-digital conversion chip U5 is connected to a first terminal of the capacitor C12, a first terminal of the capacitor C13 and a first terminal of the capacitor C14, a second terminal of the capacitor C12 and a second terminal of the capacitor C13 are both connected to a first terminal of the capacitor C11, a second terminal of the capacitor C11 and a second terminal of the capacitor C14 are both grounded, a sixth pin of the analog-to-digital conversion chip U5 is grounded through the resistor R21, a seventh pin of the analog-to-digital conversion chip U5 is connected to a 3.3V power supply in the power supply module and grounded through the capacitor C15, an eighth pin of the analog-to-digital conversion chip U5 is connected to the signal processing module, a ninth pin of the analog-to-digital conversion chip U5 is connected to the 3.3V power supply in the power supply module through the resistor R22, a ninth pin of the analog-to-digital conversion chip U5 is grounded through the resistor R23, and a ninth pin of the analog-to-digital conversion chip U5 is connected to the signal processing module through the capacitor C16. The analog-to-digital conversion chip U5 is of type AD9226.

[0039] The above disclosed is only the preferred embodiment of the present application, but the present application is not limited to this, any person skilled in the art can think of non-creative changes, and a number of improvements and refinements made without departing from the principles of the present application, should fall within the scope of protection of the present application.

Claims

1. A wireless local area network module, characterized by The application relates to a ZigBee module, which comprises a shell and a PCB board installed in the shell, wherein the PCB board is provided with a ZigBee module, a signal amplification circuit, a band-pass filter, an analog-digital conversion circuit, a signal processing module and a power supply module for supplying power to the whole module; the ZigBee module is connected to the input end of the signal processing module through the signal amplification circuit, the band-pass filter and the analog-digital conversion circuit in sequence, and the output end of the signal processing module is connected to external equipment through the ZigBee module.

2. The wireless LAN module of claim 1, wherein, The ZigBee module adopts a ZigBee module with the model SUN-JN5169.

3. The wireless LAN module of claim 1, wherein, The signal amplification circuit comprises a primary signal amplification sub-circuit, a signal feedback sub-circuit and a secondary signal amplification sub-circuit, the input end of the primary signal amplification sub-circuit is connected to external equipment through the ZigBee module, and the output end of the primary signal amplification sub-circuit is connected to the input end of the band-pass filter through the signal feedback sub-circuit and the secondary signal amplification sub-circuit in sequence.

4. The wireless LAN module of claim 3, wherein, The primary signal amplification sub-circuit comprises a junction field effect transistor Q1, a junction field effect transistor Q2, a junction field effect transistor Q3, a junction field effect transistor Q4, a resistor R1, an adjustable resistor R2, a junction field effect transistor Q5, a resistor R3, an adjustable resistor R4, a junction field effect transistor Q6, a capacitor C1, a resistor R5, a capacitor C2, a capacitor C3, a capacitor C4, a resistor R6 and a resistor R7. The gate of the junction field effect transistor Q1 is connected to the first output end of the ZigBee module, the drain of the junction field effect transistor Q1 is connected to the source of the junction field effect transistor Q2, the gate of the junction field effect transistor Q2 is connected to the source of the junction field effect transistor Q1, the drain of the junction field effect transistor Q2 is connected to the first end of the resistor R1, the first end of the adjustable resistor R2 and the gate of the junction field effect transistor Q3, the second end of the resistor R1 is connected to the first end of the capacitor C1 and the first input end of the signal feedback sub-circuit, the second end of the capacitor C1 is grounded, the second end of the adjustable resistor R2 is connected to the source of the junction field effect transistor Q3, the drain of the junction field effect transistor Q3 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the positive pole of a battery in the power supply module, and the negative pole of the battery is grounded. The gate of the junction field effect transistor Q4 is connected to the second output end of the ZigBee module, the drain of the junction field effect transistor Q4 is connected to the source of the junction field effect transistor Q5, the gate of the junction field effect transistor Q5 is connected to the source of the junction field effect transistor Q4, the drain of the junction field effect transistor Q5 is connected to the first end of the resistor R4, the first end of the adjustable resistor R5 and the gate of the junction field effect transistor Q6, the second end of the resistor R4 is connected to the first end of the capacitor C2 and the second input end of the signal feedback sub-circuit, the second end of the capacitor C2 is grounded, the second end of the adjustable resistor R5 is connected to the source of the junction field effect transistor Q6, and the drain of the junction field effect transistor Q6 is connected to the first end of the resistor R3.

5. The wireless LAN module of claim 4, wherein, The signal feedback sub-circuit comprises an amplifier U1, an amplifier U2, a resistor R6, a capacitor C3, a capacitor C4, a capacitor C5, a resistor R7, a resistor R8, a capacitor C6, a resistor R9, a resistor R10, a resistor R11 and a resistor R12; The non-inverting input end of the amplifier U1 is connected to the second end of the resistor R1, the inverting input end of the amplifier U1 is grounded through the parallel connection of the resistor R6, the capacitor C3 and the capacitor C4, the output end of the amplifier U1 is connected to the first input end of the secondary signal amplification sub-circuit, and the output end of the amplifier U1 is connected to the non-inverting input end of the amplifier U1 through the series connection of the capacitor C5 and the resistor R7. The non-inverting input end of the amplifier U2 is connected to the second end of the resistor R4, the inverting input end of the amplifier U2 is connected to the positive electrode of the battery in the power module through the resistor R8, the output end of the amplifier U2 is connected to the second input end of the secondary signal amplification sub-circuit, the output end of the amplifier U2 is connected to the non-inverting input end of the amplifier U2 through the series connection of the capacitor C6 and the resistor R9, the output end of the amplifier U1 is connected to the first end of the resistor R10, the second end of the resistor R10 is connected to the source electrode of the junction field effect transistor Q1, the output end of the amplifier U2 is connected to the first end of the resistor R11, the second end of the resistor R11 is connected to the source electrode of the junction field effect transistor Q4, and the resistor R12 is connected between the second end of the resistor R10 and the second end of the resistor R11.

6. The wireless LAN module of claim 5, wherein, The secondary signal amplification sub-circuit comprises an amplifier U3, a resistor R13, a resistor R14, a capacitor C7, a resistor R15, a resistor R16, a capacitor C8, an amplifier U4, a resistor R17 and a resistor R18; The non-inverting input end of the amplifier U3 is connected to the output end of the amplifier U1 through the resistor R13, the non-inverting input end of the amplifier U3 is grounded through the parallel connection of the resistor R14 and the capacitor C7, the inverting input end of the amplifier U3 is connected to the output end of the amplifier U2 through the resistor R15, the output end of the amplifier U3 is connected to the inverting input end of the amplifier U3 through the parallel connection of the resistor R16 and the capacitor C8, the output end of the amplifier U3 is connected to the non-inverting input end of the amplifier U4, the inverting input end of the amplifier U4 is grounded through the resistor R17, the output end of the amplifier U4 is connected to the inverting input end of the amplifier U4 through the resistor R18, and the output end of the amplifier U4 is connected to the input end of the band-pass filter.

7. The wireless LAN module of claim 1, wherein, The band-pass filter adopts a band-pass filter with the model ACPF-W060.

8. The wireless LAN module of claim 1, wherein, The analog-to-digital conversion circuit comprises an analog-to-digital conversion chip U5, a resistor R19, a resistor R20, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C11, a capacitor C11, a capacitor C11, a resistor R21, a capacitor C11, a resistor R22, a resistor R23 and a capacitor C16; The first pin of the analog-digital conversion chip U5 is connected to the output end of the band-pass filter through the resistor R19, the second pin of the analog-digital conversion chip U5 is connected to the first end of the resistor R20, the second end of the resistor R20 and the third pin of the analog-digital conversion chip U5 are both connected to the first end of the capacitor C9 and the first end of the capacitor C10, the second end of the capacitor C9 and the second end of the capacitor C10 are both grounded, the fourth pin of the analog-digital conversion chip U5 is connected to the first end of the capacitor C11, the fifth pin of the analog-digital conversion chip U5 is connected to the first end of the capacitor C12, the first end of the capacitor C13 and the first end of the capacitor C14, the second end of the capacitor C12 and the second end of the capacitor C13 are both connected to the first end of the capacitor C11, the second end of the capacitor C11 and the second end of the capacitor C14 are both grounded, the sixth pin of the analog-digital conversion chip U5 is grounded through the resistor R21, the seventh pin of the analog-digital conversion chip U5 is connected to the 3.3V power supply in the power module and is grounded through the capacitor C15, the eighth pin of the analog-digital conversion chip U5 is connected to the signal processing module, the ninth pin of the analog-digital conversion chip U5 is connected to the 3.3V power supply in the power module through the resistor R22, the ninth pin of the analog-digital conversion chip U5 is grounded through the resistor R23, and the ninth pin of the analog-digital conversion chip U5 is connected to the signal processing module through the capacitor C16.

9. The wireless LAN module of claim 1, wherein, The signal processing module comprises a single-chip microcomputer with the model of STM32F103C8T6.

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