Display substrate and display device

Abstract

The display substrate comprises pixel driving circuits, a plurality of data signal lines and a plurality of data patch cords, the pixel driving circuits, the data signal lines and the data patch cords are arranged in an array mode, at least one pixel driving circuit is electrically connected with at least one data signal line, and at least part of at least one data signal line extends in the first direction; the at least one data patch cord is electrically connected with the at least one data signal line; the at least one data patch cord comprises a first patch cord at least partially extending along a first direction; the distance between the orthographic projection of at least part of the first patch cord of the at least one data patch cord on the substrate and the orthographic projection of at least part of the active pattern of the at least one transistor extending in the first direction on the substrate is smaller than a first threshold distance. Or the distance between the film layer where the first patch cord of the at least one data patch cord is located and the film layer where the active pattern of the at least one transistor is located is greater than a second threshold distance.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, the flexible display with OLED or QLED as the light-emitting device and controlled by Thin Film Transistor (TFT) has become the mainstream product in the current display field. CONTENT OF THE UTILITY MODEL

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a display substrate and a display device.

[0005] In a first aspect, the present disclosure provides a display substrate, comprising: a substrate, and an array of pixel driving circuits, a plurality of data signal lines and a plurality of data transfer lines disposed on the substrate, at least one pixel driving circuit is electrically connected with at least one data signal line, and the at least one data signal line extends at least partially along a first direction;

[0006] The at least one data transfer line is electrically connected with the at least one data signal line;

[0007] The at least one data transfer line comprises a first transfer line extending at least partially along the first direction, and the pixel driving circuit comprises at least one transistor, and the at least one transistor comprises an active pattern;

[0008] A distance between a normal projection of at least part of the first transfer line of the at least one data transfer line on the substrate and a normal projection of at least part of the active pattern of the at least one transistor extending along the first direction on the substrate is less than a first threshold distance, or a distance between a film layer in which the first transfer line of the at least one data transfer line is located and a film layer in which the active pattern of the at least one transistor is located is greater than a second threshold distance.

[0009] In an example embodiment, the at least one data routing line further comprises: a second routing line extending at least partially along a second direction, the first direction intersecting the second direction;

[0010] The first routing line and the second routing line in the at least one data routing line are electrically connected, and a projection of the second routing line of the at least one data routing line on the substrate at least partially overlaps a projection of the at least one data signal line on the substrate.

[0011] In an example embodiment, the at least one transistor further comprises: a first pole and a second pole;

[0012] The first threshold distance is less than 1 micrometer;

[0013] The second threshold distance is a distance between a film layer in which an active pattern of the at least one transistor is located and a film layer in which the first pole and the second pole of the at least one transistor are located.

[0014] In an example embodiment, the first routing line and the second routing line in the at least one data routing line are arranged in the same layer when a distance between a projection of at least part of the first routing line of the at least one data routing line on the substrate and a projection of at least part of the active pattern of the at least one transistor on the substrate along the first direction is less than a first threshold.

[0015] In an example embodiment, further comprising: a circuit structure layer arranged on the substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0016] The first routing line and the second routing line in the at least one data routing line and the first pole and the second pole of the at least one transistor are located in the third conductive layer, and the data signal line is located in the fifth conductive layer.

[0017] In an example embodiment, the at least one pixel driving circuit comprises: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, a second pole of the second transistor and a first pole of the sixth transistor are electrically connected to a second pole of the third transistor respectively, a first pole of the second transistor is electrically connected to a control pole of the third transistor, a first pole of the fourth transistor is electrically connected to a data signal line, and a second pole of the fourth transistor is electrically connected to a first pole of the third transistor;

[0018] The active pattern of the at least one transistor comprises a channel region and first and second regions located on both sides of the channel region, the first electrode of the at least one transistor is electrically connected to the first region of the active pattern of the at least one transistor, and the second electrode of the at least one transistor is electrically connected to the second region of the active pattern of the at least one transistor.

[0019] In the at least one pixel driving circuit, the second region of the active pattern of the second transistor, the second region of the active pattern of the third transistor, and the first region of the active pattern of the sixth transistor are in an integrated structure, the second region of the active pattern of the second transistor and at least one of the active patterns of the sixth transistor extend at least partially along the first direction, and the second region of the active pattern of the second transistor and the active pattern of the sixth transistor are arranged along the second direction.

[0020] The first transfer line of the at least one data transfer line is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit and is in an integrated structure.

[0021] The distance between the orthogonal projection of at least part of the first transfer line of the at least one data transfer line on the substrate and the orthogonal projection of at least part of the second region of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction on the substrate is less than the first threshold distance.

[0022] The row in which the second pixel driving circuit is located is the same row as the row in which the first pixel driving circuit is located, and the column in which the second pixel driving circuit is located is the next column of the column in which the first pixel driving circuit is located.

[0023] In an example embodiment, the first transfer line of the at least one data transfer line is in the shape of a broken line and comprises a first transfer portion, a second transfer portion, and a third transfer portion.

[0024] The first transfer portion extends at least partially along the first direction and is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit, the second transfer portion is electrically connected to the first transfer portion and the third transfer portion respectively, and the third transfer portion extends at least partially along the first direction and is electrically connected to the second transfer line.

[0025] In an example embodiment, the orthogonal projection of the third transfer portion of the first transfer line of the at least one data transfer line on the substrate at least partially overlaps the orthogonal projection of at least part of the active pattern of the sixth transistor in the second pixel driving circuit extending along the first direction on the substrate.

[0026] In an example embodiment, a projection of at least part of the first transition portion of the first transition line of the at least one data transition line on the substrate is located away from a side of the first pixel driving circuit.

[0027] In an example embodiment, a projection of at least part of the first transition portion of the first transition line of the at least one data transition line on the substrate is located between a projection of an active pattern of the fourth transistor in the first pixel driving circuit on the substrate and a projection of an active pattern of the second transistor in the second pixel driving circuit on the substrate.

[0028] An active pattern of the fourth transistor in the at least one pixel driving circuit extends at least partially along the first direction, and a distance between a projection of at least part of the first transition portion of the first transition line of the at least one data transition line on the substrate and a projection of the active pattern of the fourth transistor in the first pixel driving circuit on the substrate is less than a first threshold distance.

[0029] In an example embodiment, further comprising: a plurality of scan signal lines and a plurality of light emitting signal lines disposed on the substrate, the scan signal lines and the light emitting signal lines extending at least partially along the second direction;

[0030] Control electrodes of the second transistor and the fourth transistor in the at least one pixel driving circuit are electrically connected with at least one scan signal line respectively, and a sixth transistor in the at least one pixel driving circuit is electrically connected with at least one light emitting signal line;

[0031] A projection of the first transition portion of the first transition line of the at least one data transition line on the substrate at least partially overlaps with a projection of the scan signal line connected with at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate;

[0032] A projection of the second transition portion of the first transition line of the at least one data transition line on the substrate is located between a projection of the scan signal line connected with the first pixel driving circuit on the substrate and a projection of the light emitting signal line connected with the first pixel driving circuit on the substrate;

[0033] A projection of the third transition portion of the first transition line of the at least one data transition line on the substrate at least partially overlaps with a projection of the light emitting signal line connected with the first pixel driving circuit on the substrate.

[0034] In an example embodiment, when the distance between the film layer in which the first data wire of the at least one data wire is located and the film layer in which the active pattern of the at least one transistor is located is greater than the second threshold distance, the first data wire of the at least one data wire is located on the side of the second data wire away from the substrate.

[0035] In an example embodiment, further comprising: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer;

[0036] The second data wire of the at least one data wire and the first pole and the second pole of the at least one transistor are located in the third conductive layer, the first data wire of the at least one data wire is located in the fourth conductive layer, and the data signal line is located in the fifth conductive layer.

[0037] In an example embodiment, the at least one pixel driving circuit comprises: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, the second pole of the second transistor and the first pole of the sixth transistor are electrically connected to the second pole of the third transistor respectively, the first pole of the second transistor is electrically connected to the control pole of the third transistor, the first pole of the fourth transistor is electrically connected to the data signal line, and the second pole of the fourth transistor is electrically connected to the first pole of the third transistor.

[0038] The first data wire of the at least one data wire is electrically connected to the first pole of the fourth transistor in the first pixel driving circuit.

[0039] At least part of the orthographic projection of the first data wire of the at least one data wire on the substrate at least partially overlaps between at least part of the orthographic projection of the second zone of the active pattern of the second transistor in the second pixel driving circuit and at least part of the orthographic projection of the active pattern of the sixth transistor on the substrate along the first direction.

[0040] The row in which the second pixel driving circuit is located is the same row as the row in which the first pixel driving circuit is located, and the column in which the second pixel driving circuit is located is the next column of the column in which the first pixel driving circuit is located.

[0041] In an exemplary embodiment, further comprising: a plurality of scan signal lines and a plurality of light emission signal lines disposed on the substrate, the control electrode of the second transistor and the control electrode of the fourth transistor in the at least one pixel driving circuit are electrically connected with at least one scan signal line respectively, and the sixth transistor in the at least one pixel driving circuit is electrically connected with at least one light emission signal line;

[0042] The first transfer line of the at least one data transfer line is in a straight line type;

[0043] The orthographic projection of the first transfer line of the at least one data transfer line on the substrate at least partially overlaps the orthographic projection of the scan signal line and the light emission signal line connected with at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate.

[0044] In an exemplary embodiment, further comprising: a plurality of first reset signal lines disposed on the substrate;

[0045] The at least one pixel driving circuit comprises: a first transistor and a seventh transistor, the control electrode of the first transistor is electrically connected with at least one first reset signal line, and the second electrode of the seventh transistor is electrically connected with the second electrode of the sixth transistor and the light emitting device connected with the pixel driving circuit respectively;

[0046] The orthographic projection of the second transfer line of the at least one data transfer line on the substrate is located between the orthographic projection of the light emission signal line connected with the first pixel driving circuit on the substrate and the orthographic projection of the first reset signal line connected with the next row of pixel driving circuit of the first pixel driving circuit on the substrate.

[0047] In an exemplary embodiment, further comprising: a plurality of first power supply lines disposed on the substrate, the first power supply lines are located on the side of the data signal line close to the substrate;

[0048] The at least one pixel driving circuit comprises: a capacitor, the capacitor comprises: a first electrode plate and a second electrode plate, the second electrode plate of the capacitor is provided with an opening, and the orthographic projection of the opening on the substrate is located within the orthographic projection of the first electrode plate of the capacitor on the substrate;

[0049] The orthographic projection of the at least one first power supply line on the substrate covers the orthographic projection of the opening of the second electrode plate of the capacitor in the pixel driving circuit connected with the first power supply line on the substrate.

[0050] In an example embodiment, comprising: a display region, the display region comprising: a first display area and a second display area located at least one side of the first display area, the first display area and the second display area comprising: arrayed light emitting devices disposed on the substrate, arrayed pixel driving circuit and a plurality of data signal lines disposed in the second display area:

[0051] At least one light emitting device located in the first display area is electrically connected with at least one pixel driving circuit located in the second display area;

[0052] The light emitting devices located in at least one display area of the first display area and the second display area comprise: a first light emitting device, a second light emitting device and a third light emitting device;

[0053] In the same display area, the light emitting area of the first light emitting device is greater than the light emitting area of the second light emitting device and less than the light emitting area of the third light emitting device;

[0054] The light emitting area of the first light emitting device located in the first display area is less than the light emitting area of the first light emitting device located in the second display area, the light emitting area of the second light emitting device located in the first display area is less than the light emitting area of the second light emitting device located in the second display area, and the light emitting area of the third light emitting device located in the first display area is less than the light emitting area of the third light emitting device located in the second display area,

[0055] At least two second light emitting devices located in the first display area are connected with the same pixel driving circuit located in the second display area.

[0056] In an example embodiment, further comprising: a plurality of anode connection lines;

[0057] At least one anode connection line is electrically connected with at least one light emitting device located in the first display area and at least one pixel driving circuit located in the second display area, respectively;

[0058] The anode connection line is a transparent conductive line.

[0059] In an example embodiment, the orthogonal projection of the at least one data signal line on the substrate is located in the second display area, and the at least one data signal line is at least partially surrounded in the periphery of the first display area.

[0060] In an example embodiment, further comprising: a plurality of second power lines and a plurality of power transfer lines disposed on the substrate; at least one light emitting device is electrically connected with at least one second power line, and at least one second power line extends at least partially along the first direction;

[0061] The second power lines are arranged in the same layer as the data signal lines, and at least one power transfer line is electrically connected with the at least one second power line.

[0062] In a second aspect, the present disclosure also provides a display device, comprising the display substrate and the photosensitive sensor.

[0063] The photosensitive sensor is located in the first display area of the display substrate and is located on a side away from the light-out side of the display substrate.

[0064] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0065] The accompanying drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical solutions of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0066] Figure 1 It is a structural schematic diagram of a display device;

[0067] Figure 2 It is a structural schematic diagram of a display substrate;

[0068] Figure 3 It is an equivalent circuit diagram of a pixel driving circuit;

[0069] Figure 4 It is Figure 3 It is a working timing diagram of the pixel driving circuit provided;

[0070] Figure 5 It is a structural schematic diagram of the display substrate provided by the embodiment of the present disclosure;

[0071] Figure 6 It is a schematic diagram of the display substrate provided by the embodiment of the present disclosure in the second display area Figure 1 ;

[0072] Figure 7 It is a schematic diagram of the display substrate provided by the embodiment of the present disclosure in the second display area Figure 2

[0073] Figure 8 It is a schematic diagram of the display substrate provided by the embodiment of the present disclosure in the second display area Figure 3 ;

[0074] Figure 9 It is a schematic diagram of the arrangement of the light-emitting device of the display area;

[0075] Figure 10 It is a schematic diagram of the connection of the pixel driving circuit of the second display area and the light-emitting device of the first display area;

[0076] Figure 11 A structural schematic diagram of a display device provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0077] For the purposes of the present disclosure, the technical solutions and advantages will be more clearly apparent from the following detailed description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings. Note that the embodiments can be implemented in many different forms. It should be readily understood by those skilled in the art that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict. In order to keep the following description of the embodiments of the present disclosure clear and brief, detailed descriptions of some known functions and known components are omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0078] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only structural schematic diagrams, and one mode of the present disclosure is not limited to the shapes or values shown in the drawings.

[0079] In the present specification, ordinal numbers such as "first", "second", "third", and the like are provided to avoid confusion of the components, and are not intended to be limited in terms of quantity.

[0080] In the present specification, for the convenience of explanation, words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0081] In this specification, unless otherwise specified and limited, the terms "mount", "connected", and "coupled" are to be interpreted broadly. For example, they can be fixed connections, or detachable connections, or integrally connected; they can be mechanical connections, or electrical connections; they can be direct connections, or indirect connections through intermediaries, or internal connections between two elements. Those skilled in the art can understand the specific meanings of the above terms in the present disclosure according to the specific circumstances.

[0082] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region refers to a region where current flows mainly.

[0083] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0084] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having a variety of functions.

[0085] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0086] In the present disclosure, A extends along the direction of B means that A can include a main portion and a sub-portion connected to the main portion, the main portion is a line, a line segment, or a bar-shaped body, the main portion extends along the direction of B, and the length of the main portion extending along the direction of B is greater than the length of the sub-portion extending along another direction. In the following description, "A extends along the direction of B" means "the main portion of A extends along the direction of B".

[0087] In this specification, "film" and "layer" can be replaced with each other. For example, "conductive layer" can be replaced with "conductive film" at times. Similarly, "insulating film" can be replaced with "insulating layer" at times.

[0088] In this specification, "disposed in the same layer" means that two (or more) structures are patterned by one patterning process and the materials thereof can be the same or different. For example, the materials of precursors for forming the two (or more) structures disposed in the same layer are the same and the materials of the finally formed structures can be the same or different.

[0089] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, can have some small deformation due to a tolerance, can have a rounded corner, a rounded side, or a deformation, and the like.

[0090] In this specification, "about" means that a limit is not strictly defined and a value within a range of a process and a measurement error is allowed.

[0091] Figure 1 A structure diagram of a display device. As shown in Figure 1 The display device can include a timing controller, a data driver, a scan driver, an emission driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the emission driver, respectively. The data driver is connected to a plurality of data signal lines (e.g., D1 to Dn), the scan driver is connected to a plurality of scan signal lines (e.g., S1 to Sm), and the emission driver is connected to a plurality of emission signal lines (e.g., E1 to Eo), respectively. n, m, and o can be natural numbers. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers. At least one sub-pixel Pxij can include a pixel driving circuit and an emission device connected to the pixel driving circuit. The pixel driving circuit can include at least a pixel driving circuit, and the pixel driving circuit can be connected to the scan signal line, the emission signal line, and the data signal line, respectively.

[0092] In an exemplary embodiment, the timing controller can provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, can provide clock signals, a scan start signal, and the like suitable for the specifications of the scan driver to the scan driver, and can provide clock signals, an emission stop signal, and the like suitable for the specifications of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the grayscale values and the control signals received from the timing controller. For example, the data driver can sample the grayscale values using the clock signals and apply data voltages corresponding to the grayscale values to the data signal lines D1 to Dn in units of pixels. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signals, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide scan signals having on-pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of an on-pulse to a next stage circuit under the control of the clock signals. The light emitting driver can generate light emission control signals to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signals, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide emission signals having off-pulse to the light emission signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register and can generate the light emission control signals in a manner that sequentially transfers the emission stop signal provided in the form of an off-pulse to a next stage circuit under the control of the clock signals.

[0093] Figure 2 FIG. 1 is a schematic view of a structure of a display substrate. Figure 2 As shown, the display substrate can include a display area AA, a binding area CC located at one side of the display area AA, and a bezel area BB located at the other side of the display area AA.

[0094] In an exemplary embodiment, the display area AA can be a flat area including a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij can be configured to display dynamic pictures or still images, and the display area AA can be referred to as an active area (AA). In some examples, the display substrate can employ a flexible substrate, and thus, the display substrate can be deformable, for example, rolled, bent, folded, or rolled up.

[0095] In an exemplary embodiment, the binding area can include a lead area, a bending area, and a complex circuit area sequentially arranged in a direction away from the display area, the lead area is connected to the display area, the bending area is connected to the lead area, and the complex circuit area is connected to the bending area.

[0096] In an example embodiment, the lead region can be provided with a plurality of lead-out lines, one end of the plurality of lead-out lines being connected to the plurality of data signal lines in the display region, and the other end of the plurality of lead-out lines being connected to the integrated circuit of the composite circuit region, such that the integrated circuit is applied to the data signal lines through the lead-out lines.

[0097] In an example embodiment, the bending region can be curved with a curvature, and the surface of the composite circuit region can be reversed, i.e., the surface of the composite circuit region facing upward can be converted into a surface facing downward through the bending of the bending region, and the third direction intersects the first direction. In an example embodiment, when the bending region is curved, the composite circuit region can overlap the display region in the thickness direction.

[0098] In an example embodiment, the composite circuit region can include an anti-static region, a driving chip region, and a binding pin region, an integrated circuit (IC) can be bound and connected to the driving chip region, and a flexible printed circuit (FPC) can be bound and connected to the binding pin region. In an example embodiment, the integrated circuit can generate a driving signal required for driving a sub-pixel, and can provide the driving signal to the sub-pixel in the display region. For example, the driving signal can be a data signal that drives the luminance of the sub-pixel. In an example embodiment, the integrated circuit can be bound and connected to the driving chip region through anisotropic conductive film or other means, and the width of the integrated circuit in the second direction can be less than the width of the composite circuit region in the second direction, and the second direction intersects the first direction. In an example embodiment, the binding pin region can be provided with a pad including a plurality of pins (PINs), and the flexible printed circuit can be bound and connected to the pad.

[0099] In an example embodiment, the bezel region BB can include, in order along a direction away from the display region AA, a circuit region, a power line region, a crack dam region, and a cutting region. The circuit region is connected to the display region AA, and can include at least a scan driver and a light emitting driver. The power line region is connected to the circuit region, and can include at least a bezel power lead extending in a direction parallel to the edge of the display region. The crack dam region is connected to the power line region, and can include at least a plurality of cracks provided on a composite insulating layer. The cutting region is connected to the crack dam region, and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0100] The display region can include a plurality of pixel units arranged in a matrix manner. At least one pixel unit can include a first sub-pixel emitting first color light, a second sub-pixel emitting second color light, and a third sub-pixel and a fourth sub-pixel emitting third color light. Each sub-pixel can include a circuit unit and a light emitting device. The circuit unit can include at least a pixel driving circuit connected with a scan signal line, a data signal line and a light emitting signal line. The pixel driving circuit can be configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, output a corresponding current to the light emitting device, and drive the light emitting device to emit light. The light emitting device in each sub-pixel is connected with the pixel driving circuit of the sub-pixel, and the light emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0101] In an example embodiment, at least one pixel driving circuit can be electrically connected with at least one light emitting device.

[0102] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) emitting red light, the second sub-pixel P2 can be a blue sub-pixel (B) emitting blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) emitting green light.

[0103] In some examples, the shape of the light emitting region of the light emitting device of at least one sub-pixel can be rectangular, diamond, pentagonal or hexagonal.

[0104] In an example embodiment, the pixel driving circuit can include a plurality of transistors and at least one capacitor, for example, the pixel driving circuit can be a 3T1C (3 transistors and 1 capacitor) structure, a 5T1C (5 transistors and 1 capacitor) structure, a 7T1C (7 transistors and 1 capacitor) structure, or an 8T1C (8 transistors and 1 capacitor) structure.

[0105] In an example embodiment, the light emitting device can be an organic light emitting diode (OLED), which emits red light, green light, blue light, or white light, etc. under the driving of its corresponding pixel driving circuit. The light emitting color of the light emitting device can be determined as needed. The light emitting device can include an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting device can be electrically connected with the corresponding pixel driving circuit. However, the present embodiment is not limited thereto.

[0106] Figure 3 An equivalent circuit diagram of a pixel driving circuit. Figure 3 is described taking the pixel driving circuit as an example of a 7T1C structure. As Figure 3As shown, the at least one pixel driving circuit is electrically connected with a scan signal line Gate, a first reset signal line Reset1, a second reset signal line Reset2, a data signal line Data, an emission signal line EM, a first initial signal line INIT1, a second initial signal line INIT2 and a first power supply line VDD respectively, and the light emitting device L is electrically connected with the pixel driving circuit and a second power supply line VSS respectively. In some examples, the first power supply line VDD is configured to provide a constant first power supply signal to the pixel driving circuit, the first power supply signal is a positive voltage signal, the second power supply line VSS is configured to provide a constant second power supply signal to the pixel driving circuit, the second power supply signal is a negative voltage signal. The scan signal line Gate is configured to provide a scan signal to the pixel driving circuit, the first reset signal line Reset1 is configured to provide a first reset signal to the pixel driving circuit, the second reset signal line Reset2 is configured to provide a second reset signal to the pixel driving circuit, the data signal line Data is configured to provide a data signal to the pixel driving circuit, the emission signal line EM is configured to provide an emission control signal to the pixel driving circuit, the first initial signal line INIT1 is configured to provide a first initial signal to the pixel driving circuit, and the second initial signal line INIT2 is configured to provide a second initial signal to the pixel driving circuit.

[0107] In some examples, the signal received by the second reset signal line connected with the at least one row of pixel driving circuits is the same as the signal received by the scan signal line connected with the at least one row of pixel driving circuits, and the signal received by the first reset signal line connected with the at least one row of pixel driving circuits is the same as the signal received by the scan signal line connected with the at least one row of pixel driving circuits. For example, the signal received by the second reset signal line connected with the nth row of pixel driving circuits is the same as the signal received by the scan signal line connected with the (n-1)th row of pixel driving circuits, and the signal received by the first reset signal line connected with the nth row of pixel driving circuits is the same as the signal received by the scan signal line connected with the (n-2)th row of pixel driving circuits. Since the signal received by at least one of the first reset signal line and the second reset signal line connected with the at least one row of pixel driving circuits is the same as the signal received by the scan signal line connected with the at least one row of pixel driving circuits, the scan driver located in the frame area can include a gate driving circuit electrically connected with the first reset signal line, the second reset signal line and the scan signal line connected with the at least one row of pixel driving circuits, so as to reduce the area occupied by the circuit area and improve the resolution of the display substrate. The resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, which can be referred to as pixel density. The higher the PPI value, the higher the density at which the display substrate can display the picture, and the more details the picture has.

[0108] In some examples, the signal received by the first reset signal line connected to the (n+1)th row of pixel driving circuits is the same as the signal received by the second reset signal line connected to the nth row of pixel driving circuits, that is, the first reset signal line connected to the (n+1)th row of pixel driving circuits and the second reset signal line connected to the nth row of pixel driving circuits can be the same signal, so that the number of signal lines of the display substrate can be reduced, and a high PPI of the display substrate can be achieved.

[0109] In some examples, the signal received by the first initial signal line connected to the nth row of pixel driving circuits is the same as the signal received by the second initial signal line connected to the nth row of pixel driving circuits, that is, the first initial signal line connected to the nth row of pixel driving circuits and the second initial signal line connected to the nth row of pixel driving circuits can be the same signal, so that the number of signal lines of the display substrate can be reduced, and a high PPI of the display substrate can be achieved.

[0110] In an example embodiment, as shown in Figure 3 the at least one pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a capacitor C, the capacitor C includes a first plate and a second plate. The control electrode of the first transistor T1 is electrically connected to a first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to a first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to a fifth node N5. The control electrode of the second transistor T2 is electrically connected to a scan signal line Gate, the first electrode of the second transistor T2 is electrically connected to a first node N1, and the second electrode of the second transistor T2 is electrically connected to a third node N3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to a second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is electrically connected to a data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the fifth transistor T5 is electrically connected to an emission signal line EM, the first electrode of the fifth transistor T5 is electrically connected to a first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The control electrode of the sixth transistor T6 is electrically connected to the emission signal line EM, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to a fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to a second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to a second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the first power supply line VDD.

[0111] In the present disclosure, the first node N1 is a connection point of the capacitor C, the first transistor T1, the second transistor T2 and the third transistor T3. Specifically, the first node N1 is a connection point of the first plate of the capacitor C, the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the control electrode of the third transistor T3.

[0112] In the present disclosure, the second node N2 is a connection point of the third transistor T3, the fourth transistor T4 and the fifth transistor T5. Specifically, the second node N2 is a connection point of the first electrode of the third transistor T3, the second electrode of the fourth transistor T4 and the second electrode of the fifth transistor T5.

[0113] In the present disclosure, the third node N3 is a connection point of the second transistor T2, the third transistor T3 and the sixth transistor T6. Specifically, the third node N3 is a connection point of the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0114] In the present disclosure, the fourth node N4 is a connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting device L. Specifically, the fourth node N4 is a connection point of the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the anode of the light emitting device L.

[0115] According to the characteristic of the transistor, the transistor can be divided into N-type transistor and P-type transistor. When the transistor is a P-type transistor, the on voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage), and the off voltage is a high voltage (for example, 5V, 10V or other suitable voltage). When the transistor is an N-type transistor, the on voltage is a high voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low voltage (for example, 0V, -5V, -10V or other suitable voltage).

[0116] In the exemplary embodiments, the first transistor T1 to the seventh transistor T7 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 can include P-type transistors and N-type transistors.

[0117] In an exemplary embodiment, the seven transistors of the pixel driving circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OPTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPTs offer advantages such as low leakage current. Integrating LTPS and OPTs onto a single display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0118] Figure 4 for Figure 3 The provided timing diagram for the pixel driving circuit is shown below. Figure 4 right Figure 3 The operation of the pixel driving circuit shown is explained. The first transistor T1 to the seventh transistor T7 in the pixel driving circuit are P-type transistors.

[0119] In some exemplary implementations, such as Figure 3 and Figure 4 As shown, during a single frame display period, the operation of the pixel driving circuit can include: a first stage P1, a second stage P2, a third stage P3, and a fourth stage P4.

[0120] In the first stage P1, also known as the first reset stage, the signal on the first reset signal line Reset1 is low, while the signals on the scan signal line Gate, the second reset signal line Reset2, and the light emission signal line EM are high. The first transistor T1 is turned on, while the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off.

[0121] The first transistor T1 is turned on, and the first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize the first node N1, clear its internal pre-stored voltage, and complete the initialization.

[0122] In the second stage (P2), the second reset stage, the signal on the second reset signal line Reset2 is low, while the signals on the scan signal line Gate, the first reset signal line Reset1, and the light emission signal line EM are high. The seventh transistor T7 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0123] The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, the anode of the light emitting device L is initialized (reset), the internal pre-stored voltage is emptied, the initialization is completed, and it is ensured that the light emitting device L does not emit light.

[0124] The third phase P3 is called a data writing phase or a threshold compensation phase. The signal of the scan signal line Gate is a low level signal, the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the emitting signal line EM are high level signals. The data signal line Data outputs a data signal. The second transistor T2 and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are turned off.

[0125] The second transistor T2 and the fourth transistor T4 are turned on, and the data signal output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the turned-on third transistor T3 and the turned-on second transistor T2, until the signal of the first node satisfies Vdata-|Vth|, wherein Vdata is the voltage value of the data signal output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3.

[0126] The fourth phase P4 is called an emitting phase. The signal of the emitting signal line EM is a low level signal, the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the scan signal line Gate are high level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are turned off.

[0127] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power signal output by the first power supply line VDD is provided to the fourth node N4 (that is, the anode of the light emitting device L) through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, so as to drive the light emitting device L to emit light.

[0128] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between the control electrode and the first electrode of the third transistor T3. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0129] I = K × (Vgs-Vth) 2 = K × [(Vdd-Vdata+|Vth|)-Vth] 2 = K × (Vdd-Vdata) 2

[0130] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting device, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, and Vdd is the voltage value of the power signal output by the first power line VDD.

[0131] The concept of a full-screen mobile phone has been widely concerned in the mobile phone market and is the development direction of future mobile phones. In a full-screen mobile phone, a camera is arranged in a display area (Full Display with Camera, FDC for short) structure, that is, the area where the camera is arranged is also displayed. The FDC structure can make the front visual area almost entirely a screen, thereby providing a user with better display effect.

[0132] With the development of OLED display technology, consumers have increasingly high requirements for the display effect of display products, and extremely narrow frames have become a new trend in the development of display products. Therefore, the narrowing of frames or even frameless design is increasingly valued in the design of OLED display products. In order to achieve a narrow frame, a display substrate adopts a Fanout in Panel (FIP for short) structure, that is, one end of a plurality of data conversion lines is connected to a plurality of data signal lines in a display area, and the other end of the plurality of data conversion lines extends to a binding area and is connected to an integrated circuit in the binding area. Since no slant line in the shape of a fan needs to be arranged in the binding area, the width of the fanout area is reduced, and the lower frame width is effectively reduced.

[0133] The load between at least one data conversion line and the active pattern of at least one transistor (for example, the active pattern of the second transistor, the active pattern of the third transistor, and the active pattern of the sixth transistor) in the display substrate is large, which causes the voltage value of the first node in the at least one pixel driving circuit to decrease, causes the driving voltage output by the at least one pixel driving circuit to be large, the brightness of part of the area of the display substrate is large, the brightness uniformity of the display substrate is reduced, and the display effect of the display substrate is affected.

[0134] Therefore, the display substrate provided by the present disclosure can improve the brightness uniformity of the display substrate and improve the display effect of the display substrate.

[0135] Figure 5 A structural schematic diagram of the display substrate provided by the present disclosure is provided, Figure 6 A schematic diagram of the display substrate provided by the present disclosure in the second display area is provided Figure 1 , Figure 7 A schematic diagram of the display substrate provided by the present disclosure in the second display area is provided Figure 2 , Figure 8 A schematic diagram of the display substrate provided by the present disclosure in the second display area is provided Figure 3 . AsFigure 5 As shown, the display substrate provided by the embodiments of the present disclosure includes a substrate, and an array of pixel driving circuits, a plurality of data signal lines Data, and a plurality of data transfer lines FL arranged on the substrate. At least one data transfer line FL is electrically connected to at least one data signal line Data.

[0136] The second display area A2 includes at least one pixel driving circuit and at least one data signal line Data electrically connected to the at least one pixel driving circuit, and the at least one data signal line Data at least partially extends along the first direction D1.

[0137] In exemplary embodiments, as shown, Figure 5 The display substrate includes a display area AA, and the display area AA includes a first display area A1 and a second display area A2 located at least one side of the first display area A1. The first display area A1 and the second display area A2 include an array of light emitting devices arranged on a substrate, and an array of pixel driving circuits and a plurality of data signal lines Data are located in the second display area A2.

[0138] As shown, Figure 6 to Figure 8 The at least one data transfer line FL includes a first transfer line FL1 at least partially extending along the first direction D1.

[0139] In exemplary embodiments, the pixel driving circuit includes at least one transistor and a capacitor. The at least one transistor includes an active pattern, a control electrode, a first electrode, and a second electrode. The capacitor includes a first electrode plate and a second electrode plate. The pixel driving circuit can be Figure 3 The pixel driving circuit provided by the embodiments of the present disclosure.

[0140] In the present disclosure, the distance between A and B can refer to the distance between the boundary of A close to B and the boundary of B close to A, or can be the distance between the boundary of A away from B and the boundary of B away from A, or can be the distance between any part of A and any part of B, and the present disclosure does not make any limitation on this.

[0141] In the present disclosure, the distance L1 between the orthographic projection of at least part of the first transfer line FL1 of the at least one data transfer line on the substrate and the orthographic projection of at least part of the active pattern of the at least one transistor extending along the first direction D1 on the substrate is less than a first threshold distance, or the distance between the film layer in which the first transfer line FL1 of the at least one data transfer line is located and the film layer in which the active pattern of the at least one transistor is located is greater than a second threshold distance. Figure 6 and Figure 7is explained by taking an example in which a distance between a normal projection of at least a portion of a first data transfer line FL1 of the at least one data transfer line on the substrate and a normal projection of at least a portion of an active pattern of the at least one transistor extending along a first direction D1 on the substrate is less than a first threshold distance, Figure 8 is explained by taking an example in which a distance between a film layer in which the first data transfer line FL1 of the at least one data transfer line is located and a film layer in which the active pattern of the at least one transistor is located is greater than a second threshold distance.

[0142] The present disclosure can reduce or eliminate a load between the data transfer line and a partial active pattern in the pixel driving circuit by taking the distance between the normal projection of at least a portion of the first data transfer line of the at least one data transfer line on the substrate and the normal projection of at least a portion of the active pattern of the at least one transistor extending along the first direction on the substrate to be less than the first threshold distance, or taking the distance between the film layer in which the first data transfer line of the at least one data transfer line is located and the film layer in which the active pattern of the at least one transistor is located to be greater than the second threshold distance, so as to improve the brightness uniformity of the display substrate, and further improve the display effect of the display substrate.

[0143] In the example embodiment, the second display area A2 is configured to display an image, and the first display area A1 can also correspond to a position of the optical device, and the first display area A1 is configured to display an image and transmit light, and the transmitted light is received by the optical device. In the example embodiment, the first display area can be referred to as a light-transmissive display area or an under-display camera (UDC) area, and the second display area can be referred to as a normal display area.

[0144] In the example embodiment, the position of the first display area A1 in the second display area A2 is not limited, and can be located at an upper portion or a lower portion of the second display area A2, or can be located at an edge position of the second display area A2, and the present disclosure does not make any limitation in this regard.

[0145] In the example embodiment, in a plane parallel to the display device, the shape of the first display area A1 can be any one or more of a rectangle, a polygon, a circle, and an ellipse, and the optical device can be an optical sensor such as a fingerprint recognition device, a camera, or a 3D imaging device. For example, the first display area A1 can be circular, and the size of the normal projection of the photosensitive sensor on the display substrate can be less than or equal to the size of the first display area A1. However, the present embodiment does not make any limitation in this regard. In other examples, the first display area can be rectangular, and the size of the normal projection of the photosensitive sensor on the display substrate can be less than or equal to the size of an inscribed circle of the first display area.

[0146] In some example embodiments, the display area AA can be a rectangle, for example, a round-cornered rectangle. The second display area A2 can be a circle or an ellipse. However, the present embodiments are not limited thereto. For example, the second display area A2 can be a rectangle, a pentagon, or a hexagon, or other shapes.

[0147] In example embodiments, the resolution of the first display area A1 and the second display area A2 can be the same, or the resolution of the first display area A1 can be less than that of the second display area A2. For example, the resolution of the first display area A1 can be about 50% to 70% or so of that of the second display area A2. The resolution (Pixels Per Inch, PPI) refers to the number of pixels per unit area, which can be referred to as pixel density. The higher the PPI value, the higher the density at which the display substrate can display a picture, and the more detailed the picture.

[0148] In example embodiments, the substrate can be a flexible substrate, or can be a rigid substrate. The display substrate includes a plurality of sub-pixels, each of which can include a pixel driving circuit composed of a plurality of transistors and a capacitor, and a light emitting device.

[0149] In example embodiments, the light emitting device can include a current driving type device, and can adopt a current type light emitting diode, such as a Micro Light Emitting Diode (Micro LED) or a Mini Light Emitting Diode (Mini LED) or an Organic Light Emitting Diode (OLED) or a Quantum Light Emitting Diode (QLED). The typical size (e.g., length) of a Micro LED can be less than 100 μm, for example, 10 μm to 50 μm. The typical size (e.g., length) of a Mini LED can be about 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0150] In example embodiments, the light emitting device can include at least an anode, an organic light emitting layer, and a cathode. The anode of the light emitting device is connected to the pixel driving circuit, the organic light emitting layer is connected to the anode, and the cathode is connected to the organic light emitting layer. The organic light emitting layer emits light of a corresponding color under the driving of the anode and the cathode.

[0151] In an exemplary embodiment, the organic light-emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In an exemplary embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0152] In an exemplary embodiment, as shown in FIG. 1, at least one data flex line FL further includes a second flex line FL2 extending at least partially along the second direction D2. Figure 6 to Figure 8

[0153] In the present disclosure, the first direction D1 intersects the second direction D2, where the first direction D1 intersects the second direction D2 means that the included angle between the first direction D1 and the second direction D2 is about 70 degrees to 90 degrees. The first direction D1 and the second direction D2 can be located in the same plane. For example, the first direction D1 can be parallel to the extension direction of the data signal line Data; the second direction can be parallel to the extension direction of the scan signal line or the light-emitting signal line.

[0154] In an exemplary embodiment, the first flex line FL1 and the second flex line FL2 located in the same data flex line FL are electrically connected, and the second flex line FL2 of at least one data flex line FL in the at least one data flex line FL has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of at least one data signal line in the plurality of data signal lines on the substrate.

[0155] In an exemplary embodiment, at least one data flex line FL further includes a third flex line (not shown in the figure) extending at least partially along the first direction D1. The third flex line is electrically connected with the signal line in the lead area in the bonding area.

[0156] ​In an exemplary embodiment, the second display area can be divided into a first sub-display area and a second sub-display area, the first sub-display area being an area provided with the data routing line, and the second sub-display area being the remaining display area except the first sub-display area in the second display area. The second sub-display area is provided with a virtual routing line, which is not electrically connected with the at least one data signal line. The provision of the virtual routing line can improve the etching uniformity of the display substrate.

[0157] In an exemplary embodiment, the first threshold distance can be less than 1 micrometer.

[0158] In an exemplary embodiment, the second threshold distance is a distance between a film layer in which the active pattern of the at least one transistor is located and a film layer in which the first electrode and the second electrode of the at least one transistor are located.

[0159] In an exemplary embodiment, as shown in Figure 6 and Figure 7 When the distance between at least part of the first routing line FL1 of the at least one data routing line and the orthographic projection of at least part of the active pattern of the at least one transistor extending along the first direction D1 on the base is less than the first threshold, the first routing line FL1 and the second routing line FL2 in the at least one data routing line are provided in the same layer.

[0160] In an exemplary embodiment, as shown in Figure 6 to Figure 8 The second display area A2 further includes a plurality of scan signal lines Gate, a plurality of light-emitting signal lines EM, a plurality of first reset signal lines Reset1 and a plurality of second reset signal lines Reset2. At least one of the plurality of scan signal lines Gate, the plurality of light-emitting signal lines EM, the plurality of first reset signal lines Reset1 and the plurality of second reset signal lines Reset2 extends at least partially along the second direction D2. Among them, Figure 6 to Figure 8 Gate(n) in the above formula refers to the scan signal line connected with the nth row of pixel driving circuit, EM(n) refers to the light-emitting signal line connected with the nth row of pixel driving circuit, Reset1(n) refers to the first reset signal line connected with the nth row of pixel driving circuit, and Reset2(n) refers to the second reset signal line connected with the nth row of pixel driving circuit. Reset1(n) and the second reset signal line Reset2(n-1) connected with the (n-1)th row of pixel driving circuit are the same signal line.

[0161] In an exemplary embodiment, as shown in Figure 6 to Figure 8 The film layer in which at least one of the plurality of scan signal lines Gate, the plurality of light-emitting signal lines EM, the plurality of first reset signal lines Reset1 and the plurality of second reset signal lines Reset2 is located is located on the side of the film layer in which the data routing line FL is located close to the base.

[0162] In an example embodiment, the display substrate can include: a circuit structure layer disposed on the base, the circuit structure layer including: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer.

[0163] In an example embodiment, the semiconductor layer can include at least: an active pattern of at least one transistor. The active pattern of at least one transistor can include: an active pattern 11 of a first transistor to an active pattern 71 of a seventh transistor.

[0164] In an example embodiment, the first conductive layer can include at least: a plurality of scanning signal lines Gate, a plurality of light-emitting signal lines EM, a plurality of first reset signal lines Reset1, a plurality of second reset signal lines Reset2, and a control electrode of at least one transistor and a first plate C1 of a capacitor.

[0165] In an example embodiment, the second conductive layer can include at least: a first plate of a capacitor.

[0166] In an example embodiment, the third conductive layer can include at least: a first electrode and a second electrode of at least one transistor. The first electrode and the second electrode of at least one transistor can include: a first electrode 13 and a second electrode 24 of a first transistor, a first electrode 23 of a second transistor, a first electrode 43 of a fourth transistor, a first electrode 53 of a fifth transistor, a second electrode 63 of a sixth transistor, a first electrode 73 and a second electrode 74 of a seventh transistor.

[0167] In an example embodiment, the fourth conductive layer can include at least: a first power supply line.

[0168] In an example embodiment, the fifth conductive layer can include at least: a data signal line.

[0169] In an example embodiment, the display substrate can further include, in a direction perpendicular to a plane of the display substrate, a light-emitting structure layer disposed on a side of the circuit structure layer away from the base, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the base. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, and the like, which are not limited in the present disclosure.

[0170] In an example embodiment, the light-emitting structure layer can include: an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit through a via, the organic light-emitting layer being connected to the anode, the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under driving of the anode and the cathode.

[0171] In an example embodiment, the encapsulation structure layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to prevent external water vapor from entering the light-emitting structure layer.

[0172] In an example embodiment, the touch structure layer can include a first touch insulation layer arranged on the encapsulation structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer, the first touch metal layer can include a plurality of bridge electrodes, the second touch metal layer can include a plurality of first touch electrodes and second touch electrodes, and the first touch electrodes or the second touch electrodes can be connected to the bridge electrodes through vias.

[0173] In an example embodiment, the active pattern of the at least one transistor includes a channel region and first and second regions located on both sides of the channel region, the first electrode of the at least one transistor is electrically connected to the first region of the active pattern of the at least one transistor, and the second electrode of the at least one transistor is electrically connected to the second region of the active pattern of the at least one transistor. Among them, in the at least one pixel driving circuit, the second region 21-2 of the active pattern of the second transistor, the second region 31-2 of the active pattern of the third transistor, and the first region 61-1 of the active pattern of the sixth transistor are one-piece structures, the second region 21-2 of the active pattern of the second transistor and at least one of the active patterns 61 of the sixth transistor at least partially extend along the first direction D1, and the second region 21-2 of the active pattern of the second transistor and the active pattern 61 of the sixth transistor are arranged along the second direction D2.

[0174] As shown in Figure 6 and Figure 7 , the first transfer line FL1 of the at least one data transfer line is electrically connected to the first electrode 43 of the fourth transistor in the first pixel driving circuit, and is a one-piece structure.

[0175] As shown in Figure 6 and Figure 7 , the distance L1 between the orthographic projection of at least part of the first transfer line FL1 of the at least one data transfer line on the substrate and the orthographic projection of at least part of the second region 21-2 of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction D1 on the substrate is less than a first threshold distance.

[0176] As shown in Figure 6 and Figure 7 , the distance L1 between the orthographic projection of at least part of the first transfer line FL1 of the at least one data transfer line on the substrate and the orthographic projection of at least part of the second region 21-2 of the active pattern of the second transistor in the second pixel driving circuit extending along the first direction D1 on the substrate is less than a first threshold distance.As shown, the row where the first pixel driving circuit is located is the same row as the row where the second pixel driving circuit is located, and the column where the second pixel driving circuit is located is the next column after the column where the first pixel driving circuit is located. Figure 6 and Figure 7 The pixel driving circuit in the nth row and mth column is the first pixel driving circuit, and the pixel driving circuit in the nth row and m+1th column is the second pixel driving circuit.

[0177] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, the first adapter cable FL1 of at least one data adapter cable is in the shape of a broken line and includes: a first adapter part FL11, a second adapter part FL12 and a third adapter part FL13.

[0178] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, the first adapter FL11 extends at least partially along the first direction D1 and is electrically connected to the first pole 43 of the fourth transistor in the first pixel driving circuit. The second adapter FL12 is electrically connected to the first adapter FL11 and the third adapter FL13 respectively. The third adapter FL13 extends at least partially along the first direction D1 and is electrically connected to the second adapter FL2.

[0179] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, for the same first adapter cable FL1, the first adapter part FL11 and the second adapter part FL12 are set at an obtuse angle, and the second adapter part FL12 and the third adapter part FL13 are set at an obtuse angle.

[0180] In an exemplary implementation, such as Figure 6 and Figure 7 As shown, the orthographic projection of the third adapter portion FL13 of the first adapter FL1 of at least one data adapter on the substrate at least partially overlaps with the orthographic projection of at least a portion of the active pattern 61 of the sixth transistor in the second pixel driving circuit extending along the first direction D1 on the substrate. Since the sixth transistor is not electrically connected to any signal line, the orthographic projection of the third adapter portion FL13 of the first adapter FL1 of at least one data adapter in this disclosure on the substrate does not overlap with the orthographic projection of the signal line connected to at least one pixel driving circuit on the substrate. This reduces the coupling capacitance between the data adapter and the signal line connected to at least one pixel driving circuit, thus ensuring the reliability of the display substrate.

[0181] In an exemplary implementation, such as Figure 7As shown, at least part of the first transfer portion FL11 of the first transfer line FL1 of the at least one data transfer line has a projection on the substrate that is located between the projection on the substrate of the active pattern 41 of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern 21 of the second transistor in the second pixel driving circuit.

[0182] In an example embodiment, as shown in Figure 6 As shown, at least part of the first transfer portion FL11 of the first transfer line FL1 of the at least one data transfer line has a projection on the substrate that is located between the projection on the substrate of the active pattern 41 of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern 21 of the second transistor in the second pixel driving circuit.

[0183] In an example embodiment, as shown in Figure 7 As shown, at least part of the first transfer portion FL11 of the first transfer line FL1 of the at least one data transfer line has a projection on the substrate that is located between the projection on the substrate of the active pattern 41 of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern 21 of the second transistor in the second pixel driving circuit.

[0184] In an example embodiment, as shown in Figure 6 and Figure 7 As shown, at least part of the first transfer portion FL11 of the first transfer line FL1 of the at least one data transfer line has a projection on the substrate that is located between the projection on the substrate of the active pattern 41 of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern 21 of the second transistor in the second pixel driving circuit.

[0185] In an example embodiment, as shown in Figure 6 and Figure 7 As shown, at least part of the first transfer portion FL11 of the first transfer line FL1 of the at least one data transfer line has a projection on the substrate that is located between the projection on the substrate of the active pattern 41 of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern 21 of the second transistor in the second pixel driving circuit.

[0186] In an example embodiment, as shown in Figure 8 and Figure 8 As shown, at least part of the first transfer portion FL11 of the first transfer line FL1 of the at least one data transfer line has a projection on the substrate that is located between the projection on the substrate of the active pattern 41 of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern 21 of the second transistor in the second pixel driving circuit.

[0187] The first to third data transfer lines in the at least one data transfer line in the present disclosure can be arranged in a manner that can reduce the coupling capacitance between the at least one data transfer line and the signal line connected to the at least one pixel driving circuit, thereby improving the reliability of the display substrate.

[0188] In an example embodiment, as shown in Figure 8 When the distance between the film layer in which the first data transfer line FL1 of the at least one data transfer line is located and the film layer in which the active pattern of the at least one transistor is located is greater than a second threshold distance, the first data transfer line FL1 of the at least one data transfer line FL is located on the side of the second data transfer line FL2 away from the substrate.

[0189] In an example embodiment, as shown in Figure 8 The third conductive layer at least further includes the second data transfer line FL2 of the at least one data transfer line FL.

[0190] In an example embodiment, as shown in Figure 8 The fourth conductive layer at least includes the first data transfer line FL1 of the at least one data transfer line FL.

[0191] In an example embodiment, as shown in Figure 8 The first data transfer line FL1 of the at least one data transfer line is electrically connected to the first electrode 43 of the fourth transistor in the first pixel driving circuit.

[0192] In an example embodiment, as shown in Figure 8 The first data transfer line FL1 of the at least one data transfer line at least partially overlaps between the orthographic projection of the first data transfer line FL1 on the substrate and the orthographic projection of the at least part of the second region 21-2 of the active pattern of the second transistor in the second pixel driving circuit and the orthographic projection of the at least part of the active pattern of the active pattern 61 of the sixth transistor extending along the first direction D1 on the substrate. Wherein the row in which the first pixel driving circuit is located and the row in which the second pixel driving circuit is located are the same row, and the column in which the second pixel driving circuit is located is the next column of the column in which the first pixel driving circuit is located. Figure 8 The pixel driving circuit in the nth row and the mth column in the array is the first pixel driving circuit, and the pixel driving circuit in the nth row and the m+1th column is the second pixel driving circuit.

[0193] In an example embodiment, as shown in Figure 8 The first data transfer line FL1 of the at least one data transfer line is a straight line type.

[0194] In an example embodiment, as shown in Figure 8As shown in FIG. 1, a first projection of the first data transfer line FL1 on the substrate at least partially overlaps a first projection of the scan signal line Gate and the emission signal line EM connected to at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate.

[0195] In an example embodiment, as shown in FIG. 1, the display substrate further comprises a plurality of first power lines VDD arranged on the substrate, and the first power line VDD is located on a side of the data signal line Data close to the substrate. Figure 9 As shown in FIG. 1, a second projection of the second data transfer line FL2 on the substrate at least partially overlaps a first projection of the active pattern 71 of the seventh transistor in the at least one pixel driving circuit on the substrate, and is located between a second projection of the emission signal line EM connected to the first pixel driving circuit on the substrate and a second projection of the first reset signal line Reset1 connected to the next row of pixel driving circuits of the first pixel driving circuit on the substrate.

[0196] The arrangement of the first data transfer line and the second data transfer line in the at least one data transfer line in the present disclosure can improve the reliability of the display substrate by reducing the coupling capacitance between the at least one data transfer line and the signal line connected to the at least one pixel driving circuit.

[0197] The arrangement of the data transfer line in the present disclosure can reasonably utilize the space of the layout.

[0198] In an example embodiment, as shown in FIG. 1, the display substrate further comprises a plurality of first power lines VDD arranged on the substrate, and the first power line VDD is located on a side of the data signal line Data close to the substrate. Figure 9

[0199] In an example embodiment, the second plate of the capacitor is provided with an opening V, and a first projection of the opening V on the substrate is located within a range of a first projection of the first plate C1 of the capacitor on the substrate.

[0200] In an example embodiment, a first projection of the at least one first power line VDD on the substrate covers a second projection of the opening V of the second plate of the capacitor in the pixel driving circuit connected to the first power line VDD on the substrate. The first projection of the at least one first power line VDD on the substrate covering the second projection of the opening V of the second plate of the capacitor in the pixel driving circuit connected to the first power line VDD can avoid the influence of the remaining signal lines on the first plate of the capacitor, and can ensure the stability of the signal of the first node in the pixel driving circuit.

[0201] In an example embodiment, the at least one light emitting device located in the first display area A1 is electrically connected to the at least one pixel driving circuit located in the second display area A2. The first display area A1 in the present disclosure is not provided with the pixel driving circuit, and the light transmittance of the first display area can be improved.

[0202] Figure 9 ​A schematic view of the arrangement of the light emitting devices in the display area is shown. As shown in Figure 9 The light emitting devices in at least one of the first display area A1 and the second display area A2 include a first light emitting device, a second light emitting device and a third light emitting device. Exemplarily, the second light emitting device emits light rays having a wavelength greater than that of the third light emitting device and less than that of the first light emitting device. For example, the first light emitting device can be a red light emitting device, the second light emitting device can be a green light emitting device, and the third light emitting device can be a blue light emitting device. However, the present embodiment is not limited thereto.

[0203] In an exemplary embodiment, as shown in Figure 9 In the first display area A1 or the second display area A2, a plurality of second light emitting devices are arranged in the ith row with a certain interval, the first light emitting devices and the third light emitting devices are alternately arranged in the ith+1 row adjacent to the ith row, a plurality of second light emitting devices are arranged in the ith+2 row adjacent to the ith+1 row with a certain interval, and the first light emitting devices and the third light emitting devices are alternately arranged in the ith+3 row adjacent to the ith+2 row. The above arrangement can be repeated for multiple rows of light emitting devices.

[0204] In an exemplary embodiment, as shown in Figure 9 In the same display area, the light emitting area of the first light emitting device is greater than that of the second light emitting device and less than that of the third light emitting device. Exemplarily, in the first display area A1, the light emitting area of the first light emitting device A11 is greater than that of the second light emitting device A12 and less than that of the third light emitting device A13, and in the second display area A2, the light emitting area of the first light emitting device A21 is greater than that of the second light emitting device A22 and less than that of the third light emitting device A23.

[0205] In an exemplary embodiment, as shown in Figure 10 The light emitting area of the first light emitting device A11 in the first display area A1 is less than that of the first light emitting device A21 in the second display area A2, the light emitting area of the second light emitting device A12 in the first display area A1 is less than that of the second light emitting device A22 in the second display area A2, and the light emitting area of the third light emitting device A13 in the first display area A1 is less than that of the third light emitting device A23 in the second display area A2.

[0206] In an exemplary embodiment, as shown in Figure 10As shown, at least two second light emitting devices located in the first display area A1 are connected to the same pixel driving circuit located in the second display area A2. Connecting at least two second light emitting devices located in the first display area A1 to the same pixel driving circuit located in the second display area A2 can reduce the number of signal lines of the display area, and thus can improve the light transmittance of the first display area.

[0207] In an example embodiment, Figure 10 FIG. 4 is a schematic diagram of the connection of the pixel driving circuit of the second display area and the light emitting device of the first display area. As shown in FIG. 4, the pixel driving circuit of the second display area is connected to the light emitting device of the first display area. Figure 5 As shown, the display substrate further comprises a plurality of anode connection lines EL. At least one anode connection line EL is electrically connected to at least one light emitting device located in the first display area A1 and at least one pixel driving circuit located in the second display area A2, respectively.

[0208] In an example embodiment, the anode connection line EL is a transparent conductive line.

[0209] In an example embodiment, the pixel driving circuit can comprise a first type of pixel driving circuit and a second type of pixel driving circuit. The first type of pixel driving circuit is electrically connected to the light emitting device located in the first display area, and the second type of pixel driving circuit is electrically connected to the light emitting device located in the second display area.

[0210] In an example embodiment, the orthographic projection of at least one second type of pixel driving circuit on the substrate at least partially overlaps with the orthographic projection of the anode of at least one light emitting device located in the second display area on the substrate.

[0211] In an example embodiment, the orthographic projection of at least one first type of pixel driving circuit on the substrate does not have an overlapping area with the orthographic projection of the anode of at least one light emitting device located in the first display area on the substrate.

[0212] In an example embodiment, at least one first type of pixel driving circuit and a plurality of second type of pixel driving circuits can be arranged alternately. Figure 11 FIG. 5 is a schematic diagram of the pixel driving circuit of the display substrate in FIG. 4, which is described by taking the example of the first type of pixel driving circuit HP and the four second type of pixel driving circuits P arranged alternately.

[0213] In an example embodiment, the display substrate of the present disclosure can be applied to a display device with pixel driving circuits, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED), or quantum dot light emitting diode display (QDLED), etc., which are not limited by the present disclosure.

[0214] In an example embodiment, as shown in FIG. 6, Figure 11As shown, the orthogonal projection of the at least one data signal line Data on the substrate is located in the second display area A2, and the at least one data signal line Data at least partially surrounds the periphery of the first display area A1.

[0215] In an example embodiment, the second display area A2 further includes: a plurality of second power supply lines and a plurality of power supply transfer lines arranged on the substrate; at least one light emitting device is electrically connected to at least one second power supply line, and the at least one second power supply line at least partially extends along the first direction D1. The arrangement of the power supply transfer line in the present disclosure can improve the residual image problem of screen off.

[0216] In an example embodiment, the display substrate can include: a via hole exposing the cathode of the at least one light emitting device, and the at least one second power supply line is electrically connected to the cathode of the at least one light emitting device through the via hole exposing the cathode of the at least one light emitting device.

[0217] In an example embodiment, the display substrate can further include: a second power supply bus located in the non-display area, and the at least one second power supply line is electrically connected to the second power supply bus.

[0218] In an example embodiment, the power supply transfer line can be arranged in the same direction as the data transfer line, and the present disclosure does not make any limitation in this regard.

[0219] In an example embodiment, the second power supply line can be arranged on the same layer as the data signal line, and at least one power supply transfer line is electrically connected to at least one second power supply line.

[0220] ​ A structural schematic diagram of a display device provided by an embodiment of the present disclosure is shown. As shown, the display device provided by an embodiment of the present disclosure can include: the display substrate 1 and the photosensitive sensor 2 provided by any one of the foregoing embodiments. Wherein, the photosensitive sensor 2 is located in the first display area A1 of the display substrate 1, and is located on the side away from the light emitting side of the display substrate 1. ​

[0221] In an example embodiment, the display substrate can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate.

[0222] In an example embodiment, when the light-transmitting display area A1 is rectangular, the orthogonal projection area of the photosensitive sensor 2 on the substrate is less than or equal to the area of the inscribed circle of the light-transmitting display area A1.

[0223] ​In exemplary embodiments, the photosensitive sensor 2 can include at least one of a camera module (e.g., a front-facing camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), etc.

[0224] In exemplary embodiments, the front-facing camera module is typically enabled when a user takes a selfie or video call, and the display area of the display device displays the image obtained by the selfie for the user to view. The front-facing camera module includes, for example, a lens, an image sensor, an image processing chip, etc. An optical image of a scene generated by the lens is projected onto the surface of the image sensor (which includes both CCD and CMOS) to be converted into an electrical signal, which is converted into a digital image signal by the image processing chip after analog-digital conversion, and then sent to the processor for processing, and the image of the scene is output on the display screen.

[0225] In exemplary embodiments, the 3D structured light sensor and the time-of-flight (ToF) sensor can be used for face recognition to unlock the display device.

[0226] The display device provided by the embodiments of the present disclosure can display an image in the light-transmitting display area to maintain the display integrity of the entire display device.

[0227] In addition, the display device can be any device that displays images whether in motion (e.g., video) or stationary (e.g., still images) and whether text or graphics. More specifically, it is contemplated that the embodiments can be implemented in and / or used with a variety of electronic devices, such as, but not limited to, mobile telephones, wireless devices, personal data assistants, handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, navigation systems, audio / video player, audio / video recorder, microphones, video cameras, display, etc. The embodiments are not limited in this context.

[0228] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0229] For clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness and size of layers or microstructures are exaggerated. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intervening element.

[0230] Although the disclosed embodiments have been fully described above with reference to the attachments, figures, and the accompanying drawings, other embodiments can be utilized and changes can be made without departing from the scope of the disclosure, which is not to be limited by the above-described embodiments. Accordingly, various modifications and changes can be made to the embodiments without departing from the scope of the disclosure as set forth in the claims below. The disclosure is not to be limited to the embodiments set forth herein for the purpose of the practice of the present disclosure.

Claims

1. A display substrate, characterized by, The display panel comprises a substrate and an array of pixel driving circuits, a plurality of data signal lines and a plurality of data transfer lines arranged on the substrate, at least one pixel driving circuit is electrically connected with at least one data signal line, and the at least one data signal line extends at least partially along a first direction; At least one data transfer line is electrically connected with at least one data signal line; The at least one data transfer line comprises a first transfer line extending at least partially along the first direction, and the pixel driving circuit comprises at least one transistor, and the at least one transistor comprises an active pattern; A distance between a projection of at least part of the first transfer line of the at least one data transfer line on the substrate and a projection of at least part of the active pattern of the at least one transistor on the substrate along the first direction is less than a first threshold distance, or a distance between a film layer in which the first transfer line of the at least one data transfer line is located and a film layer in which the active pattern of the at least one transistor is located is greater than a second threshold distance.

2. The display substrate of claim 1, wherein, The at least one data transfer line further comprises a second transfer line extending at least partially along a second direction, and the first direction intersects the second direction; The first transfer line and the second transfer line in the same data transfer line are electrically connected, and a projection of the second transfer line of the at least one data transfer line on the substrate at least partially overlaps a projection of the at least one data signal line on the substrate.

3. The display substrate of claim 1, wherein, The at least one transistor further comprises a first electrode and a second electrode; The first threshold distance is less than 1 micrometer; The second threshold distance is a distance between a film layer in which the active pattern of the at least one transistor is located and a film layer in which the first electrode and the second electrode of the at least one transistor are located.

4. The display substrate of claim 2, wherein, When a distance between a projection of at least part of the first transfer line of the at least one data transfer line on the substrate and a projection of at least part of the active pattern of the at least one transistor on the substrate along the first direction is less than a first threshold distance, the first transfer line and the second transfer line in the at least one data transfer line are arranged in the same layer.

5. The display substrate of claim 4, wherein, Further comprising: A circuit structure layer arranged on the substrate, and the circuit structure layer comprises a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer; The first transfer line and the second transfer line in the at least one data transfer line and the first electrode and the second electrode of the at least one transistor are located in the third conductive layer, and the data signal line is located in the fifth conductive layer. 6.The display substrate of claim 4, wherein, The at least one pixel driving circuit comprises a second transistor, a third transistor, a fourth transistor and a sixth transistor, the third transistor is a driving transistor, a second electrode of the second transistor and a first electrode of the sixth transistor are electrically connected with a second electrode of the third transistor respectively, a first electrode of the second transistor is electrically connected with a control electrode of the third transistor, a first electrode of the fourth transistor is electrically connected with a data signal line, and a second electrode of the fourth transistor is electrically connected with a first electrode of the third transistor; The active pattern of the at least one transistor comprises a channel region and first and second regions located on both sides of the channel region, a first electrode of the at least one transistor is electrically connected to the first region of the active pattern of the at least one transistor, and a second electrode of the at least one transistor is electrically connected to the second region of the active pattern of the at least one transistor; In the at least one pixel driving circuit, the second region of the active pattern of the second transistor, the second region of the active pattern of the third transistor, and the first region of the active pattern of the sixth transistor are in an integral structure, the second region of the active pattern of the second transistor and at least one of the active patterns of the sixth transistor extend at least partially along the first direction, and the second region of the active pattern of the second transistor and the active pattern of the sixth transistor are arranged along the second direction; The first transfer line of the at least one data transfer line is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit and is in an integral structure; A distance between a projection on the substrate of at least part of the first transfer line of the at least one data transfer line and a projection on the substrate of at least part of the second region of the active pattern of the second transistor in the second pixel driving circuit along the first direction is less than the first threshold distance; The row where the first pixel driving circuit is located is the same row as the row where the second pixel driving circuit is located, and the column where the second pixel driving circuit is located is the next column of the column where the first pixel driving circuit is located. 7.The display substrate of claim 6, wherein, The first transfer line of the at least one data transfer line is in a polyline shape and comprises a first transfer part, a second transfer part, and a third transfer part; The first transfer part extends at least partially along the first direction and is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit, the second transfer part is electrically connected to the first transfer part and the third transfer part respectively, and the third transfer part extends at least partially along the first direction and is electrically connected to the second transfer line. 8.The display substrate of claim 7, wherein, A projection on the substrate of the third transfer part of the first transfer line of the at least one data transfer line at least partially overlaps with a projection on the substrate of at least part of the active pattern of the sixth transistor in the second pixel driving circuit along the first direction. 9.The display substrate of claim 7, wherein, At least part of the projection on the substrate of the first transfer part of the first transfer line of the at least one data transfer line is located on a side of the projection on the substrate of at least one of the active pattern of the second transistor and the active pattern of the sixth transistor in the second pixel driving circuit away from the first pixel driving circuit. 10.The display substrate of claim 7, wherein, At least part of the projection on the substrate of the first transfer part of the first transfer line of the at least one data transfer line is located between the projection on the substrate of the active pattern of the fourth transistor in the first pixel driving circuit and the projection on the substrate of the active pattern of the second transistor in the second pixel driving circuit. An active pattern of the fourth transistor in the at least one pixel driving circuit extends at least partially along the first direction, and a distance between a normal projection of the first transfer part of the first transfer line of the at least one data transfer line on the substrate and a normal projection of the active pattern of the fourth transistor in the first pixel driving circuit on the substrate is less than a first threshold distance. 11.The display substrate of claim 7, wherein, Further comprising: a plurality of scanning signal lines and a plurality of light-emitting signal lines disposed on the substrate, the scanning signal lines and the light-emitting signal lines extending at least partially along the second direction; the control electrodes of the second transistor and the fourth transistor in the at least one pixel driving circuit are electrically connected with at least one scanning signal line, and the sixth transistor in the at least one pixel driving circuit is electrically connected with at least one light-emitting signal line; a normal projection of the first transfer part of the first transfer line of the at least one data transfer line on the substrate at least partially overlaps with a normal projection of the scanning signal line connected with at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate; a normal projection of the second transfer part of the first transfer line of the at least one data transfer line on the substrate is located between a normal projection of the scanning signal line connected with the first pixel driving circuit on the substrate and a normal projection of the light-emitting signal line connected with the first pixel driving circuit on the substrate; a normal projection of the third transfer part of the first transfer line of the at least one data transfer line on the substrate at least partially overlaps with a normal projection of the light-emitting signal line connected with the first pixel driving circuit on the substrate. 12.The display substrate of claim 2, wherein, When a distance between a film layer in which the first transfer line of the at least one data transfer line is located and a film layer in which an active pattern of the at least one transistor is located is greater than the second threshold distance, the first transfer line in the at least one data transfer line is located on a side of the second transfer line away from the substrate. 13.The display substrate of claim 12, wherein, Further comprising: a circuit structure layer disposed on the substrate, the circuit structure layer comprising: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer; the second transfer line in the at least one data transfer line and the first electrode and the second electrode of the at least one transistor are located in the third conductive layer, the first transfer line in the at least one data transfer line is located in the fourth conductive layer, and the data signal line is located in the fifth conductive layer. 14.The display substrate of claim 6, wherein, The at least one pixel driving circuit comprises: a second transistor, a third transistor, a fourth transistor, and a sixth transistor, wherein the third transistor is a driving transistor, the second electrode of the second transistor and the first electrode of the sixth transistor are electrically connected with the second electrode of the third transistor respectively, the first electrode of the second transistor is electrically connected with the control electrode of the third transistor, the first electrode of the fourth transistor is electrically connected with a data signal line, and the second electrode of the fourth transistor is electrically connected with the first electrode of the third transistor. The first end of the first data transfer line is electrically connected to the first electrode of the fourth transistor in the first pixel driving circuit; The normal projection of at least part of the first data transfer line on the substrate at least partially overlaps with the normal projection of at least part of the second region of the active pattern of the second transistor and at least part of the active pattern of the sixth transistor in the second pixel driving circuit along the first direction on the substrate; The row where the first pixel driving circuit is located is the same as the row where the second pixel driving circuit is located, and the column where the second pixel driving circuit is located is the next column of the column where the first pixel driving circuit is located.

15. The display substrate of claim 14, wherein, Further comprising: A plurality of scanning signal lines and a plurality of light-emitting signal lines are arranged on the substrate, the control electrode of the second transistor and the control electrode of the fourth transistor in the at least one pixel driving circuit are respectively electrically connected to at least one scanning signal line, and the sixth transistor in the at least one pixel driving circuit is electrically connected to at least one light-emitting signal line; The first data transfer line of the at least one data transfer line is linear; The normal projection of the first data transfer line of the at least one data transfer line on the substrate at least partially overlaps with the normal projection of the scanning signal line and the light-emitting signal line connected to at least one of the first pixel driving circuit and the second pixel driving circuit on the substrate. 16.The display substrate of claim 15, wherein, Further comprising: A plurality of first reset signal lines are arranged on the substrate; The at least one pixel driving circuit comprises a first transistor and a seventh transistor, the control electrode of the first transistor is electrically connected to at least one first reset signal line, and the second electrode of the seventh transistor is electrically connected to the second electrode of the sixth transistor and the light-emitting device connected to the pixel driving circuit; The normal projection of the second data transfer line of the at least one data transfer line on the substrate is located between the normal projection of the light-emitting signal line connected to the first pixel driving circuit on the substrate and the normal projection of the first reset signal line connected to the next row of pixel driving circuits of the first pixel driving circuit on the substrate. 17.The display substrate of claim 1, wherein, Further comprising: A plurality of first power supply lines are arranged on the substrate, and the first power supply lines are located on the side of the data signal line close to the substrate; The at least one pixel driving circuit comprises a capacitor, the capacitor comprises a first electrode plate and a second electrode plate, the second electrode plate of the capacitor is provided with an opening, and the normal projection of the opening on the substrate is located within the normal projection of the first electrode plate of the capacitor on the substrate; The normal projection of the at least one first power supply line on the substrate covers the normal projection of the opening of the second electrode plate of the capacitor in the pixel driving circuit connected by the first power supply line on the substrate. 18.The display substrate of claim 1, wherein, Comprise: The display region comprises a first display area and a second display area located at least one side of the first display area, the first display area and the second display area comprise: arrayed light emitting devices arranged on the substrate, arrayed pixel driving circuits and a plurality of data signal lines arranged in the second display area: At least one light emitting device in the first display area is electrically connected with at least one pixel driving circuit in the second display area; The light emitting devices in at least one display area of the first display area and the second display area comprise: first light emitting devices, second light emitting devices and third light emitting devices; In the same display area, the light emitting area of the first light emitting device is larger than the light emitting area of the second light emitting device and smaller than the light emitting area of the third light emitting device; The light emitting area of the first light emitting device in the first display area is smaller than the light emitting area of the first light emitting device in the second display area, the light emitting area of the second light emitting device in the first display area is smaller than the light emitting area of the second light emitting device in the second display area, and the light emitting area of the third light emitting device in the first display area is smaller than the light emitting area of the third light emitting device in the second display area, At least two second light emitting devices in the first display area are connected with the same pixel driving circuit in the second display area. 19.The display substrate of claim 18, wherein, Further comprising: A plurality of anode connection lines; At least one anode connection line is electrically connected with at least one light emitting device in the first display area and at least one pixel driving circuit in the second display area respectively; The anode connection line is a transparent conductive line. 20.The display substrate of claim 18, wherein, The orthographic projection of the at least one data signal line on the substrate is located in the second display area, and the at least one data signal line is at least partially surrounded in the periphery of the first display area. 21.The display substrate of claim 1, wherein, Further comprising: A plurality of second power lines and a plurality of power transfer lines arranged on the substrate; at least one light emitting device is electrically connected with at least one second power line, and the at least one second power line extends at least partially along the first direction; The second power line is arranged in the same layer as the data signal line, and at least one power transfer line is electrically connected with the at least one second power line.

22. A display device comprising: Comprise: The display substrate and the photosensitive sensor according to any one of claims 1 to 21; The photosensitive sensor is located in the first display area of the display substrate and is located on the side away from the light emitting side of the display substrate.

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