Trigger system wake-up circuit and electronic equipment

Abstract

The utility model provides a trigger system wake-up circuit and electronic equipment, and the trigger system wake-up circuit comprises a trigger signal input end; the switch circuit comprises a first switch branch circuit and a second switch branch circuit which are connected between the trigger signal input end and the system wake-up input end; the control end of the first switch branch is connected with the trigger signal input end; the key circuit is connected between a node between the second switch branch and the system wake-up input end and the electrode ground; when the trigger signal input end receives a wake-up instruction, the first switch branch and the second switch branch are conducted in sequence, a rising edge signal is formed at the system wake-up input end, and the system is triggered to be in a wake-up state from a sleep state; when the key circuit is pressed, a rising edge signal is formed at the system awakening input end, and the system is triggered to be in an awakening state from a sleep state.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a trigger system wake-up circuit and electronic device. Background Technology

[0002] Currently, electronic device systems typically have only one wake-up terminal, supporting only one wake-up method. If an electronic device wants to support multiple wake-up methods, it usually needs to be replaced with a more advanced system-on-a-chip (SoC). This increases both cost and product size, and the implementation of multiple wake-up methods in a more advanced SoC consumes more embedded system resources. As electronic devices become increasingly complex and feature-rich, wake-up circuits that support multiple wake-up methods are becoming essential. Summary of the Invention

[0003] To address the existing technical problems, this application provides a simple, low-cost, and widely applicable trigger system wake-up circuit and electronic device.

[0004] In a first aspect, embodiments of this application provide a system wake-up triggering circuit, including:

[0005] Trigger signal input terminal;

[0006] The switching circuit includes a first switching branch and a second switching branch connected between the trigger signal input terminal and the system wake-up input terminal; the control terminal of the first switching branch is connected to the trigger signal input terminal.

[0007] The button circuit is connected between the node and the ground electrode between the second switch branch and the system wake-up input terminal;

[0008] When the trigger signal input terminal receives a wake-up command, the first switch branch and the second switch branch are turned on in sequence, forming a rising edge signal at the system wake-up input terminal, triggering the system to transition from sleep state to wake-up state; when the button circuit is pressed, a rising edge signal is formed at the system wake-up input terminal, triggering the system to transition from sleep state to wake-up state.

[0009] In a second aspect, an electronic device is provided, including the trigger system wake-up circuit described in any embodiment of this application.

[0010] The trigger system wake-up circuit provided in the above embodiment is designed with a first switch branch and a second switch branch connected to the system wake-up input terminal. The control terminal of the first switch branch is connected to the trigger signal input terminal, and a button circuit is set between the second switch branch and the system wake-up input terminal. In this way, the trigger signal input terminal and the system wake-up input terminal can realize multiple triggering methods such as product power-on trigger wake-up and external button interruption wake-up. The first switch branch and the second switch branch are used to generate rising edge signals that can trigger the system from sleep state to wake-up state under different triggering methods. Therefore, it is compatible with existing systems that only include one wake-up terminal. The structure is simple, the cost is low, and it will not increase the system's resource consumption or product size. It has a wide range of applications.

[0011] The electronic devices provided in the above embodiments are based on the same concept as the corresponding trigger system wake-up circuit embodiments, and thus have the same technical effects as the corresponding trigger system wake-up circuit embodiments, which will not be repeated here. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a system wake-up circuit in one embodiment.

[0013] Figure 2 This is a circuit diagram of the wake-up circuit of the trigger system in one embodiment.

[0014] Figure 3 This is a circuit diagram of the system wake-up circuit in another embodiment. Detailed Implementation

[0015] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] In the following description, the phrase "some embodiments" refers to a subset of all possible embodiments. It should be noted that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0018] In the following description, the terms "first, second, and third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, and third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0019] Please see Figure 1 The trigger system wake-up circuit provided in one embodiment of this application includes: a trigger signal input terminal 10; a switch circuit 20, including a first switch branch 21 and a second switch branch 22 connected between the trigger signal input terminal 10 and the system wake-up input terminal 30; the control terminal of the first switch branch 21 is connected to the trigger signal input terminal 10; and a button circuit 23 connected between the node and ground of the second switch branch 22 and the system wake-up input terminal 30. When the trigger signal input terminal 10 receives a wake-up command, the first switch branch 21 and the second switch branch 22 are turned on in sequence, forming a rising edge signal at the system wake-up input terminal 30, triggering the system to change from a sleep state to a wake-up state; when the button circuit 23 is pressed, a rising edge signal is formed at the system wake-up input terminal 30, triggering the system to change from a sleep state to a wake-up state.

[0020] The trigger signal input terminal 10 receives a wake-up command, which can be a power-on signal received when the power button is pressed, or an on signal received when the preset operating system on button is pressed. The system wake-up input terminal 30 refers to the wake-up terminal (pin) of the electronic device's system controller (MCU).

[0021] In the above embodiments, the trigger system wake-up circuit includes a first switch branch 21 and a second switch branch 22 connected to the system wake-up input terminal 30. The trigger signal input terminal 10 and the system wake-up input terminal 30 can realize various triggering methods such as product power-on trigger wake-up and external button interrupt wake-up. The first switch branch 21 and the second switch branch 22 are used to form a rising edge signal that can trigger the system from sleep state to wake-up state under different triggering methods. Therefore, it is compatible with existing systems that only include one wake-up terminal. The structure is simple, the cost is low, and it will not increase the system's resource consumption and product size. It has a wide range of applications.

[0022] The system wake-up input terminal 30 is at a high level when the system is in sleep mode, and the rising edge signal is a high-low-high signal. The first switch branch 21 and the second switch branch 22 are configured so that when the trigger signal input terminal 10 receives a wake-up command, they are sequentially turned on to form a low-level signal and then a high-level signal, thus forming a high-low-high rising edge signal as the wake-up signal to trigger the system from sleep mode to wake-up mode. The button circuit 23 is connected to the node between the second switch branch 22 and the system wake-up input terminal 30. When the button circuit 23 is pressed, it can also first form a low-level signal and then a high-level signal at the system wake-up input terminal 30, thus forming a high-low-high rising edge signal as the wake-up signal to trigger the system from sleep mode to wake-up mode. Thus, the configuration of the first switch branch 21 and the second switch branch 22 allows the same rising edge signal that can trigger the system to switch from sleep state to wake state to wake state to be generated at the system wake-up input terminal 30 when the trigger signal input terminal 10 receives the wake-up command and when the button circuit 23 connected to the second switch branch 22 is pressed. This makes the system wake-up circuit compatible with existing systems that only include one wake-up terminal and can also trigger the system from sleep state to wake state in multiple triggering methods.

[0023] Please see Figure 2 In some embodiments, the first switch branch 21 includes a first transistor Q2, which includes a first control terminal, a first controlled input terminal, and a first controlled output terminal. The first control terminal is connected to the trigger signal input terminal 10, and the first controlled input terminal and the first controlled output terminal are respectively connected to the system wake-up input terminal 30 and ground. The first controlled input terminal is connected to the power supply VCC. In an optional example, the trigger signal input terminal 10 is used to connect to an external power supply to determine whether the system is in a sleep state or a wake-up state. When the trigger signal input terminal 10 is not connected to an external power supply, the system is powered by the power supply VCC and is in a low-power sleep state. When the trigger signal input terminal 10 is connected to an external power supply, the system is powered by the external power supply and is in a wake-up state. The first transistor Q2 is a field-effect transistor. The first controlled input terminal is the drain and the first controlled output terminal is the source. When the system is in sleep mode, if the trigger signal input terminal 10 is not connected to an external power supply, the first controlled input terminal is at a high potential. The power supply VCC supplies power to the system wake-up input terminal 30 through the first controlled input terminal. At this time, the system wake-up input terminal 30 is at a high potential.

[0024] The first switching branch 21 further includes a first voltage divider resistor R5 connected between the trigger signal input terminal 10 and the first control terminal, a first current-limiting resistor R1 connected between the first controlled input terminal and the power supply VCC, and a first rectifier diode D1. The anode of the first rectifier diode D1 is connected to the junction between the first controlled input terminal and the first current-limiting resistor R1, and the cathode of the first rectifier diode D1 is connected to the system wake-up input terminal 30. The setting of the first rectifier diode D1 can ensure the direction of the power supply current from the first switching branch 21 to the system wake-up input terminal 30. The first voltage divider resistor R5 is used to ensure the control terminal voltage of the first transistor Q2, and the first current-limiting resistor R1 is used to regulate the power supply current from the power supply VCC to the system wake-up input terminal 30.

[0025] In some embodiments, the second switch branch 22 includes a second transistor Q1, which includes a second control terminal, a second controlled input terminal, and a second controlled output terminal. The second control terminal is connected to ground, and the second controlled input terminal and the second controlled output terminal are respectively connected to the trigger signal input terminal 10 and the system wake-up input terminal 30. Since the second controlled input terminal and the second controlled output terminal of the second transistor Q1 are connected to the trigger signal input terminal 10 and the system wake-up input terminal 30, when the system is in sleep mode, if the trigger signal input terminal 10 is not connected to an external power supply, the second transistor Q1 remains off due to the internal diode effect. In an optional example, the second transistor Q1 is a field-effect transistor, with the second controlled input terminal as the drain and the second controlled output terminal as the source. When the system is in sleep mode, if the trigger signal input terminal 10 is not connected to an external power supply, the second transistor Q1 is off, and both the second control terminal and the second controlled input terminal are at low potentials. At this time, the power supply VCC supplies power to the system wake-up input terminal 30 through the first controlled input terminal of the first transistor Q2, and the system wake-up input terminal 30 is at a high potential.

[0026] Optionally, the second switching branch 22 further includes a second rectifier diode D2 disposed between the trigger signal input terminal 10 and the second controlled input terminal; the positive terminal of the second rectifier diode D2 is connected to the end of the energy storage circuit 221 connected to the trigger signal input terminal 10, and the negative terminal of the second rectifier diode D2 is connected to the second controlled input terminal. The placement of the second rectifier diode D2, when the system is in sleep mode and the trigger signal input terminal 10 is not connected to an external power supply, can prevent the internal micro-conduction of the second transistor Q1 from turning on, prevent leakage current from the preceding stage to the trigger signal input terminal 10, and maintain the effective cutoff state of the second transistor Q1.

[0027] Optionally, the second switching branch 22 further includes an energy storage circuit 221 located between the second controlled input terminal and the second control terminal; the energy storage circuit 221 includes an energy storage capacitor C1 and an energy storage resistor R3 connected in parallel. When the system is in sleep mode, if the trigger signal input terminal 10 is connected to an external power supply, the setting of the energy storage circuit 221 can delay the turn-on time of the second transistor Q1. During the delayed turn-on time, the system wake-up input terminal 30 remains at a low level under the influence of the first switching branch 21 being turned on. When the second transistor Q1 is turned on, the system wake-up input terminal 30 changes from a low level to a high level, so that the first switching branch 21 and the second switching branch 22 are turned on sequentially, thus forming a rising edge signal of high level-low level-high level as a wake-up signal to trigger the system from sleep mode to wake-up mode.

[0028] Optionally, the second switching branch 22 further includes a second voltage divider resistor R2 connected between the trigger signal input terminal 10 and the positive terminal of the rectifier diode, and a third voltage divider resistor R4 connected between the junction of the energy storage circuit 221 and the second control terminal and the electrode ground. The second voltage divider resistor R2, the energy storage resistor R3, and the third voltage divider resistor R4 form a DC path between the trigger signal input terminal 10 and the electrode ground. When the trigger signal input terminal 10 is connected to an external power supply, the second voltage divider resistor R2 and the energy storage resistor R3 can provide a low potential to the second control terminal of the second transistor Q1, so that the second transistor Q1 can be turned on smoothly.

[0029] In some embodiments, the button circuit 23 includes a button switch S2, and a transient voltage suppression diode D3 and a debounce capacitor C2 connected in parallel with the button switch S2. The button circuit 23 is connected between the electrode ground of the node between the second controlled output terminal of the second transistor Q1 and the system wake-up input terminal 30. When the button switch S2 is pressed, the button switch S2 first closes, short-circuiting the button circuit 23 and pulling the potential at the system wake-up input terminal 30 low. When the button switch S2 is released, the potential at the system wake-up input terminal 30 changes from low to high. Thus, pressing the button switch S2 can generate a low-level signal and a high-level signal sequentially at the system wake-up input terminal 30, forming a rising edge signal of high-low-high as a wake-up signal to trigger the system from sleep state to wake-up state. The debounce capacitor C2 eliminates the bounce phenomenon when the button switch S2 is pressed, ensuring the stability of the button switch state. The transient voltage suppression diode D3 protects the pin of the system wake-up input terminal 30 from damage by transient overvoltages and stabilizes the circuit voltage.

[0030] Optionally, the trigger system wake-up circuit also includes a filter capacitor C3 connected between the trigger signal input terminal 10 and the ground electrode. The filter capacitor C3 can absorb high-frequency noise signals that appear in the circuit, prevent high-frequency noise in the power supply voltage from interfering with the circuit, and store and release electrical energy, thereby improving the stability of the circuit.

[0031] In order to gain a more comprehensive understanding of the wake-up circuit of the triggering system provided in the embodiments of this application, Figure 2 Taking the example shown, the working principle of the system wake-up circuit will be explained:

[0032] The wake-up command received by the trigger signal input terminal 10 is the system power-on command. The trigger signal input terminal 10 uses the connection of external power supply as variable 1 (Trigger source 1) to wake up the system, and the operation of the key switch S2 as variable 2 (Key wake up) to wake up the system.

[0033] When the system is in sleep mode and the trigger signal input terminal 10 is not connected, the potential at the trigger signal input terminal 10 is low. For ease of description, the potential at the trigger signal input terminal 10 is represented by potential point B. At this time, for the first switch branch 21, the first transistor Q2 is off, and the system is powered by the power supply VCC. The current of the power supply VCC flows to the first current limiting resistor R1, the first rectifier diode D1, and the system wake-up input terminal 30. The potential at the system wake-up input terminal 30 is high. For ease of description, the potentials at the power supply VCC and the first controlled input terminal are represented by potential point A, and the potential at the system wake-up input terminal 30 is represented by potential point D. For the second switching branch 22, the second rectifier diode D2 prevents the internal diode effect of the second transistor Q1 from causing it to conduct slightly, preventing the second transistor Q1 from turning on and preventing leakage current from the front stage to the trigger signal input terminal 10. The potential at the system wake-up input terminal 30 of the subsequent stage is pulled low. For ease of description, the potential at the front stage of the energy storage circuit 221 is represented by potential point C, and the potential at the subsequent stage of the energy storage circuit 221 is represented by potential point E. The second transistor Q1 is cut off, and the potential at the second controlled output terminal, i.e., the system wake-up input terminal 30, is at a high level. The potentials at the second control terminal, the second controlled input terminal, and the trigger signal input terminal 10 are all at a low level. The voltage at potential point C can be obtained by voltage division using the second voltage divider resistor R2, the energy storage resistor R3, and the third voltage divider resistor R4, thus making the voltage variable and adjustable with a wider voltage range.

[0034] When the trigger signal input terminal 10 is connected to an external power supply, the potential at the trigger signal input terminal 10 is high (point B is high). At this time, for the first switch branch 21, the first transistor Q2 is turned on, making the potential at the first controlled input terminal low (point A is low), and the potential at the system wake-up input terminal 30 is low (point D is low). For the second switch branch 22, due to the energy storage circuit 221, the turn-on time of the second transistor Q1 is delayed. During the delayed turn-on period, the system wake-up input terminal 30 remains low. When the delay time is reached, the second transistor Q1 is turned on, and the potential at the second controlled output terminal changes from low to high. The voltage signal generates a rising edge, and a rising edge signal of high voltage-low voltage-high voltage is formed at the system wake-up input terminal 30 as the wake-up signal to trigger the system from sleep state to wake-up state.

[0035] When the trigger signal input terminal 10 is connected to an external power supply, the current flow of the external power supply includes the following paths: The first current flow is through the trigger signal input terminal 10, the first voltage divider resistor R5, the first control terminal, and the first transistor Q2, causing the level at the first controlled input terminal to be pulled low, and at the same time, the potential at the system wake-up input terminal 30 is pulled low; the second current flow is through the trigger signal input terminal 10, the second voltage divider resistor R2, the energy storage circuit 221, and the third voltage divider resistor R4. The function of the second current flow includes two aspects: First, the energy storage circuit 221 forms an RC charging circuit, causing the second transistor Q1 to conduct with a delay relative to the first transistor Q2. The energy storage period of the energy storage circuit 221 is... The delayed turn-on time of the second transistor Q1 is such that the first transistor Q2 turns on first, providing a low level (point D is low) to the system wake-up input terminal 30. Secondly, the second voltage divider resistor R2, the energy storage resistor R3, and the third voltage divider resistor R4 provide a low potential (point E is low) to the second control terminal of the second transistor Q1. When the energy storage voltage charging time is reached, causing the second control terminal to reach a preset voltage, the second transistor Q1 turns on, generating a third current flowing through the trigger signal input terminal 10, the second voltage divider resistor R2, and the second transistor Q1, providing a high level (point D is high) to the system wake-up input terminal 30, thus successfully triggering the system to switch from sleep mode to wake-up mode. In this embodiment, the resistance values ​​of the first current-limiting resistor R1, the first voltage divider resistor R5, the second voltage divider resistor R2, the energy storage resistor R3, and the third voltage divider resistor R4 can all be set according to actual conditions, such as 100KΩ. The current value in the circuit can be controlled within tens of microamps (µA), resulting in extremely low power consumption of the overall circuit module.

[0036] When the system is in sleep mode, when the button switch S2 is pressed, the high level at the system wake-up input terminal 30 is pulled low (point D is low level). When the button switch S2 is released and restored, the system wake-up input terminal 30 goes from low level to high level (point D is high level), and the voltage signal generates a rising edge, thus successfully triggering the system to switch from sleep mode to wake-up mode.

[0037] As described above, the trigger system wake-up circuit provided in this application embodiment can be compatible with controllers that have only one wake-up pin to realize multiple triggering methods such as external power-on wake-up of the device and external button switch S2 interrupt wake-up. The circuit structure is simple, the cost is low, and it will not increase the system's resource consumption or product size, and it has a wide range of applications.

[0038] It should be noted that the trigger signal input terminal 10 may include one or more. In an optional example, the trigger signal input terminal 10 includes one or more power supply ports for external power supplies with different voltages. Please refer to [link / reference]. Figure 3 The trigger system wake-up circuit also includes multiple trigger signal input branches 11 connected to the trigger signal input terminal 10. Each trigger signal input branch 11 includes a logic OR gate 112 connected to multiple trigger signal sources and a buffer 113 connected to the output terminal of the logic OR gate 112. The logic OR gate 112 can be used for multiple trigger source inputs. When the trigger source input is not connected to an external power supply, the logic OR gate 112 outputs 0; when the trigger source input is connected to an external power supply, the logic OR gate 112 outputs 1. The buffer 113 can increase the driving capability and optimize the timing of the corresponding trigger signal input branch 11.

[0039] It should be noted that in the wake-up circuit of the trigger system provided in this application embodiment, various circuit devices, such as logic OR gate 112, buffer 113, various resistors and switching transistors, can all be surface-mount devices, which can reduce the overall size of the circuit and is more suitable for the trend of miniaturized products.

[0040] In another aspect, this application provides an electronic device including a trigger system wake-up circuit according to any embodiment of this application.

[0041] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0042] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A trigger system wake-up circuit, characterized in that, include: Trigger signal input terminal; The switching circuit includes a first switching branch and a second switching branch connected between the trigger signal input terminal and the system wake-up input terminal; The control terminal of the first switch branch is connected to the trigger signal input terminal; The button circuit is connected between the node and the ground electrode between the second switch branch and the system wake-up input terminal; When the trigger signal input terminal receives a wake-up command, the first switch branch and the second switch branch are turned on in sequence, forming a rising edge signal at the system wake-up input terminal, triggering the system to transition from sleep state to wake-up state; when the button circuit is pressed, a rising edge signal is formed at the system wake-up input terminal, triggering the system to transition from sleep state to wake-up state.

2. The trigger system wake-up circuit according to claim 1, characterized in that, When the system is in sleep mode, the system wake-up input is at a high level; the rising edge signal is a high-low-high signal.

3. The trigger system wake-up circuit according to claim 1, characterized in that, The first switch branch includes a first transistor, which includes a first control terminal, a first controlled input terminal, and a first controlled output terminal. The control terminal is connected to the trigger signal input terminal, and the first controlled input terminal and the first controlled output terminal are respectively connected to the system wake-up input terminal and ground. The first controlled input terminal is connected to the power supply.

4. The trigger system wake-up circuit according to claim 3, characterized in that, The first switch branch further includes a first voltage divider resistor connected between the trigger signal input terminal and the first control terminal, a first current limiting resistor connected between the first controlled input terminal and the power supply, and a first rectifier diode; The positive terminal of the first rectifier diode is connected to the junction between the first controlled input terminal and the first current-limiting resistor, and the negative terminal of the first rectifier diode is connected to the system wake-up input terminal.

5. The trigger system wake-up circuit according to claim 1, characterized in that, The second switch branch includes a second transistor, which includes a second control terminal, a second controlled input terminal, and a second controlled output terminal. The second control terminal is connected to ground, and the second controlled input terminal and the second controlled output terminal are respectively connected to the trigger signal input terminal and the system wake-up input terminal.

6. The trigger system wake-up circuit according to claim 5, characterized in that, The second switching branch further includes an energy storage circuit disposed between the second controlled input terminal and the second control terminal, the energy storage circuit including an energy storage capacitor and an energy storage resistor connected in parallel; and / or; The second switch branch also includes a second rectifier diode disposed between the trigger signal input terminal and the second controlled input terminal. The positive terminal of the second rectifier diode is connected to the end of the energy storage circuit connected to the trigger signal input terminal, and the negative terminal of the second rectifier diode is connected to the second controlled input terminal.

7. The trigger system wake-up circuit according to claim 6, characterized in that, The second switching branch further includes a second voltage divider resistor connected between the trigger signal input terminal and the positive terminal of the second rectifier diode, and a third voltage divider resistor connected between the junction of the energy storage circuit and the second control terminal and the electrode ground.

8. The trigger system wake-up circuit according to claim 1, characterized in that, The button circuit includes a button switch, and a transient voltage suppression diode and a debounce capacitor connected in parallel with the button switch.

9. The trigger system wake-up circuit according to any one of claims 1 to 8, characterized in that, It also includes multiple trigger signal input branches connected to the trigger signal input terminal, each of the trigger signal input branches including a logic OR gate connected to the multiple trigger signal sources and a buffer connected to the output terminal of the logic OR gate; And / or, It also includes a filter capacitor connected between the trigger signal input terminal and the electrode ground.

10. An electronic device, characterized in that, Includes a trigger system wake-up circuit as described in any one of claims 1 to 9.

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