Semiconductor device

Abstract

A semiconductor device includes a first conductive type semiconductor layer, a cellular region, and a source metal. The cell region is located in the first conductive type semiconductor layer and includes a plurality of cells. The cell comprises a trench gate, a second conductive type grounding shielding region, a Schottky region and a source region. The trench gate includes a trench and a gate electrode, the gate electrode includes a first extension portion and a second extension portion, the first extension portion is filled in the trench, and the second extension portion extends from the first extension portion to a position above the source region. The second conductive type grounding shielding region covers one side of the groove and at least one part of the bottom. The Schottky region is located on the side, away from the groove, of the second conductive type grounding shielding region. The source region adjoins one side of the trench away from the second conductive type grounding shielding region. The source electrode metal is electrically connected with the second conductive type grounding shielding region and the source electrode region and has Schottky contact with the Schottky region. The semiconductor device has high reliability and low switching loss.

Description

Technical Field

[0001] This application belongs to the field of integrated circuits and relates to a semiconductor device. Background Technology

[0002] Wide-bandgap semiconductor material SiC is an ideal material for fabricating high-voltage power electronic devices. Compared with Si, SiC has advantages such as high breakdown electric field strength, high saturation drift velocity, high thermal conductivity, and good thermal stability, making it suitable for manufacturing high-power electronic devices. For example, SiC vertical double-diffused metal oxide semiconductor (VDMOSFET) exhibits better frequency characteristics and switching loss performance compared to other types of power devices.

[0003] SiC VDMOS includes planar and trench types. Trench VDMOS can effectively improve the dynamic loss of the device because there is no JFET region. However, trench VDMOS is prone to electric field concentration at the bottom of the trench, which can affect the reliability of VDMOS.

[0004] Therefore, how to provide a semiconductor device that improves the reliability of semiconductor devices has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Utility Model Content

[0006] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a semiconductor device to solve the problem that the reliability of trench semiconductor devices in the prior art needs to be improved.

[0007] To achieve the above and other related objectives, this application provides a semiconductor device, comprising:

[0008] First conductivity type semiconductor layer;

[0009] A cell region, located in the first conductivity type semiconductor layer, comprises multiple cells, each cell including a trench gate, a second conductivity type ground shield region, a Schottky region, and a source region; wherein...

[0010] The trench gate includes a trench and a gate electrode. The gate electrode includes a first extension and a second extension. The first extension is filled in the trench, and the second extension extends from the first extension to above the source region.

[0011] The second conductivity type grounding shielding area covers one side of the trench and at least a portion of the bottom of the trench;

[0012] The Schottky region is located on the side of the second conductivity type grounding shield area away from the trench;

[0013] The source region is adjacent to the side of the trench away from the second conductivity type contact region;

[0014] The source metal is located above the first conductivity type semiconductor layer. The source metal is electrically connected to both the second conductivity type ground shield region and the source region, and the source metal has a Schottky contact with the Schottky region.

[0015] Optionally, there is a distance between the source region and the second conductivity type grounding shield region between any two adjacent trenches, and the Schottky region is located between the source region and the second conductivity type grounding shield region.

[0016] Optionally, the source region includes a second conductivity type well region and a first conductivity type source region, both of which are adjacent to the trench, and the first conductivity type source region is located in the second conductivity type well region.

[0017] Optionally, the first conductivity type source region includes a first extension region and a plurality of second extension regions connected together. The first extension region extends along the length direction of the trench, and the second extension regions extend along the width direction of the trench. The source metal is electrically connected to the first extension region.

[0018] Optionally, a first channel forming region is formed based on a portion of the second conductivity type well region located outside the first extension region, and a second channel forming region is formed based on the region of the second conductivity type well region adjacent to the trench.

[0019] Optionally, the distance between the second extension and the side of the trench adjacent to the second conductivity type grounding shield is less than the distance between the first extension and the side of the trench adjacent to the second conductivity type grounding shield.

[0020] Optionally, the second conductivity type grounding shield area includes a shield area and a grounding area, the shield area being connected to the grounding area, the shield area covering at least a portion of the bottom of the trench, and the grounding area covering one side of the trench.

[0021] Optionally, the ratio between the thickness of the shielding area and the depth of the trench is in the range of 1 / 30 to 1 / 3.

[0022] Optionally, the ratio between the width of the contact area and the width of the trench is in the range of 1 / 10 to 1.

[0023] Optionally, the source region further includes a plurality of second conductivity type contact regions, the second conductivity type contact regions being located on the upper surface of the second conductivity type well region, and two second conductivity type contact regions being arranged on both sides of the second extension region in the first direction, the source metal being electrically connected to the second conductivity type contact regions.

[0024] As described above, the semiconductor device of this application provides a second conductivity type ground shielding region within the cell of the semiconductor device. This second conductivity type ground shielding region covers one side and at least a portion of the bottom of the trench in the trench gate, and is electrically connected to the source metal for grounding. This provides excellent electric field protection for the trench gate, contributing to high reliability of the semiconductor device. Furthermore, the structure of the first conductivity type semiconductor layer located on the side of the second conductivity type ground shielding region away from the trench constitutes a Schottky region, and the source metal has a Schottky contact with the Schottky region. This allows for the integration of a Schottky diode within the cell structure of the semiconductor device, achieving a replacement optimization for the low-performance body diode of the semiconductor device, reducing the turn-on voltage of the device's body diode, and lowering the switching losses of the semiconductor device. Furthermore, by designing the structure of the source region within the cell, the source region includes a first extension region and multiple second extension regions. Based on the second channel forming region formed in the second conductivity type well region, a first channel forming region is added to simultaneously provide both horizontal and vertical channels under operating conditions. This compensates for the channel density loss due to the second conductive grounding shield region, ensuring the device's current carrying capacity. Additionally, based on the above structural design of the source region, the contact area between the source metal and the Schottky region is further increased, enhancing the device's current output capability. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0026] Figure 2 for Figure 1 A partial perspective view of the structure shown;

[0027] Figure 3 for Figure 1 A schematic diagram of the cross-sectional structure of the A-A' section;

[0028] Figure 4 for Figure 1A schematic diagram of the cross-sectional structure of the B-B' section;

[0029] Figure 5 for Figure 1 A schematic diagram of the cross-sectional structure of the C-C' section;

[0030] Figure 6 This is a schematic diagram of the structure of the semiconductor device provided in the embodiments of this application before the gate dielectric is formed.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10- Semiconductor layer of first conductivity type, 101- Schottky region, 11- Substrate, 12- Buffer layer, 13- Drift layer;

[0033] 20-Trench gate, 21-Trench, 22-Gate electrode, 22a-First extension, 22b-Second extension, 23-Gate dielectric;

[0034] 30 - Second conductivity type grounding shielding area; 31 - Shielding area; 32 - Grounding area;

[0035] 40 - Source region, 41 - Second conductivity type well region, 42 - First conductivity type source region, 42a - First extension region, 42b - Second extension region, 43 - Second conductivity type contact region;

[0036] 50 - Source metal; 60 - Isolation dielectric layer; 70 - Drain metal; I - Region. Detailed Implementation

[0037] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0038] Please see Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0039] Besides the issue of high dynamic losses due to the high density of the JFET region, planar SiC VDMOS also suffers from excessively high on-state voltage drop of the parasitic body diode. Since the parasitic body diode is a bipolar device, it exhibits a large reverse recovery current, and the on-state voltage drop continuously increases due to bipolar degradation. Furthermore, the presence of base plane dislocations (BDPs) common in SiC material affects the reverse recovery characteristic mode of the device. Therefore, the body diode of SiC VDMOS is unsuitable as a reverse recovery diode; this problem also exists in trench SiC VDMOS.

[0040] To address the issues of high turn-on voltage and bipolar degradation in body diodes, Schottky barrier diodes (SBDs) can be integrated into the cells of SiC VDMOS devices. This leverages the advantages of SBDs, such as low turn-on voltage and the absence of bipolar degradation, to improve device performance. For example, the source-well region within the cell can be disconnected to reserve space for SBD integration. However, to obtain an SBD with good current-carrying capacity, the area between the source and well regions needs to have a certain width, which increases the cell size and consequently the overall size of the SiC VDMOS device, hindering practical applications.

[0041] This application provides a semiconductor device; please refer to [link / reference]. Figure 1 and Figure 2 ,in, Figure 1 A schematic diagram of the semiconductor device is shown. Figure 2 It shows Figure 1 A partial perspective view of the structure shown (the source metal is represented by a dashed box). This semiconductor device includes a first conductivity type semiconductor layer 10 (not labeled, please refer to [reference needed]). Figures 3 to 5 ), cell region and source metal 50 (unmarked, please refer to relevant documentation). Figures 3 to 5 ).

[0042] Specifically, please refer to the following: Figures 3 to 5 ,in, Figure 3 It shows Figure 2 A cross-sectional view of the A-A' section. Figure 4 It shows Figure 2 A cross-sectional view of the B-B' section. Figure 5 It shows Figure 2A cross-sectional view of the C-C' region. The cell region is located in the first conductivity type semiconductor layer 10. The cell region includes multiple cells (not labeled), each cell including a trench gate 20, a second conductivity type ground shielding region 30, a Schottky region 101, and a source region 40. The trench gate 20 includes a trench 21 and a gate electrode 22. The gate electrode 22 includes a first extension 22a and a second extension 22b. The first extension 22a fills the trench 21. The second extension 22b extends from the first extension 22a to above the source region 40. The second conductivity type ground shielding region 30 covers one side of the trench 21 and at least a portion of the bottom of the trench 21. The Schottky region 101 is located on the side of the second conductivity type ground shielding region 30 away from the trench 21. The source region 40 is adjacent to the side of the trench 21 away from the second conductivity type contact region 43.

[0043] Specifically, the source metal 50 is located above the first conductivity type semiconductor layer 10. The source metal 50 is electrically connected to both the second conductivity type ground shield region 30 and the source region 40. Furthermore, the source metal 50 has a Schottky contact with the Schottky region 101. The source metal 50 and the second conductivity type ground shield region 30 serve to electrically lead out and ground the second conductivity type ground shield region 30. The Schottky contact between the source metal 50 and the Schottky region 101 allows for the bulk integration of a Schottky diode within the semiconductor device.

[0044] It should be noted that, since multiple cells are connected in parallel in the semiconductor device, the boundaries between these cells are not entirely clear. For example, the cells can be divided based on the edge of the second conductivity type ground shielding region 30 away from the trench 21. In this case, the Schottky region 101 is located on the side of the trench 21 away from the second conductivity type ground shielding region 30. Alternatively, the cells can also be divided based on the edge of the trench gate 20 away from the second conductivity type ground shielding region 30. In this case, the Schottky region 101 is located on the side of the second conductivity type ground shielding region 30 away from the trench 21. This embodiment uses this dividing boundary as an example.

[0045] In this embodiment, any cell in the semiconductor device includes a second conductivity type ground shielding region 30 and a Schottky region 101. On one hand, the second conductivity type ground shielding region 30 reduces the electric field strength at the bottom of the trench gate 20, effectively protecting the trench gate 20 and increasing the withstand voltage performance and reliability of the semiconductor device. On the other hand, the Schottky region 101 integrates a Schottky diode in the semiconductor device, reducing the turn-on voltage of the body diode, lowering the turn-on loss of the semiconductor device, and improving its operating performance.

[0046] In an optional embodiment, there is a distance between the source region 40 and the second conductivity type ground shield region 30 between any two adjacent trenches 21, and the Schottky region 101 is located between the source region 40 and the second conductivity type ground shield region 30.

[0047] In this embodiment of the application, any two adjacent trenches 21 include a local structure of an undoped first conductivity type semiconductor layer 10, and the local structure is located between the source region 40 and the second conductivity type ground shield region 30, and the Schottky region 101 is formed based on the local structure.

[0048] In an optional embodiment, the source region 40 includes a second conductivity type well region 41 and a first conductivity type source region 42, both of which are adjacent to the trench 21, and the first conductivity type source region 42 is located in the second conductivity type well region 41.

[0049] Furthermore, for a clearer description of the structure of the source region 40, please refer to [link to relevant documentation]. Figure 6 , Figure 6 This diagram illustrates the structure of the semiconductor device before the gate dielectric is formed. The first conductivity type source region 42 includes a connected first extension region 42a and a plurality of second extension regions 42b. The first extension region 42a extends along the length direction of the trench 21. The second extension regions 42b extend along the width direction of the trench 21. Figure 1 and Figure 2 As shown, the source metal 50 is electrically connected to the first extension region 42a. It is readily understood that the length direction of the trench 21 is perpendicular to the width direction of the trench 21.

[0050] It should be noted that the source metal 50 described in this embodiment is a one-piece structure. To achieve Schottky contact between the source metal 50 and the Schottky region 101 to form a Schottky diode, the source metal 50 needs to be a metal material with a work function higher than that of the Schottky region 101, such as Ni or Ti. In other embodiments, the source metal 50 can be a separate connected structure. For example, the source metal 50 may include a first metal portion (not shown) and a second metal portion (not shown). The first metal portion directly contacts the Schottky region 101, and the second metal portion directly contacts the first extension region 42a. The second metal portion also covers or connects to the first metal portion to form the source metal 50. In this case, although the manufacturing steps of the source metal 50 are increased compared to a one-piece structure, different metal materials can be selected according to the nature or function of the area to be contacted, and the source metal 50 can be constructed accordingly. For example, a metal material (e.g., Al) that can form a good ohmic contact with the first extension region 42a can be selected as the second metal part, thereby reducing the contact resistance and improving the device's conductivity.

[0051] In optional embodiments, such as Figure 3 As shown, a portion of the second conductivity type well region 41 located outside the first extension region 42a constitutes a first channel forming region (not shown), and the region of the second conductivity type well region 41 adjacent to the trench 21 constitutes a second channel forming region (not shown). The first channel forming region is a horizontal channel forming region, and the second channel forming region is a vertical channel forming region.

[0052] In this embodiment, the first conductivity type source region 42 is structurally configured such that it includes a first extension region 42a and a plurality of second extension regions 42b, with the plurality of second extension regions 42b spaced apart along the length of the trench 21. This results in a horizontal channel that is spaced apart along with the arrangement of the second extension portions 22b. Such a layout design effectively increases the contact area between the source metal 50 and the Schottky region 101, thereby increasing the current conduction capability of the Schottky diode and improving the current output capability of the semiconductor device.

[0053] In this embodiment, the semiconductor device cell has a second conductivity type ground shielding region 30, which improves the device's withstand voltage performance and reliability. However, since the second conductivity type ground shielding region 30 covers one side of the trench 21, it sacrifices the second channel formation region formed on the sidewall of the trench 21, which will increase the device's on-resistance to some extent. In this embodiment, based on the structure of the first conductivity type source region 42 (including the first extension region 42a and the second extension region 42b), the structure of the trench gate 20 is adjusted so that the gate dielectric 23 covers a portion of the surface of the first extension region 42a, and the portion of the second conductivity type well region 41 located around the first extension region 42a forms the first channel formation region. When the gate voltage is greater than the threshold voltage, an inversion layer is formed on the side of the first channel formation region close to the gate dielectric 23, thereby forming the first channel (the first channel is a horizontal channel). The formation of the first channel helps to increase the channel density of the semiconductor device, thereby compensating for the reduced device conductivity caused by the setting of the second conductivity type ground shielding area 30, and achieving high reliability of the semiconductor device without significantly affecting its operating performance.

[0054] In an optional embodiment, the doping concentration of the second channel forming region is the same as that of the first channel forming region to ensure the consistency of the activation of horizontal and vertical channels in the cell, thereby ensuring the operational stability of the semiconductor device. The doping concentrations of the second channel forming region and the first channel forming region are not higher than the doping concentrations of other regions in the second conductivity type well region 41, which facilitates inversion to form the channel.

[0055] In an optional embodiment, the doping concentration range of the first channel formation region is 5e16 cm⁻¹. -3 ~2e17cm -3 (Including endpoint values), the doping concentration range of the second channel formation region is 5e16 cm⁻¹. -3 ~2e17cm -3 (Including endpoint values). For example, the first channel forming region can be 8e16 cm. -3 or 1e17 cm -3 Furthermore, the doping concentration in the second channel formation region can be 8e16 cm⁻¹. -3 or 1e17 cm -3 .

[0056] In an optional embodiment, the distance between the second extension 22b and the side of the trench 21 adjacent to the second conductivity type grounding shield 30 is less than the distance between the first extension 22a and the side of the trench 21 adjacent to the second conductivity type grounding shield 30. That is, a portion of the surface of the first extension 22a is not covered by the second extension 22b.

[0057] In this embodiment, based on the structure of the gate electrode 22, the first extension 22a is designed not to be completely covered by the second extension 22b, so that there is a notch on the side of the gate electrode 22 near the second conductivity type grounding shielding area 30 (e.g., Figure 3 (The area shown in the dashed box I). Thus, while the isolation dielectric layer 60 (see below) completely covers the trench gate 20, it avoids the isolation dielectric layer 60 covering the surface of the second conductivity type grounding shield area 30 located on one side of the trench 21. This allows the subsequently formed source metal 50 to have good contact with the second conductivity type grounding shield area 30, ensuring that the second conductivity type grounding shield area 30 can be properly grounded.

[0058] In an optional embodiment, the second conductivity type grounding shielding area 30 includes a shielding area 31 and a grounding area 32. The shielding area 31 is connected to the grounding area 32. The shielding area 31 covers at least a portion of the bottom of the trench 21, and the grounding area 32 covers one side of the trench 21. For example, the shielding area 31 completely covers the bottom of the trench 21 to achieve all-around protection of the bottom of the trench 21. The grounding area 32 covers one side of the trench 21.

[0059] In this embodiment, for the second conductivity type grounding shielding region 30, the shielding region 31 is mainly used to reduce the electric field concentration at the bottom of the trench gate 20, and the grounding region 32 is mainly used to ground the shielding region 31. Based on this, while satisfying the grounding effect of the shielding region 31, the width of the grounding region 32 can be relatively small; for example, the width of the grounding region 32 is smaller than the width of the second conductivity type well region 41. Compared with the cell structure in related technologies where well regions are spaced apart to reserve areas for integrated Schottky diodes, in this embodiment, because the width of the grounding region 32 is smaller, correspondingly, the width of the Schottky region 101 between any two adjacent trenches 21—between the second conductivity type grounding shielding region 30 and the source region 40—can be set relatively wide. This improves the performance of the Schottky diode without additionally increasing the cell area or the overall area of ​​the semiconductor device, making it suitable for practical miniaturization applications.

[0060] In optional embodiments, such as Figure 3As shown, the ratio between the thickness a of the shielding area 31 and the depth b of the trench 21 ranges from 1 / 30 to 1 / 3 (including the endpoint values). For example, the ratio between the thickness a of the shielding area 31 and the depth b of the trench 21 can be 1 / 15 or 1 / 5.

[0061] In optional embodiments, such as Figure 3 As shown, the ratio between the width c of the contact area 32 and the width d of the groove 21 ranges from 1 / 10 to 1 (including the endpoint value). For example, the ratio between the width c of the contact area 32 and the width d of the groove 21 can be 3 / 10 or 3 / 5.

[0062] In optional embodiments, such as Figure 3 As shown, the depth b of the trench 21 ranges from 1.5 μm to 3 μm (inclusive of endpoints). For example, the depth b of the trench 21 can be 1.8 μm, 2.2 μm, or 2.6 μm. The width d of the trench 21 ranges from 0.3 μm to 1 μm (inclusive of endpoints). For example, the width d of the trench 21 can be 0.5 μm or 0.8 μm. The depth c and width a of the trench 21 are selected and adjusted based on the application scenario and cell size of the semiconductor device. In this document, "depth" refers to the dimension in the direction from the source metal 50 to the first conductivity type semiconductor layer 10 (i.e., the height direction of the cell), and "width" refers to the dimension perpendicular to the arrangement direction of the plurality of cells (i.e., the width direction of the cell).

[0063] In optional embodiments, such as Figure 3 As shown, the thickness 'a' (or doping depth) of the shielding region 31 ranges from 0.1 μm to 0.5 μm (inclusive). For example, the thickness 'a' of the shielding region 31 can be 0.2 μm or 0.4 μm. The width 'c' of the grounding region 32 ranges from 0.1 μm to 0.3 μm (inclusive). For example, the width 'c' of the grounding region 32 can be 0.15 μm or 0.25 μm. The thickness 'a' of the shielding region 31 can be adjusted according to actual needs, provided that the second conductivity type grounding shielding region 30 can achieve the electric field protection effect of the trench gate 20. The width 'c' of the grounding region 32 needs to ensure that the grounding region 32 has a sufficiently large area to make good contact with the source metal 50 in order to achieve the grounding effect of the second conductivity type grounding shielding region 30. The width 'c' of the grounding region 32 also needs to be minimized as much as possible to avoid occupying too much effective cell area.

[0064] In optional embodiments, such as Figure 2 and Figure 3As shown, the source region 40 further includes a plurality of second conductivity type contact regions 43. The second conductivity type contact regions 43 are located on the upper surface of the second conductivity type well region 41, and two second conductivity type contact regions 43 are arranged on both sides of the second extension region 42b in the first direction. The source metal 50 is electrically connected to the second conductivity type contact regions 43.

[0065] In an optional embodiment, the second conductive type contact area 43 and the grounding area 32 in the second conductive type grounding shield area 30 are formed in the same step, which helps to simplify the process steps.

[0066] In optional embodiments, such as Figures 3 to 5 As shown, the trench gate 20 further includes a gate dielectric 23, which covers the inner wall of the trench 21 and a portion of the surface of the source region 40. The gate electrode 22 is located above the gate dielectric 23. The gate dielectric 23 is made of silicon oxide, and the gate electrode 22 is made of polycrystalline silicon.

[0067] In optional embodiments, such as Figures 3 to 5 As shown, the semiconductor device further includes an isolation dielectric layer 60, which covers the trench gate 20 (covering the exposed surface in the trench gate 20 structure), and the source metal 50 is embedded in the isolation dielectric layer 60 to connect with the first extension region 42a, the Schottky region 101 and the second conductivity type ground shield region 30 in the first conductivity type semiconductor layer 10.

[0068] In an optional embodiment, along the direction from the first conductivity type semiconductor layer 10 to the source metal 50, the semiconductor layer includes a substrate 11, a buffer layer 12, and a drift layer 13 stacked sequentially, with the cell region located on the side of the drift layer 13 away from the buffer layer 12. The substrate 11, the buffer layer 12, and the drift layer 13 are all first conductivity type semiconductor layers 10. The doping concentration of the buffer layer 12 is between the doping concentration of the substrate 11 and the doping concentration of the drift layer 13. The material of the first conductivity type semiconductor layer 10 includes silicon carbide and other suitable semiconductor materials.

[0069] In an optional embodiment, the semiconductor device further includes a drain metal 70 located on the side of the substrate 11 away from the buffer layer 12.

[0070] In an optional embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Alternatively, the first conductivity type is P-type and the second conductivity type is N-type. In this embodiment, the example is given with the first conductivity type being N-type and the second conductivity type being P-type. That is, in this embodiment, the semiconductor device is an N-type device, which includes an N-type epitaxial layer, a P-type well region, an N-type source region, a P-type ground shield region, and a P-type contact region.

[0071] In this embodiment, a second conductivity type ground shielding region is provided in the cell region. This second conductivity type ground shielding region covers one side and at least a portion of the bottom of the trench in the trench gate, and is electrically connected to the source metal. This provides good electric field protection for the trench gate, contributing to high reliability of the semiconductor device. Furthermore, a Schottky region is formed based on the structure of the first conductivity type semiconductor layer located on the side of the second conductivity type ground shielding region away from the trench. The source metal has a Schottky contact with the Schottky region, allowing the integration of a Schottky diode within the cell structure of the semiconductor device. This achieves a replacement optimization for the low-performance body diode of the semiconductor device, reducing the turn-on voltage of the body diode and lowering the switching losses of the semiconductor device. Further, the structure of the source region in the cell is designed such that the source region includes a first extension region and multiple second extension regions. Based on the second channel forming region formed in the second conductivity type well region, a first channel forming region is added to simultaneously provide horizontal and vertical channels under operating conditions. This compensates for the channel density loss caused by the second conductive grounding shield region, ensuring the device's current carrying capacity. Furthermore, based on the above structural design of the source region, the contact area between the source metal and the Schottky region is further increased, enhancing the device's current output capability.

[0072] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A semiconductor device, characterized in that, include: First conductivity type semiconductor layer; A cell region, located in the first conductivity type semiconductor layer, comprises multiple cells, each cell including a trench gate, a second conductivity type ground shield region, a Schottky region, and a source region; wherein... The trench gate includes a trench and a gate electrode. The gate electrode includes a first extension and a second extension. The first extension is filled in the trench, and the second extension extends from the first extension to above the source region. The second conductivity type grounding shielding area covers one side of the trench and at least a portion of the bottom of the trench; The Schottky region is located on the side of the second conductivity type grounding shield area away from the trench; The source region is adjacent to the side of the trench that is away from the grounding shield region of the second conductivity type; The source metal is located above the first conductivity type semiconductor layer. The source metal is electrically connected to both the second conductivity type ground shield region and the source region, and the source metal has a Schottky contact with the Schottky region.

2. The semiconductor device according to claim 1, characterized in that: There is a distance between the source region and the second conductivity type grounding shield region between any two adjacent trenches, and the Schottky region is located between the source region and the second conductivity type grounding shield region.

3. The semiconductor device according to claim 1, characterized in that: The source region includes a second conductivity type well region and a first conductivity type source region. Both the second conductivity type well region and the first conductivity type source region are adjacent to the trench, and the first conductivity type source region is located in the second conductivity type well region.

4. The semiconductor device according to claim 3, characterized in that: The first conductivity type source region includes a first extension region and a plurality of second extension regions connected together. The first extension region extends along the length direction of the trench, and the second extension regions extend along the width direction of the trench. The source metal is electrically connected to the first extension region.

5. The semiconductor device according to claim 4, characterized in that: The first channel forming region is formed by a portion of the second conductivity type well region located outside the first extension region, and the second channel forming region is formed by the region of the second conductivity type well region adjacent to the trench.

6. The semiconductor device according to claim 4, characterized in that: The distance between the second extension and the side of the trench adjacent to the second conductivity type grounding shield is less than the distance between the first extension and the side of the trench adjacent to the second conductivity type grounding shield.

7. The semiconductor device according to claim 1, characterized in that: The second conductivity type grounding shield area includes a shield area and a grounding area, the shield area being connected to the grounding area, the shield area covering at least a portion of the bottom of the trench, and the grounding area covering one side of the trench.

8. The semiconductor device according to claim 7, characterized in that: The ratio between the thickness of the shielding area and the depth of the trench is in the range of 1 / 30 to 1 / 3.

9. The semiconductor device according to claim 7, characterized in that: The ratio between the width of the contact area and the width of the trench is in the range of 1 / 10 to 1.

10. The semiconductor device according to claim 4, characterized in that: The source region also includes a plurality of second conductivity type contact regions, which are located on the upper surface of the second conductivity type well region. Two second conductivity type contact regions are arranged on both sides of the second extension region in the first direction. The source metal is electrically connected to the second conductivity type contact regions.

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