Semiconductor device

Abstract

The utility model discloses a semiconductor device, and relates to the technical field of semiconductors, the semiconductor device comprises a substrate, a semiconductor epitaxial layer, an electrode layer and a thermoluminescent layer, the semiconductor epitaxial layer is arranged on the substrate; the electrode layer is arranged on the side, away from the substrate, of the semiconductor epitaxial layer and comprises a source electrode, a drain electrode, a grid electrode, a grid electrode routing pad and a drain electrode routing pad; and the thermoluminescent layer is arranged on one side, far away from the substrate, of the semiconductor epitaxial layer, at least covers the channel region, exposes the gate routing pad and the drain routing pad, and is configured to absorb heat generated by the channel region and dissipate the heat in a luminous form. Compared with the prior art, the semiconductor device provided by the embodiment of the utility model has the advantages that the thermoluminescent layer is additionally designed, and the thermoluminescent layer can be heated to emit light, so that the heat generated by the channel region can be absorbed and dissipated in a light emitting manner, the heat dissipation effect can be improved, the junction temperature of a chip can be reduced, and the efficiency of the drain electrode can be maintained.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and more specifically, to a semiconductor device. Background Technology

[0002] GaN-based RF power devices have a high electron saturation velocity, enabling them to achieve higher output power and drain efficiency compared to silicon-based and gallium arsenide-based devices, and allowing them to operate at higher ambient temperatures. However, due to the higher output power, GaN-based RF power devices also generate more heat.

[0003] Generally, improving the drain efficiency of GaN-based RF power devices helps convert DC power into AC output power as much as possible, thereby reducing heat generation. However, in some applications where there is no heat exchange with the outside environment, the heat generated by the system cannot be dissipated in time. As the temperature rises, the drain efficiency of GaN-based RF power devices decreases, resulting in more heat loss and severely affecting the reliability of GaN-based RF power devices. Utility Model Content

[0004] The purpose of this invention is to provide a semiconductor device that can improve heat dissipation, reduce chip junction temperature, and maintain drain efficiency.

[0005] The embodiments of this utility model are implemented as follows:

[0006] This utility model embodiment provides a semiconductor device, including:

[0007] Substrate;

[0008] A semiconductor epitaxial layer disposed on the substrate;

[0009] An electrode layer disposed on the side of the semiconductor epitaxial layer away from the substrate, the electrode layer including a source, a drain, a gate, a gate bonding pad and a drain bonding pad, the source, the gate and the drain being disposed sequentially on the semiconductor epitaxial layer, the semiconductor epitaxial layer between the source and the drain forming a channel region, the gate bonding pad being connected to the gate, and the drain bonding pad being connected to the drain;

[0010] A thermoluminescent layer disposed on the side of the semiconductor epitaxial layer away from the substrate, the thermoluminescent layer at least covers the channel region and exposes the gate bonding pad and the drain bonding pad, and is configured to absorb the heat generated in the channel region and dissipate it in the form of light emission.

[0011] In an optional embodiment, the semiconductor device further includes a dielectric layer disposed on the semiconductor epitaxial layer, the dielectric layer covering the source, the drain and the gate, and exposing the gate bonding pad and the drain bonding pad, and the thermoluminescent layer disposed on the dielectric layer.

[0012] In an optional embodiment, the dielectric layer is provided with a first gate window exposing the gate bonding pad and a first drain window exposing the drain bonding pad. The thermoluminescent layer covers the dielectric layer and is provided with a second gate window exposing the gate bonding pad and a second drain window exposing the drain bonding pad. The second gate window corresponds to and overlaps with the first gate window in the center, and the second drain window corresponds to and overlaps with the first drain window in the center.

[0013] In an optional implementation, the size of the first drain window is smaller than the size of the corresponding second drain window; the size of the first gate window is smaller than the size of the corresponding second gate window.

[0014] In an optional embodiment, the first drain window corresponds to and overlaps with the drain bonding pad at the center, and the size of the first drain window is smaller than the size of the drain bonding pad; the first gate window corresponds to and overlaps with the gate bonding pad at the center, and the size of the first gate window is smaller than the size of the gate bonding pad.

[0015] In an optional embodiment, the thermoluminescent layer covers the central region of the dielectric layer, and the projection of the thermoluminescent layer onto the semiconductor epitaxial layer overlaps with the channel region.

[0016] In an optional embodiment, a light-shielding layer is further disposed on the dielectric layer, the projection of the light-shielding layer on the semiconductor epitaxial layer is located within the channel region, the thermoluminescent layer covers the light-shielding layer, and the light-shielding layer is configured to block the channel region.

[0017] In an optional embodiment, a heat-absorbing layer or a heat-conducting layer is further disposed on the dielectric layer, the projection of the heat-absorbing layer or the heat-conducting layer on the semiconductor epitaxial layer being at least partially located within the channel region, the thermoluminescent layer covering the heat-absorbing layer or the heat-conducting layer, the heat-absorbing layer being configured to absorb and store the heat generated in the channel region, and the heat-conducting layer being configured to conduct the heat generated in the channel region to the thermoluminescent layer.

[0018] In an optional embodiment, a plurality of etched trenches are provided on the surface of the heat-absorbing layer or the heat-conducting layer away from the substrate, and the thermoluminescent layer fills the etched trenches.

[0019] In an optional embodiment, a heat-absorbing layer is further disposed on the dielectric layer, the projection of the heat-absorbing layer on the semiconductor epitaxial layer being at least partially located within the channel region, the thermoluminescent layer and the heat-absorbing layer being arranged at intervals, and the heat-absorbing layer being configured to absorb and store the heat generated in the channel region.

[0020] The beneficial effects of this utility model embodiment are:

[0021] The semiconductor device provided by this invention comprises a semiconductor epitaxial layer and an electrode layer sequentially disposed on a substrate. The source, drain, gate, gate bonding pad, and drain bonding pad of the electrode layer are all disposed on the semiconductor epitaxial layer. The gate bonding pad is connected to the gate, and the drain bonding pad is connected to the drain, facilitating external interconnection. Furthermore, a thermoluminescent layer is disposed on the side of the semiconductor layer away from the substrate. The thermoluminescent layer at least covers the channel region and exposes the gate bonding pad and drain bonding pad. This layer can absorb heat generated in the channel region and dissipate it in the form of light emission, achieving heat dissipation. Compared to the prior art, the semiconductor device provided by this invention, through the additional design of the thermoluminescent layer, can emit light when heated, thereby absorbing heat generated in the channel region and dissipating it in the form of light emission. This improves heat dissipation, reduces chip junction temperature, and maintains drain efficiency. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this utility model and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of a first type of semiconductor device provided in an embodiment of this utility model;

[0024] Figure 2 for Figure 1 Schematic diagram of the cross section at point AA;

[0025] Figure 3 for Figure 1 Schematic diagram of the cross section at point BB;

[0026] Figure 4 This is a schematic diagram of the structure of a second semiconductor device provided in an embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the structure of a third semiconductor device provided in an embodiment of the present invention;

[0028] Figure 6 for Figure 5A magnified view of a section at point VI;

[0029] Figure 7 This is a schematic diagram of the structure of a fourth semiconductor device provided in an embodiment of the present invention.

[0030] icon:

[0031] 100 - Semiconductor device; 110 - Substrate; 111 - Grounding via; 112 - Metal plating; 120 - Semiconductor epitaxial layer; 121 - Channel region; 130 - Electrode layer; 131 - Source; 132 - Drain; 133 - Gate; 134 - Gate bonding pad; 135 - Drain bonding pad; 140 - Thermoluminescent layer; 141 - Second gate window; 143 - Second drain window; 150 - Dielectric layer; 151 - First gate window; 153 - First drain window; 160 - Light-shielding layer; 170 - Heat-absorbing layer; 171 - Etched trench; 180 - Thermally conductive layer. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0034] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0035] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this utility model is in use. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model. In addition, the terms "first," "second," and "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0036] Furthermore, terms such as "horizontal" and "vertical" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0037] In the description of this utility model, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0038] As disclosed in the background section, existing technologies address chip heat dissipation by improving the drain efficiency of GaN-based RF power devices to convert DC power into AC output power as much as possible, thereby reducing heat generation. However, in some applications with poor heat dissipation (thermal insulation), the heat generated by the system cannot be dissipated to the outside in a timely manner. As the temperature rises, the drain efficiency of GaN-based RF power devices decreases, resulting in more heat loss and severely affecting the reliability of GaN-based RF power devices.

[0039] Furthermore, to address the drain efficiency issue, existing technologies employ external matching circuits to phase-shift the current and voltage waveforms, minimizing current when voltage is high and vice versa, thereby reducing DC power consumption and improving drain efficiency. However, this method uses circuit-level matching, resulting in a large circuit footprint. While theoretically achieving 100% efficiency is achievable, it is unrealistic for practical devices, and most applications are low-power pulse devices, rarely used in continuous wave applications.

[0040] Furthermore, to address the drain efficiency issue, existing technologies also control the second harmonic of each gate finger on the chip by matching it, thereby reducing the chip's DC power consumption and improving the device's drain efficiency. However, this method requires adding long metal lines to the chip, resulting in significant waste of chip area and poor second harmonic control. It is only suitable for narrow bandwidth applications, with each chip designed for a specific application.

[0041] Therefore, the better solution to the problem of decreased drain efficiency after temperature rise is to improve chip heat dissipation. However, current heat dissipation solutions for chips usually only involve adding thermally conductive materials. However, heat will still accumulate, so existing heat dissipation solutions cannot meet the heat dissipation requirements of chips.

[0042] In view of this, the present invention provides a novel semiconductor device, the structure and working principle of which will be described in detail below.

[0043] See Figures 1 to 3 The semiconductor device 100 provided in this embodiment of the present invention can improve heat dissipation, reduce chip junction temperature, meet the heat dissipation requirements of the chip, and maintain the efficiency of the drain 132.

[0044] The semiconductor device 100 provided in this embodiment includes a substrate 110, a semiconductor epitaxial layer 120, an electrode layer 130, and a thermoluminescent layer 140. The semiconductor epitaxial layer 120 is disposed on the substrate 110. The electrode layer 130 is disposed on the side of the semiconductor epitaxial layer 120 away from the substrate 110. The electrode layer 130 includes a source 131, a drain 132, a gate 133, a gate bonding pad 134, and a drain bonding pad 135. The source 131, gate 133, and drain 132 are sequentially disposed on a half-side of the substrate 110. On the conductor epitaxial layer 120, a channel region 121 is formed between the source 131 and the drain 132. The gate bonding pad 134 is connected to the gate 133, and the drain bonding pad 135 is connected to the drain 132. The thermoluminescent layer 140 is disposed on the side of the semiconductor epitaxial layer 120 away from the substrate 110. The thermoluminescent layer at least covers the channel region 121 and exposes the gate bonding pad 134 and the drain bonding pad 135. It is configured to absorb the heat generated in the channel region 121 and dissipate it in the form of light emission.

[0045] It should be noted that the semiconductor device 100 mentioned in this embodiment refers to an RF power device / chip. The thermoluminescent layer 140 is formed using thermoluminescent materials, such as lithium fluoride (LiF) doped with magnesium and copper (Mg, Cu), aluminum oxide (AlO) doped with carbon (C) or chromium (Cr), calcium sulfide oxide (CaSO) doped with dysprosium (Dy), calcium fluoride (CaF) doped with europium (Eu), etc. The substrate 110 can be a SiC substrate 110, and the semiconductor epitaxial layer 120 can be an AlGaN / GaN epitaxial layer. SiC has high thermal conductivity, which can conduct the heat of the channel region 121 to the packaging substrate, improving the heat dissipation effect. At the same time, the 2DEG generated by AlGaN / GaN epitaxy has high electron mobility and electron saturation velocity, and the chip fabricated based on this can achieve higher drain efficiency 132.

[0046] A thermoluminescent material is coated on the semiconductor epitaxial layer 120. During device operation, heat is generated in the channel region 121. The thermoluminescent material itself stores some of this heat and dissipates it as light. This embodiment of the invention, by additionally providing a thermoluminescent layer 140, converts some of the heat originally isolated internally into other forms of energy (light energy) for dissipation. Therefore, the temperature of the channel region 121 can be significantly reduced, maintaining the drain efficiency 132 and improving reliability. Similarly, in other preferred embodiments of the invention, by providing different structures, some of the internal heat can also be converted into other forms of energy, such as mechanical energy, electrical energy, and acoustic energy.

[0047] It should also be noted that, in this embodiment, the thermoluminescent material absorbs heat and emits light. Therefore, the photons generated by the thermoluminescent material can help the charge carriers in the channel region 121 overcome the energy barrier of the trapped state (detrapping) and improve the overall linearity of the device.

[0048] Furthermore, the semiconductor device 100 also includes a dielectric layer 150 disposed on the semiconductor epitaxial layer 120. The dielectric layer 150 covers the source 131, drain 132, and gate 133, and exposes the gate bonding pad 134 and drain bonding pad 135. A thermoluminescent layer 140 is disposed on the dielectric layer 150. Specifically, the dielectric layer 150 can be an inorganic dielectric layer 150 or an organic dielectric layer 150. The inorganic dielectric layer 150 can be at least one of SiN and SiO2, and the organic dielectric layer 150 can be polyimide. In the actual fabrication of the dielectric layer 150, a dielectric material can be deposited on the surface of the semiconductor epitaxial layer 120 first, so that the dielectric layer 150 can cover and protect the source 131, drain 132, and gate 133. Then, the dielectric layer 150 is etched into the area of ​​the gate bonding pad 134 and drain bonding pad 135 to expose the gate bonding pad 134 and drain bonding pad 135, which facilitates subsequent packaging and wire bonding.

[0049] In some embodiments, a first gate window 151 exposing the gate bonding pad 134 and a first drain window 153 exposing the drain bonding pad 135 are provided on the dielectric layer 150. A thermoluminescent layer 140 covers the dielectric layer 150 and is provided with a second gate window 141 exposing the gate bonding pad 134 and a second drain window 143 exposing the drain bonding pad 135. The second gate window 141 corresponds to and overlaps with the first gate window 151 in the center, and the second drain window 143 corresponds to and overlaps with the first drain window 153 in the center. Specifically, when actually fabricating the dielectric layer 150, the first gate window 151 and the first drain window 153 can be formed on the dielectric layer 150 by etching. Similarly, when fabricating the thermoluminescent layer 140, the second gate window 141 can also be formed by etching. Using a mask for pattern design ensures that the centers of the first gate window 151 and the second gate window 141 overlap (i.e., the geometric centers overlap), while the centers of the first drain window 153 and the second drain window 143 also overlap.

[0050] In some embodiments, the size of the first drain window 153 is smaller than the size of the corresponding second drain window 143; the size of the first gate window 151 is smaller than the size of the corresponding second gate window 141. Specifically, by controlling the etching range, the opening areas of the second drain window 143 and the second gate window 141 can be made larger, so as to avoid interference with the effective bonding areas of the gate bonding pad 134 and the drain bonding pad 135 as much as possible, and ensure the bonding effect.

[0051] In some embodiments, the first drain window 153 corresponds to and overlaps with the drain bonding pad 135 at the center, and the size of the first drain window 153 is smaller than the size of the drain bonding pad 135; the first gate window 151 corresponds to and overlaps with the gate bonding pad 134 at the center, and the size of the first gate window 151 is smaller than the size of the gate bonding pad 134. Specifically, the size of the first drain window 153 is slightly smaller than the size of the drain bonding pad 135, and the size of the first gate window 151 is slightly smaller than the size of the gate bonding pad 134. By etching the dielectric layer 150 and controlling the etching orientation, the dielectric layer 150 can precisely cover the edge areas of the drain bonding pad 135 and the gate bonding pad 134, thereby achieving a better protection effect and exposing the bonding pads as much as possible.

[0052] In some other preferred embodiments of this invention, the thermoluminescent layer 140 covers the central region of the dielectric layer 150, and the projection of the thermoluminescent layer 140 onto the semiconductor epitaxial layer 120 overlaps with the channel region 121. Specifically, the thermoluminescent material outside the channel region 121 can be etched away, leaving only the thermoluminescent material within the channel region 121 or the active region. The channel region 121 is the main heat-generating region, and this arrangement maximizes the utilization rate of the thermoluminescent material.

[0053] In some embodiments, a grounding via 111 is provided on the side of the substrate 110 away from the electrode layer 130. The grounding via 111 penetrates the substrate 110 and the semiconductor epitaxial layer 120 and is correspondingly bonded to the source electrode 131. A metal plating layer 112 is provided on the hole wall of the grounding via 111 and the surface of the substrate 110 away from the electrode layer 130. The metal plating layer 112 is in electrical contact with the source electrode 131.

[0054] See Figure 4 In some embodiments, a light-shielding layer 160 is further disposed on the dielectric layer 150. The projection of the light-shielding layer 160 onto the semiconductor epitaxial layer 120 covers the channel region 121, and the thermoluminescent layer 140 covers the light-shielding layer 160. The light-shielding layer 160 is configured to block the channel region 121. Specifically, in scenarios where linearity requirements are not high, or in scenarios where circuit matching has been completed, it is desirable to reduce the chip channel temperature and maintain the drain efficiency 132 without affecting the original performance of the chip. In such cases, a light-shielding layer 160 can be added above the channel region 121. The light-shielding layer 160 is a light-shielding material, such as a thin metal film or other opaque materials. The area of ​​the light-shielding layer 160 is larger than the channel region 121, which can effectively block the light emitted by the thermoluminescent layer 140 from entering the channel region 121.

[0055] See Figure 5 In some embodiments, a heat-absorbing layer 170 is further disposed on the dielectric layer 150. The projection of the heat-absorbing layer 170 onto the semiconductor epitaxial layer 120 is at least partially located within the channel region 121. A thermoluminescent layer 140 covers the heat-absorbing layer 170, which is configured to absorb and store the heat generated in the channel region 121. The heat-absorbing layer 170 can cover the entire dielectric layer 150 and can be made of a high-heat-capacity material. In actual fabrication, a high-heat-capacity material can be first coated onto the dielectric layer 150, followed by a thermoluminescent material. The high-heat-capacity material can absorb and store some of the heat generated in the channel region 121, helping to reduce the channel temperature.

[0056] See Figure 7In other preferred embodiments of this invention, a heat-absorbing layer 170 is further disposed on the dielectric layer 150. The projection of the heat-absorbing layer 170 onto the semiconductor epitaxial layer 120 is at least partially located within the channel region 121. The thermoluminescent layer 140 and the heat-absorbing layer 170 are arranged alternately, and the heat-absorbing layer 170 is configured to absorb and store the heat generated in the channel region 121. Specifically, the thermoluminescent layer 140 and the heat-absorbing layer 170 are arranged alternately on both sides, which allows the high heat capacity material and the thermoluminescent material to work separately, thereby improving the heat dissipation effect.

[0057] See Figure 6 In some embodiments, a plurality of etched trenches 171 are formed on the surface of the heat-absorbing layer 170 away from the substrate 110, and the thermoluminescent layer 140 is filled into the etched trenches 171. The etched trenches 171 can be formed on the surface of the heat-absorbing layer 170 by an etching process. The etched trenches 171 do not penetrate the heat-absorbing layer 170, and the thermoluminescent layer 140 can be filled into the etched trenches 171, which can significantly increase the contact area between the heat-absorbing layer 170 and the thermoluminescent layer 140, increase the light emission, and thus further reduce the channel temperature.

[0058] See Figure 5 In some embodiments, a thermally conductive layer 180 is further disposed on the dielectric layer 150. The projection of the thermally conductive layer 180 onto the semiconductor epitaxial layer 120 is at least partially located within the channel region 121. A thermoluminescent layer 140 covers the thermally conductive layer 180, and the thermally conductive layer 180 is configured to conduct heat generated in the channel region 121 to the thermoluminescent layer 140. The thermally conductive layer 180 can cover the entire dielectric layer 150 and is made of a high thermal conductivity material. In actual fabrication, a high thermal conductivity material can be first coated onto the dielectric layer 150, followed by the thermoluminescent material. The high thermal conductivity material can reduce thermal resistance, allowing the heat generated in the channel region 121 to be quickly transferred to the thermoluminescent material, thereby improving the response speed of the thermoluminescent material.

[0059] See Figure 6 In some embodiments, a plurality of etched trenches 171 are formed on the surface of the thermally conductive layer 180 away from the substrate 110, and the thermoluminescent layer 140 is filled into the etched trenches 171. The etched trenches 171 are formed on the surface of the heat-absorbing layer 170 by an etching process. The etched trenches 171 do not penetrate the thermally conductive layer 180, and the thermoluminescent layer 140 can fill into the etched trenches 171, which can significantly increase the contact area between the thermally conductive layer 180 and the thermoluminescent layer 140, increase the light emission, and thereby further reduce the channel temperature.

[0060] This utility model embodiment also provides a method for fabricating a semiconductor device 100, the process of which is as follows:

[0061] S1: A substrate 110 with a semiconductor epitaxial layer 120 is provided, and an electrode layer 130 is disposed on the semiconductor epitaxial layer 120.

[0062] This step can involve forming a semiconductor epitaxial layer 120 on the substrate 110 using conventional epitaxial growth processes. Preferably, an AlGaN / GaN epitaxial layer can be grown on the SiC substrate 110. The SiC substrate 110 has high thermal conductivity, which can conduct heat from the channel region 121 to the packaging substrate. The 2DEG generated by AlGaN / GaN epitaxy has high electron mobility and electron saturation velocity, and chips fabricated based on this can achieve higher drain efficiency 132.

[0063] A gate 133, a source 131, a drain 132, a gate bonding pad 134, and a drain bonding pad 135 are disposed on a semiconductor epitaxial layer 120. The electrode layer 130 is made of metal material. A channel region 121 is formed between the source 131 and the drain 132. The gate bonding pad 134 and the drain bonding pad 135 can be used for wire bonding to electrically connect the gate 133 and the drain 132 to the external package.

[0064] S2: Set up a dielectric layer 150, and open windows on the dielectric layer 150 to form a first gate window 151 and a first drain window 153.

[0065] This step involves depositing a conventional dielectric material on the surface of the semiconductor epitaxial layer 120 to form a dielectric layer 150 and protect the electrodes. Commonly used inorganic dielectrics are SiN, SiO2, or both, while commonly used organic dielectrics are polyimide. The dielectric material is etched away in the areas of the gate bonding pad 134 and the drain bonding pad 135 to form the first gate window 151 and the first drain window 153, respectively, exposing the gate bonding pad 134 and the drain bonding pad 135 areas to facilitate subsequent packaging wire bonding. The etching area is smaller than the areas of the gate bonding pad 134 and the drain bonding pad 135.

[0066] S3: A thermoluminescent layer 140 is provided, and a second gate window 141 and a second drain window 143 are formed on the thermoluminescent layer 140.

[0067] This step involves depositing a thermoluminescent material on the dielectric layer 150 using spin coating or spray coating. After the material has cured, the thermoluminescent material in the areas of the gate bonding pad 134 and the drain bonding pad 135 is etched away, exposing the gate bonding metal pad 133 and the drain bonding pad 135 to facilitate subsequent packaging and wire bonding. The etching range is larger than that of conventional dielectric etching.

[0068] Of course, only the thermoluminescent material in the active region can be retained here.

[0069] S4: Grounding via 111 etched.

[0070] Grounding etching is performed on the back side of substrate 110. The grounding via 111 of the ISV device is directly connected to the source 131. The via wall and the back side of the chip have a metal plating layer 112, so that the source 131 can be connected to ground during packaging.

[0071] In summary, the semiconductor device 100 provided in this embodiment of the present invention has a semiconductor epitaxial layer 120 and an electrode layer 130 sequentially disposed on a substrate 110. The source 131, drain 132, gate 133, gate bonding pad 134, and drain bonding pad 135 of the electrode layer 130 are all disposed on the semiconductor epitaxial layer 120. The gate bonding pad 134 is connected to the gate 133, and the drain bonding pad 135 is connected to the drain 132, facilitating external wiring. Furthermore, a thermoluminescent layer 140 is disposed on the side of the semiconductor layer away from the substrate 110. The thermoluminescent layer 140 at least covers the channel region 121 and exposes the gate bonding pad 134 and the drain bonding pad 135, enabling it to absorb the heat generated in the channel region 121 and dissipate it in the form of light emission, thus achieving heat dissipation. Compared to the prior art, the semiconductor device 100 provided in this embodiment of the present invention has an additional thermoluminescent layer 140 designed. The thermoluminescent layer 140 can emit light when heated, thereby absorbing the heat generated in the channel region 121 and dissipating it in the form of light emission, which can improve the heat dissipation effect, reduce the chip junction temperature, and maintain the efficiency of the drain 132.

[0072] The above description is merely a preferred embodiment of this utility model and is not intended to limit the utility model. Various modifications and variations can be made to this utility model by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Substrate (110); A semiconductor epitaxial layer (120) is disposed on the substrate (110); An electrode layer (130) is disposed on the side of the semiconductor epitaxial layer (120) away from the substrate (110). The electrode layer (130) includes a source (131), a drain (132), a gate (133), a gate bonding pad (134), and a drain bonding pad (135). The source (131), the gate (133), and the drain (132) are sequentially disposed on the semiconductor epitaxial layer (120). A channel region (121) is formed in the semiconductor epitaxial layer (120) between the source (131) and the drain (132). The gate bonding pad (134) is connected to the gate (133), and the drain bonding pad (135) is connected to the drain (132). A thermoluminescent layer (140) is disposed on the side of the semiconductor epitaxial layer (120) away from the substrate (110). The thermoluminescent layer (140) at least covers the channel region (121) and exposes the gate bonding pad (134) and the drain bonding pad (135). It is configured to absorb the heat generated by the channel region (121) and dissipate it in the form of light emission.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes a dielectric layer (150) disposed on the semiconductor epitaxial layer (120), the dielectric layer (150) covering the source (131), the drain (132) and the gate (133), and exposing the gate bonding pad (134) and the drain bonding pad (135), and the thermoluminescent layer (140) disposed on the dielectric layer (150).

3. The semiconductor device according to claim 2, characterized in that, The dielectric layer (150) is provided with a first gate window (151) exposing the gate bonding pad (134) and a first drain window (153) exposing the drain bonding pad (135). The thermoluminescent layer (140) covers the dielectric layer (150) and is provided with a second gate window (141) exposing the gate bonding pad (134) and a second drain window (143) exposing the drain bonding pad (135). The second gate window (141) corresponds to the first gate window (151) and overlaps with it in the center. The second drain window (143) corresponds to the first drain window (153) and overlaps with it in the center.

4. The semiconductor device according to claim 3, characterized in that, The size of the first drain window (153) is smaller than the size of the corresponding second drain window (143); the size of the first gate window (151) is smaller than the size of the corresponding second gate window (141).

5. The semiconductor device according to claim 3, characterized in that, The first drain window (153) corresponds to and overlaps with the drain bonding pad (135) at the center, and the size of the first drain window (153) is smaller than the size of the drain bonding pad (135); the first gate window (151) corresponds to and overlaps with the gate bonding pad (134) at the center, and the size of the first gate window (151) is smaller than the size of the gate bonding pad (134).

6. The semiconductor device according to claim 2, characterized in that, The thermoluminescent layer (140) covers the central region of the dielectric layer (150), and the projection of the thermoluminescent layer (140) onto the semiconductor epitaxial layer (120) overlaps with the channel region (121).

7. The semiconductor device according to any one of claims 2-6, characterized in that, A light-shielding layer (160) is also provided on the dielectric layer (150). The projection of the light-shielding layer (160) on the semiconductor epitaxial layer (120) covers the channel region (121). The thermoluminescent layer (140) covers the light-shielding layer (160). The light-shielding layer (160) is configured to block the channel region (121).

8. The semiconductor device according to any one of claims 2-6, characterized in that, A heat-absorbing layer (170) or a heat-conducting layer (180) is further disposed on the dielectric layer (150). The projection of the heat-absorbing layer (170) or the heat-conducting layer (180) on the semiconductor epitaxial layer (120) is at least partially located within the channel region (121). The thermoluminescent layer (140) covers the heat-absorbing layer (170) or the heat-conducting layer (180). The heat-absorbing layer (170) is configured to absorb and store the heat generated in the channel region (121). The heat-conducting layer (180) is configured to conduct the heat generated in the channel region (121) to the thermoluminescent layer (140).

9. The semiconductor device according to claim 8, characterized in that, The heat-absorbing layer (170) or the heat-conducting layer (180) has a plurality of etched trenches (171) on the side surface away from the substrate (110), and the thermoluminescent layer (140) fills the etched trenches (171).

10. The semiconductor device according to any one of claims 2-6, characterized in that, A heat-absorbing layer (170) is also provided on the dielectric layer (150). The projection of the heat-absorbing layer (170) on the semiconductor epitaxial layer (120) is at least partially located within the channel region (121). The thermoluminescent layer (140) and the heat-absorbing layer (170) are arranged at intervals. The heat-absorbing layer (170) is configured to absorb and store the heat generated by the channel region (121).

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