Radio frequency switching circuit and radio frequency chip

Abstract

The utility model provides a radio frequency switch circuit and a radio frequency chip. The radio frequency switch circuit comprises a first resistor unit, a switch circuit, a second resistor unit and a bias network which are electrically connected in sequence. The first resistor unit is used for reducing voltage distribution of the switching circuit; the second resistor unit is used for reducing voltage distribution of the switching circuit; the bias network is used for rectifying the radio frequency signal received by the switching circuit into a direct current signal. Compared with the prior art, the radio frequency switch circuit provided by the utility model can control the amplitude of a radio frequency signal reaching the diode through the bias network on the basis of providing a direct current bias voltage at the body end of the MOS tube of the switch circuit, and the diode can play a role in rectifying the radio frequency signal to rectify the radio frequency signal into a direct current signal. The bias voltage of the body end of the MOS tube is further reduced, partial depletion of source and drain channels is avoided, the harmonic performance of the switch is ensured, and non-linear distortion of a radio frequency signal does not occur.

Description

Technical Field

[0001] This utility model relates to the field of communication technology, and in particular to a radio frequency switch circuit and a radio frequency chip. Background Technology

[0002] Radio frequency switches are widely used in high-power applications. Metal-oxide-semiconductor field-effect transistors (MOSFETs) generate high-order harmonics at high power, which can affect signal transmission performance and even cause signal distortion. In order to reduce the impact of switching nonlinearity on signal integrity, the body of the MOSFET needs to be properly biased.

[0003] In existing RF switching circuits, the body of the NMOS transistor is P-type doped, while the drain and source are N-type doped. Therefore, there are reverse-biased diodes at the body, source, and drain. If a high-power signal flows through one end of the switch in the off-state mode while the body is floating, the reverse-biased diodes may turn on and generate harmonics, affecting signal performance.

[0004] Therefore, there is an urgent need for a new radio frequency switch circuit and radio frequency chip to solve the above-mentioned technical problems. Utility Model Content

[0005] This invention provides an RF switch circuit and an RF chip, which aims to properly bias the body terminal of the MOS transistor in the RF switch circuit to ensure that the integrity of the signal is not affected when the switch is off.

[0006] In a first aspect, the present invention provides a radio frequency switch circuit, the radio frequency switch circuit comprising a first resistor unit, a switch circuit, a second resistor unit, and a bias network connected in sequence.

[0007] The first end of the first resistor unit is used to receive the first bias voltage, and the second end of the first resistor unit is connected to the first input terminal of the switching circuit. The first resistor unit is used to reduce the voltage distribution of the switching circuit.

[0008] The second input terminal of the switching circuit serves as the input terminal of the radio frequency switching circuit for receiving radio frequency signals, and the output terminal of the switching circuit serves as the output terminal of the radio frequency switching circuit.

[0009] The first end of the second resistor unit is used to receive the second bias voltage, the second end of the second resistor unit is connected to the third input terminal of the switching circuit, and the second resistor unit is used to reduce the voltage distribution of the switching circuit.

[0010] The bias network is used to rectify the radio frequency signal received by the switching circuit into a DC signal.

[0011] Preferably, the switching circuit includes a first MOSFET, a second MOSFET, a third MOSFET, and a fourth MOSFET;

[0012] The gates of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET together serve as the first input terminal of the switching circuit; the drain of the first MOSFET serves as the output terminal of the switching circuit; the source of the first MOSFET is connected to the drain of the second MOSFET; the source of the second MOSFET is connected to the drain of the third MOSFET; the source of the third MOSFET is connected to the drain of the fourth MOSFET; and the source of the fourth MOSFET serves as the second input terminal of the switching circuit; the body terminals of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET together serve as the third input terminal of the switching circuit.

[0013] Preferably, the first resistor unit includes a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0014] The first end of the first resistor, the first end of the second resistor, the first end of the third resistor, and the first end of the fourth resistor together serve as the first end of the first resistor unit; the second end of the first resistor, the second end of the second resistor, the second end of the third resistor, and the second end of the fourth resistor together serve as the second end of the first resistor unit.

[0015] Preferably, the second resistor unit includes a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor;

[0016] The first end of the fifth resistor, the first end of the sixth resistor, the first end of the seventh resistor, and the first end of the eighth resistor together serve as the first end of the second resistor unit; the second end of the fifth resistor, the second end of the sixth resistor, the second end of the seventh resistor, and the second end of the eighth resistor together serve as the second end of the second resistor unit.

[0017] Preferably, the bias network includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode, and an eighth diode;

[0018] The first end of the ninth resistor is connected to the second end of the fifth resistor, and the second end of the ninth resistor is connected to the anode of the first diode and the anode of the second diode, respectively; the cathodes of the first diode and the cathodes of the second diode are connected to each other and are respectively connected to the source of the second MOS transistor and the drain of the third MOS transistor.

[0019] The first end of the tenth resistor is connected to the second end of the sixth resistor, and the second end of the tenth resistor is connected to the positive terminal of the third diode and the positive terminal of the fourth diode, respectively; the negative terminal of the third diode is connected to the drain of the first MOS transistor; the negative terminal of the fourth diode is connected to the source of the third MOS transistor and the drain of the fourth MOS transistor, respectively.

[0020] The first end of the eleventh resistor is connected to the second end of the seventh resistor, and the second end of the eleventh resistor is connected to the positive terminal of the fifth diode and the positive terminal of the sixth diode. The negative terminal of the fifth diode is connected to the drain of the second MOS transistor and the source of the first MOS transistor. The negative terminal of the sixth diode is connected to the source of the fourth MOS transistor.

[0021] The first end of the twelfth resistor is connected to the second end of the eighth resistor, and the second end of the twelfth resistor is connected to the positive terminal of the seventh diode and the positive terminal of the eighth diode, respectively; the negative terminals of the seventh diode and the eighth diode are connected to each other and are respectively connected to the source of the second MOS transistor and the drain of the third MOS transistor.

[0022] Preferably, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all NMOS transistors.

[0023] Secondly, this utility model also provides a radio frequency chip, which includes a radio frequency switching circuit as described in any of the above embodiments.

[0024] Compared with the prior art, the radio frequency switch circuit proposed in this utility model includes a first resistor unit, a switch circuit, a second resistor unit, and a bias network connected in sequence. The first end of the first resistor unit is used to receive a first bias voltage, and the second end of the first resistor unit is connected to the first input terminal of the switch circuit. The first resistor unit is used to reduce the voltage distribution of the switch circuit. The second input terminal of the switch circuit serves as the input terminal of the radio frequency switch circuit and is used to receive radio frequency signals. The output terminal of the switch circuit serves as the output terminal of the radio frequency switch circuit. The first end of the second resistor unit is used to receive a second bias voltage, and the second end of the second resistor unit is connected to the third input terminal of the switch circuit. The second resistor unit is used to reduce the voltage distribution of the switch circuit. The bias network is used to rectify the radio frequency signals received by the switch circuit into DC signals. The radio frequency (RF) switch circuit proposed in this invention adds a bias network to the DC bias voltage applied to the body terminal of the MOSFET in the switching circuit. This allows control over the amplitude of the RF signal reaching the diode. The diode rectifies the RF signal into a DC signal, further reducing the bias voltage at the body terminal of the MOSFET. This prevents depletion of the source-drain channel and conduction of the parasitic reverse diode, ensuring the harmonic performance of the switch and preventing nonlinear distortion of the RF signal. Attached Figure Description

[0025] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description in conjunction with the following drawings. (Appendix)

[0026] In the picture:

[0027] Figure 1 This is a schematic diagram of the circuit structure of the radio frequency switch circuit provided in this embodiment of the utility model. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.

[0029] Example 1

[0030] Please refer to Figure 1 The present invention provides a radio frequency switch circuit 100, which includes a first resistor unit 1, a switch circuit 3, a second resistor unit 3, and a bias network 4 connected in sequence.

[0031] The first end of the first resistor unit 1 is used to receive the first bias voltage VG, and the second end of the first resistor unit 1 is connected to the first input terminal of the switching circuit 3. The first resistor unit 1 is used to reduce the voltage distribution of the switching circuit 3.

[0032] The second input terminal of the switching circuit 3 serves as the input terminal of the radio frequency switching circuit 100 for receiving radio frequency signals, and the output terminal of the switching circuit 3 serves as the output terminal of the radio frequency switching circuit 100.

[0033] The first end of the second resistor unit 3 is used to receive the second bias voltage VB, and the second end of the second resistor unit 3 is connected to the third input terminal of the switching circuit 3. The second resistor unit 3 is used to reduce the voltage distribution of the switching circuit 3.

[0034] The bias network 4 is used to rectify the radio frequency signal received by the switching circuit 3 into a DC signal.

[0035] In this embodiment of the present invention, the switching circuit 3 includes a first MOSFET M1, a second MOSFET M2, a third MOSFET M3, and a fourth MOSFET M4;

[0036] The gates of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 together serve as the first input terminal of the switching circuit 3. The drain of the first MOSFET M1 serves as the output terminal of the switching circuit 3. The source of the first MOSFET M1 is connected to the drain of the second MOSFET M2, the source of the second MOSFET M2 is connected to the drain of the third MOSFET M3, and the source of the third MOSFET M3 is connected to the drain of the fourth MOSFET M4. The source of the fourth MOSFET M4 serves as the second input terminal of the switching circuit 3. The body terminals of the first MOSFET M1, the second MOSFET M2, the third MOSFET M3, and the fourth MOSFET M4 together serve as the third input terminal of the switching circuit 3. It should be noted that the body terminal of a MOSFET can also be referred to as the substrate.

[0037] In this embodiment of the present invention, the first resistor unit 1 includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4;

[0038] The first end of the first resistor R1, the first end of the second resistor R2, the first end of the third resistor R3, and the first end of the fourth resistor R4 together serve as the first end of the first resistor unit 1; the second end of the first resistor R1, the second end of the second resistor R2, the second end of the third resistor R3, and the second end of the fourth resistor R4 together serve as the second end of the first resistor unit 1.

[0039] Specifically, the second end of the first resistor R1 is connected to the gate of the first MOSFET M1, the second end of the second resistor R2 is connected to the gate of the second MOSFET M2, the second end of the third resistor R3 is connected to the gate of the third MOSFET M3, and the second end of the fourth resistor R4 is connected to the gate of the fourth MOSFET M4.

[0040] In this embodiment of the present invention, the second resistor unit 3 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8.

[0041] The first end of the fifth resistor R5, the first end of the sixth resistor R6, the first end of the seventh resistor R7, and the first end of the eighth resistor R8 together serve as the first end of the second resistor unit 3; the second end of the fifth resistor R5, the second end of the sixth resistor R6, the second end of the seventh resistor R7, and the second end of the eighth resistor R8 together serve as the second end of the second resistor unit 3.

[0042] Specifically, the second end of the fifth resistor R5 is connected to the body terminal of the first MOSFET M1, the second end of the sixth resistor R6 is connected to the body terminal of the second MOSFET M2, the second end of the seventh resistor R7 is connected to the body terminal of the third MOSFET M3, and the second end of the eighth resistor R8 is connected to the body terminal of the fourth MOSFET M4.

[0043] In this embodiment of the present invention, the bias network 4 includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a seventh diode D7, and an eighth diode D8.

[0044] The first end of the ninth resistor R9 is connected to the second end of the fifth resistor R5, and the second end of the ninth resistor R9 is connected to the positive terminal of the first diode D1 and the positive terminal of the second diode D2 respectively; the negative terminals of the first diode D1 and the second diode D2 are connected to each other and are respectively connected to the source of the second MOS transistor M2 and the drain of the third MOS transistor M3.

[0045] The first end of the tenth resistor R10 is connected to the second end of the sixth resistor R6, and the second end of the tenth resistor R10 is connected to the positive terminal of the third diode D3 and the positive terminal of the fourth diode D4 respectively; the negative terminal of the third diode D3 is connected to the drain of the first MOS transistor M1; the negative terminal of the fourth diode D4 is connected to the source of the third MOS transistor M3 and the drain of the fourth MOS transistor M4 respectively.

[0046] The first end of the eleventh resistor R11 is connected to the second end of the seventh resistor R7. The second end of the eleventh resistor R11 is connected to the positive terminal of the fifth diode D5 and the positive terminal of the sixth diode D6. The negative terminal of the fifth diode D5 is connected to the drain of the second MOS transistor M2 and the source of the first MOS transistor M1. The negative terminal of the sixth diode D6 is connected to the source of the fourth MOS transistor M4.

[0047] The first end of the twelfth resistor R12 is connected to the second end of the eighth resistor R8, and the second end of the twelfth resistor R12 is connected to the positive terminal of the seventh diode D7 and the positive terminal of the eighth diode D8, respectively; the negative terminals of the seventh diode D7 and the eighth diode D8 are connected to each other and are respectively connected to the source of the second MOS transistor M2 and the drain of the third MOS transistor M3.

[0048] In this embodiment of the invention, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, and the fourth MOS transistor M4 are all NMOS transistors.

[0049] It should be noted that the number of MOSFETs in the switching circuit 3 of this utility model can be adjusted according to the actual situation, including but not limited to 4 MOSFETs. Furthermore, each additional MOSFET in the switching circuit 3 will cause the first resistor unit 1 to add a corresponding resistor, the second resistor unit 3 to add a corresponding resistor, and the bias network 4 to add a corresponding resistor and two diodes. Their connection method is the same as that of the first resistor R1, the first MOSFET M1, the fifth resistor R5, the ninth resistor R9, the first diode D1, and the second diode D2.

[0050] Specifically, when the switch is in the off mode, the channel between the second input and output terminals of the switching circuit 3 needs to be completely depleted to prevent partial depletion, which would cause the high-power RF signal flowing through the off switch to generate harmonics and affect the linearity of the signal. Therefore, during off, the first bias voltage VG and the second bias voltage VB will be supplied with a negative voltage through a charge pump to establish a negative electrostatic field to deplete the source-drain channel. However, under the condition of a large RF signal, the voltage driving capability may be insufficient, and the negative voltage at the gate and body of the MOS transistor in the switching circuit 3 will rise. There will also be an RF voltage difference between the body and the source and drain, and the parasitic reverse diode may turn on.

[0051] To achieve better radio frequency (RF) performance, this invention adds a bias network 4 to the DC bias voltage applied to the body terminal of the MOS transistor in the switching circuit 3. One end of the second resistor unit 3 is connected to the body terminal of each MOS transistor in the switching circuit 3, and the other end is connected to the diode in the bias network 4. This allows control over the amplitude of the RF signal reaching the diode. The diode can rectify the RF signal into a DC signal, further reducing the bias voltage at the body terminal. This prevents depletion of the source-drain channel and conduction of parasitic reverse diodes, ensuring the harmonic performance of the switch and preventing nonlinear distortion of the RF signal.

[0052] When the RF switch circuit 100 is in the off mode, the first bias voltage VG and the second bias voltage VB need to be supplied with a negative DC bias voltage through the charge pump. When a large signal flows through this off switch, the diode in the bias network 4 will rectify the coupled RF signal to generate a DC voltage, which will further strengthen the negative bias voltage of the body terminal of the MOS transistor in the switching circuit 3, ensuring the working state of the switch and the performance of the high-power RF signal.

[0053] Compared with the prior art, the radio frequency switch circuit proposed in this utility model includes a first resistor unit, a switch circuit, a second resistor unit, and a bias network connected in sequence. The first end of the first resistor unit is used to receive a first bias voltage, and the second end of the first resistor unit is connected to the first input terminal of the switch circuit. The first resistor unit is used to reduce the voltage distribution of the switch circuit. The second input terminal of the switch circuit serves as the input terminal of the radio frequency switch circuit and is used to receive radio frequency signals. The output terminal of the switch circuit serves as the output terminal of the radio frequency switch circuit. The first end of the second resistor unit is used to receive a second bias voltage, and the second end of the second resistor unit is connected to the third input terminal of the switch circuit. The second resistor unit is used to reduce the voltage distribution of the switch circuit. The bias network is used to rectify the radio frequency signals received by the switch circuit into DC signals. The radio frequency (RF) switch circuit proposed in this invention adds a bias network to the DC bias voltage applied to the body terminal of the MOSFET in the switching circuit. This allows control over the amplitude of the RF signal reaching the diode. The diode rectifies the RF signal into a DC signal, further reducing the bias voltage at the body terminal of the MOSFET. This prevents depletion of the source-drain channel and conduction of the parasitic reverse diode, ensuring the harmonic performance of the switch and preventing nonlinear distortion of the RF signal.

[0054] Example 2

[0055] This utility model also provides a radio frequency chip, which includes the radio frequency switch circuit 100 as described in the above embodiments, and can achieve the same technical effect as the radio frequency switch circuit 100 in the above embodiments, which will not be described again here.

[0056] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0057] The embodiments of the present utility model have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present utility model. However, the present utility model is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes under the guidance of the present utility model without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present utility model.

Claims

1. A radio frequency switch circuit, characterized by The radio frequency switch circuit comprises a first resistance unit, a switch circuit, a second resistance unit and a bias network connected in sequence; a first end of the first resistance unit is configured to receive a first bias voltage, and a second end of the first resistance unit is connected to a first input end of the switch circuit, and the first resistance unit is configured to reduce voltage distribution of the switch circuit; a second input end of the switch circuit is configured as an input end of the radio frequency switch circuit and configured to receive a radio frequency signal, and an output end of the switch circuit is configured as an output end of the radio frequency switch circuit; a first end of the second resistance unit is configured to receive a second bias voltage, and a second end of the second resistance unit is connected to a third input end of the switch circuit, and the second resistance unit is configured to reduce voltage distribution of the switch circuit; the bias network is configured to rectify the radio frequency signal received by the switch circuit into a direct current signal.

2. The radio frequency switch circuit of claim 1, wherein, The switch circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor; a gate of the first MOS transistor, a gate of the second MOS transistor, a gate of the third MOS transistor and a gate of the fourth MOS transistor are collectively configured as a first input end of the switch circuit; a drain of the first MOS transistor is configured as an output end of the switch circuit, a source of the first MOS transistor is connected to a drain of the second MOS transistor, a source of the second MOS transistor is connected to a drain of the third MOS transistor, a source of the third MOS transistor is connected to a drain of the fourth MOS transistor, and a source of the fourth MOS transistor is configured as a second input end of the switch circuit; a body of the first MOS transistor, a body of the second MOS transistor, a body of the third MOS transistor and a body of the fourth MOS transistor are collectively configured as a third input end of the switch circuit.

3. The radio frequency switch circuit of claim 1, wherein, The first resistance unit comprises a first resistance, a second resistance, a third resistance and a fourth resistance; a first end of the first resistance, a first end of the second resistance, a first end of the third resistance and a first end of the fourth resistance are collectively configured as a first end of the first resistance unit; and a second end of the first resistance, a second end of the second resistance, a second end of the third resistance and a second end of the fourth resistance are collectively configured as a second end of the first resistance unit.

4. The radio frequency switch circuit of claim 2, wherein, The second resistance unit comprises a fifth resistance, a sixth resistance, a seventh resistance and an eighth resistance; a first end of the fifth resistance, a first end of the sixth resistance, a first end of the seventh resistance and a first end of the eighth resistance are collectively configured as a first end of the second resistance unit; and a second end of the fifth resistance, a second end of the sixth resistance, a second end of the seventh resistance and a second end of the eighth resistance are collectively configured as a second end of the second resistance unit.

5. The radio frequency switch circuit of claim 4, wherein, The bias network comprises a ninth resistance, a tenth resistance, an eleventh resistance, a twelfth resistance, a first diode, a second diode, a third diode, a fourth diode, a fifth diode, a sixth diode, a seventh diode and an eighth diode. The first end of the ninth resistor is connected to the second end of the fifth resistor, and the second end of the ninth resistor is connected to the anode of the first diode and the anode of the second diode, respectively; the cathode of the first diode and the cathode of the second diode are connected to each other and connected to the source of the second MOS tube and the drain of the third MOS tube, respectively; The first end of the tenth resistor is connected to the second end of the sixth resistor, and the second end of the tenth resistor is connected to the anode of the third diode and the anode of the fourth diode, respectively; the cathode of the third diode is connected to the drain of the first MOS tube; and the cathode of the fourth diode is connected to the source of the third MOS tube and the drain of the fourth MOS tube, respectively; The first end of the eleventh resistor is connected to the second end of the seventh resistor, and the second end of the eleventh resistor is connected to the anode of the fifth diode and the anode of the sixth diode, respectively; the cathode of the fifth diode is connected to the drain of the second MOS tube and the source of the first MOS tube, respectively; and the cathode of the sixth diode is connected to the source of the fourth MOS tube; The first end of the twelfth resistor is connected to the second end of the eighth resistor, and the second end of the twelfth resistor is connected to the anode of the seventh diode and the anode of the eighth diode, respectively; the cathode of the seventh diode and the cathode of the eighth diode are connected to each other and connected to the source of the second MOS tube and the drain of the third MOS tube, respectively.

6. The radio frequency switch circuit of claim 2, wherein, The first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube are all NMOS tubes.

7. A radio frequency chip, characterized by The radio frequency chip comprises the radio frequency switch circuit as claimed in any one of claims 1-6.

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