Photoelectric chip stacking packaging structure

Abstract

The utility model discloses a photoelectric chip stacking and packaging structure which comprises a PCB main board, a B substrate installed on the upper side of the PCB main board and an A substrate installed on the upper side of the B substrate, a photoelectric chip is arranged on the upper side of the A substrate, a bottom filling layer and solder balls are arranged among the PCB main board, the B substrate and the A substrate, an analog-to-digital conversion chip is arranged between the B substrate and the A substrate, and the bottom filling layer and the solder balls are arranged between the B substrate and the A substrate. A solder ball is arranged on the lower side of the analog-to-digital conversion chip; according to the utility model, the photoelectric chip is vertically connected with the analog-to-digital conversion chip through the solder balls, and the packaging mode is changed, so that the photoelectric detector module is miniaturized, and the signal transmission speed between the photoelectric chip and the analog-to-digital conversion chip is improved, thereby achieving the purposes of reducing the packaging area and improving the signal transmission speed.

Description

TECHNICAL FIELD

[0001] The utility model belongs to X -ray imaging technical field, concretely relates to a photoelectric chip stack packaging structure. BACKGROUND

[0002] Traditional photoelectric chip adopts the lead bonding mode packaging, and the digital analog conversion chip and the photoelectric chip are in the same PCB, so that the photoelectric chip module is large, therefore, a photoelectric chip stack packaging structure is needed to solve the above problems. SUMMARY

[0003] The utility model discloses a photoelectric chip stack packaging structure to solve the problems in the background art.

[0004] To achieve the above object, the utility model provides the following technical scheme: a photoelectric chip stack packaging structure, including PCB mainboard, install B substrate on the upside of PCB mainboard and install A substrate on the upside of B substrate, the upside of A substrate is provided with photoelectric chip, the bottom filling layer and the tin ball are arranged between PCB mainboard, B substrate and A substrate, the digital analog conversion chip is arranged between B substrate and A substrate, the downside of digital analog conversion chip is provided with tin ball.

[0005] Preferably, the downside of photoelectric chip and the tin ball between B substrate and PCB mainboard are installed at equal distance.

[0006] Preferably, the edge between B substrate and A substrate is provided with tin ball.

[0007] Preferably, the downside of digital analog conversion chip is uniformly provided with tin ball.

[0008] Compared with the prior art, the utility model has the advantages of:

[0009] The photoelectric chip of the utility model is interconnected with the digital analog conversion chip perpendicularly through tin ball, makes photoelectric detector module miniaturization through changing the packaging mode, improves the signal transmission speed between photoelectric chip and digital analog conversion chip, thereby achieves the purpose of reducing the packaging area and improving the signal transmission speed. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 It is the structural schematic diagram of the utility model;

[0011] In the drawing: 1, PCB mainboard;2, B substrate;3, A substrate;4, photoelectric chip;5, bottom filling layer;6, digital analog conversion chip;7, tin ball. DETAILED DESCRIPTION

[0012] With reference to the drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative labor fall within the scope of the present application.

[0013] Please refer to Figure 1 The utility model provides a technical scheme: a photoelectric chip stacked package structure, including PCB mainboard 1, install on the upside of PCB mainboard 1 B substrate 2 and install on the upside of B substrate 2 A substrate 3, the upside of A substrate 3 is provided with photoelectric chip 4, the bottom filling layer 5 and the tin ball 7 are provided between PCB mainboard 1, B substrate 2 and A substrate 3, the analog-digital conversion chip 6 is provided between B substrate 2 and A substrate 3, the downside of analog-digital conversion chip 6 is provided with tin ball 7, change package mode, make photoelectric detector module miniaturization, improve photoelectric chip and the signal transmission speed between analog-digital conversion chip, the downside of photoelectric chip 4 and the tin ball 7 between B substrate 2 and PCB mainboard 1 are installed equidistantly, the edge between B substrate 2 and A substrate 3 is provided with tin ball 7, the downside of analog-digital conversion chip 6 is uniformly provided with tin ball 7.

[0014] From the above description, the utility model has the following beneficial effects: change package mode, make photoelectric detector module miniaturization, improve photoelectric chip and the signal transmission speed between analog-digital conversion chip.

[0015] Adopt the above technical scheme, and photoelectric chip is connected with analog-digital conversion chip vertically through tin ball.

[0016] The working principle and use flow of the utility model: photoelectric chip 4 adopts the mode of planting ball, and is inverted to A substrate 3, and is composed of package A3;Analog-digital conversion chip 6 adopts the mode of planting ball and is inverted to B substrate 2, and is composed of package B2, finally, photoelectric detector module is composed of package A3, package B2, PCB mainboard 1 upper and lower layer.

[0017] It is to be noted that the relational terms herein, such as first and second, and the like, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0018] The above description is merely intended to illustrate the technical solutions of the present application, but not to limit the present application. Other modifications or equivalent replacements to the technical solutions of the present application made by those skilled in the art shall be included in the scope of the claims of the present application, as long as these modifications or equivalent replacements do not depart from the spirit and scope of the technical solutions of the present application.

Claims

1. A stacked packaging structure for optoelectronic chips, characterized in that: It includes a PCB motherboard (1), a B substrate (2) mounted on the upper side of the PCB motherboard (1) and an A substrate (3) mounted on the upper side of the B substrate (2). An optoelectronic chip (4) is disposed on the upper side of the A substrate (3). A bottom filler layer (5) and solder balls (7) are disposed between the PCB motherboard (1), the B substrate (2) and the A substrate (3). An analog-to-digital converter chip (6) is disposed between the B substrate (2) and the A substrate (3). Solder balls (7) are disposed on the lower side of the analog-to-digital converter chip (6).

2. The optoelectronic chip stacked packaging structure according to claim 1, characterized in that: The solder balls (7) on the lower side of the optoelectronic chip (4) and between the B substrate (2) and the PCB motherboard (1) are all installed at equal intervals.

3. The optoelectronic chip stacked packaging structure according to claim 1, characterized in that: Solder balls (7) are provided at the edge between substrate B (2) and substrate A (3).

4. The optoelectronic chip stacked packaging structure according to claim 1, characterized in that: Solder balls (7) are evenly arranged on the lower side of the analog-to-digital converter chip (6).

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