Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a substrate, a plurality of sub-pixels (Pxij), a driving circuit layer and a pixel definition layer, the sub-pixels (Pxij), the driving circuit layer and the pixel definition layer are arranged on the substrate, the driving circuit layer is located between the substrate and the pixel definition layer, the driving circuit layer comprises a plurality of conductive layers, a plurality of pixel openings (K) are formed in the pixel definition layer, and each sub-pixel (Pxij) comprises at least one pixel opening (K); in at least one conducting layer of the multiple conducting layers, at least one signal line (SL) in the same conducting layer corresponds to at least one pixel opening (K), at least one signal line (SL) and the corresponding pixel opening (K) have an overlapping area, and in the area corresponding to the same pixel opening (K), at least one signal line (SL) and the corresponding pixel opening (K) have an overlapping area. The at least one signal line (SL) is symmetrical relative to a first center line of the pixel opening (K), and the first center line is a center line of the pixel opening (K) extending along the second direction Y. According to the technical scheme provided by the embodiment of the invention, the asymmetric color cast can be improved.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) and quantum dot light emitting diode (QLED) are active light emitting display devices, which have the advantages of self-luminous, wide viewing angle, high contrast, low power consumption, extremely high response speed, lightness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices with OLED or QLED as light emitting devices and controlled by thin film transistors (TFT) have become the mainstream products in the current display field.

[0003] At present, the display substrate has the technical problem of color asymmetry. CONTENT OF THE UTILITY MODEL

[0004] The problem to be solved by the embodiment of the present disclosure is to provide a display substrate and a display device to solve the technical problem of color asymmetry of the existing display substrate.

[0005] In order to solve the above technical problems, in a first aspect, the embodiment of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels, a driving circuit layer and a pixel definition layer disposed on the substrate, the driving circuit layer is located between the substrate and the pixel definition layer in a direction perpendicular to the plane where the display substrate is located, the driving circuit layer comprises a plurality of conductive layers, a plurality of pixel openings are formed in the pixel definition layer, and the sub-pixel comprises at least one pixel opening.

[0006] In at least one conductive layer of the plurality of conductive layers, at least one signal line in the same conductive layer corresponds to at least one pixel opening, the at least one signal line and the corresponding pixel opening have an overlapping area, in the area corresponding to the same pixel opening, the at least one signal line is symmetrical to the first middle line of the pixel opening, and the first middle line is the middle line of the pixel opening extending in the second direction.

[0007] In an exemplary embodiment, the at least one conductive layer comprises the conductive layer in the driving circuit layer which is most adjacent to the pixel definition layer, and the at least one signal line is located in the conductive layer which is most adjacent to the pixel definition layer.

[0008] In an exemplary embodiment, the display substrate further comprises an anode conductive layer, the anode conductive layer is located between the driving circuit layer and the pixel definition layer in a direction perpendicular to the plane of the display substrate, the anode conductive layer comprises a plurality of anodes, the plurality of anodes correspond to the plurality of pixel openings one by one, the orthographic projection of the pixel opening on the base is within the orthographic projection of the corresponding anode on the base.

[0009] The at least one signal line corresponds to at least one anode, there is an overlapping area between the at least one signal line and the corresponding anode, in the area corresponding to the same anode, the at least one signal line is symmetrical to the second median line of the anode main body, and the second median line is a median line of the anode main body extending in the second direction; in the same sub-pixel, the orthographic projection of the first median line and the second median line on the base overlaps.

[0010] In an exemplary embodiment, the at least one signal line comprises at least one first type of signal line and at least one second type of signal line, the at least one first type of signal line and the at least one second type of signal line are arranged at intervals along the first direction and extend along the second direction, in the first direction, the size of the first type of signal line is greater than the size of the second type of signal line, and in the plane parallel to the base, the first direction intersects the second direction.

[0011] At least part of the structure of the area corresponding to the pixel opening of at least part of the first type of signal line is provided as a hollow structure, the hollow structure divides the first type of signal line into a plurality of lines arranged at intervals along the first direction, in the area corresponding to the same pixel opening, in the first direction, the size of at least part of the lines and at least part of the second type of signal line is consistent with the size of at least part of the second type of signal line.

[0012] In an exemplary embodiment, in the area corresponding to the same pixel opening: a plurality of first spacings are provided between the plurality of lines and the at least one second type of signal line, the plurality of first spacings are consistent in size, and the first spacing is the distance between adjacent two of the plurality of lines and the at least one second type of signal line.

[0013] In an exemplary embodiment, in the area corresponding to the same pixel opening, the plurality of lines and the at least one second type of signal line are uniformly arranged along the first direction.

[0014] In an exemplary embodiment, in the region corresponding to the pixel opening, the size of the line and the size of the second type of signal line along the first direction are both greater than or equal to 1 micron and less than or equal to 15 microns, and the size of the first pitch along the first direction is greater than or equal to 1 micron and less than or equal to 15 microns.

[0015] In an exemplary embodiment, the substrate includes a display region, and the plurality of sub-pixels are located in the display region. A same first type of signal line is provided with at least one connection node in the display region, and a plurality of lines in the same first type of signal line are connected to each other at the connection node.

[0016] In an exemplary embodiment, the display substrate further includes a frame region surrounding the display region and a plurality of first connection structures. In the second direction, the first connection structures are located on a side of the display region close to the frame region. In at least some of the plurality of first connection structures, each first connection structure corresponds to one first type of signal line, and a plurality of lines in a same first type of signal line are connected to each other through the corresponding first connection structure on the side close to the frame region.

[0017] In an exemplary embodiment, the display substrate further includes a plurality of first connection structures. In at least some of the plurality of first connection structures, each first connection structure corresponds to one first type of signal line. In the second direction, the first connection structures are located between adjacent two pixel openings. In at least some of the plurality of pixel openings, each pixel opening is provided with at least one first connection structure on both sides, and a plurality of lines in a same first type of signal line between adjacent two pixel openings are connected to each other through the corresponding first connection structure.

[0018] In an exemplary embodiment, at least one of the sub-pixels includes a pixel driving circuit, and the pixel driving circuit is located in the driving circuit layer. At least one of the pixel driving circuits includes a plurality of transistors and at least one capacitor. The plurality of transistors include at least one first type of transistor and at least one second type of transistor.

[0019] In a direction perpendicular to a plane in which the substrate is located, the capacitor comprises: a first electrode plate located on one side of the substrate, and a second electrode plate located on a side of the first electrode plate away from the substrate; the first type of transistor comprises: an active layer located on a side of the first electrode plate close to the substrate, a control electrode disposed in the same layer as the first electrode plate, a first electrode and a second electrode located on a side of the control electrode away from the substrate; the second type of transistor comprises: an active layer located on a side of the second electrode plate away from the substrate, a control electrode located on a side of the active layer away from the substrate, and a first electrode and a second electrode located on a side of the control electrode away from the substrate; the first electrode and the second electrode of the first type of transistor are disposed in the same layer as the first electrode and the second electrode of the second type of transistor, and the at least one signal line is located on a side of the first electrode and the second electrode away from the substrate.

[0020] In an example embodiment, the at least one signal line comprises a plurality of first power lines and a plurality of first initial signal connection lines, the at least one signal line extends along the second direction and is arranged along a first direction; the plurality of sub-pixels at least comprises a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, the plurality of sub-pixels form a plurality of pixel units, and each pixel unit at least comprises a first sub-pixel, a second sub-pixel and a third sub-pixel.

[0021] In the same pixel unit: in the second direction, the pixel opening of the second sub-pixel and the pixel opening of the third sub-pixel are arranged in sequence with a spacing; in the first direction, the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel are arranged in sequence, the pixel opening of the second sub-pixel and the pixel opening of the third sub-pixel are located on the same side of the pixel opening of the first sub-pixel, the first initial signal connection line is located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel, and in the region corresponding to the pixel opening of the second sub-pixel and the pixel opening of the third sub-pixel, the two first power lines in the second sub-pixel and the third sub-pixel are symmetrical with respect to the first initial signal connection line.

[0022] In an example embodiment, the at least one signal line further comprises a plurality of first second initial signal connection lines and a plurality of second power lines.

[0023] The first second initial signal line is located in the pixel driving circuit of the first sub-pixel, and each sub-pixel is provided with one second power line; in the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the first second initial signal line and the second power line in the first sub-pixel are symmetrical with respect to a third center line, and the third center line is a center line of the pixel opening of the first sub-pixel extending in the second direction.

[0024] In an exemplary embodiment, the display substrate further comprises a plurality of anode connection electrodes, a plurality of data signal lines and a plurality of anodes, the plurality of anodes are located between the driving circuit layer and the pixel opening in the direction perpendicular to the plane of the display substrate, the plurality of anode connection electrodes correspond to the plurality of anodes one by one, the sub-pixel further comprises at least one anode connection electrode and at least one anode, in the same sub-pixel, the pixel driving circuit is electrically connected to the corresponding anode through the corresponding anode connection electrode; the at least one signal line further comprises the plurality of anode connection electrodes;

[0025] In the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the data signal line and the anode connection electrode of the first sub-pixel are symmetrical relative to the third median line, in the first direction, the data signal line is located on the side of the first second initial signal connection line away from the second power line, and the anode connection electrode of the first sub-pixel is located on the side of the second power line away from the first second initial signal connection line.

[0026] In an exemplary embodiment, in the same pixel unit: in the region corresponding to the anode of the second sub-pixel, the anode connection electrodes in the second sub-pixel and the third sub-pixel are symmetrical relative to the first initial signal connection line; in the first direction, in any one of the second sub-pixel and the third sub-pixel, the anode connection electrode is located on the side of the first power line away from the first initial signal connection line.

[0027] In an exemplary embodiment, the at least one signal line comprises a plurality of first type signal lines and a plurality of second type signal lines, in the first direction, the size of the first type signal line is greater than the size of the second type signal line;

[0028] The plurality of first type signal lines comprises: a first second initial signal line and a second power line in the pixel driving circuit of the first sub-pixel, and a first power line in the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel; the plurality of second type signal lines comprises: a data signal line and an anode connection electrode in the pixel driving circuit of the first sub-pixel, and a first initial signal connection line between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel;

[0029] The region corresponding to the pixel opening of the first type of signal line is provided as a hollow structure, the hollow structure divides the first type of signal line into a plurality of lines arranged at intervals along the first direction, and in the region corresponding to the same pixel opening, the size of the plurality of lines in the first direction is consistent with the size of the second type of signal line.

[0030] In an example embodiment, the display substrate further comprises a plurality of second power supply connection lines, the second power supply connection lines extend along the first direction, and the second power supply connection lines are provided in the same layer as the first electrode and the second electrode.

[0031] The plurality of second power supply lines and the plurality of second power supply connection lines are connected to each other through second power supply vias to form a grid structure, the pixel opening of the first sub-pixel overlaps with the second power supply via, and in the region corresponding to the first pixel opening, the size of the line in the second power supply connection line along the first direction at the position of the second power supply via is greater than the size of the line along the first direction at the position not provided with the second power supply via.

[0032] In an example embodiment, in the same sub-pixel, a plurality of anode vias are provided, the plurality of anode vias include a first anode via and a second anode via, the anode connection electrode is electrically connected to the corresponding pixel driving circuit through the first anode via and is electrically connected to the corresponding anode through the second anode via, and the line of the first type of signal line adjacent to the anode via is bent away from the anode connection via in the direction away from the anode via.

[0033] In an example embodiment, in the same pixel unit: in the second power supply line corresponding to the anode of the first sub-pixel, at least one line in the second power supply line corresponding to the position of the anode via in the first sub-pixel is bent away from the corresponding anode via in the first direction and is combined with the line of the second power supply line away from the corresponding anode via; and in the first power supply line corresponding to the anode of the second sub-pixel, at least one line in the first power supply line corresponding to the position of the anode via in the second sub-pixel is bent away from the corresponding anode via in the first direction and is combined with the line of the first power supply line away from the corresponding anode via.

[0034] In a second aspect, the present disclosure further provides a display device comprising the display substrate described in any of the above embodiments.

[0035] The display substrate and display device provided in this disclosure include a display substrate in which the driving circuit layer includes multiple conductive layers. At least one signal line in the same conductive layer corresponds to at least one pixel opening. At least one signal line and the corresponding pixel opening have an overlapping area. In the area corresponding to the same pixel opening, at least one signal line is symmetrical with respect to the first center line of the pixel opening. The first center line is the center line of the pixel opening extending along a second direction. This can improve asymmetric color shift and solve the problem of color shift asymmetry to a certain extent, thereby improving the display effect.

[0036] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0037] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0038] Figure 1 This is a schematic diagram of the structure of a display device;

[0039] Figure 2a This is a schematic diagram of the structure of a display substrate;

[0040] Figure 2b The diagram shown is a schematic diagram of the structure of a display substrate;

[0041] Figure 2c The diagram shown is an enlarged view of the first border area.

[0042] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0043] Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0044] Figure 5a The diagram shown is a structural schematic of a display substrate provided in an embodiment of this disclosure;

[0045] Figure 5b As shown Figure 5a A schematic diagram of a planar structure consisting of a fifth conductive layer, an anode conductive layer, and a pixel opening;

[0046] Figure 5c As shown Figure 5b A schematic diagram of a cross-sectional structure at the M1-M1 position;

[0047] Figure 5d As shown Figure 5bA schematic diagram of a cross-sectional structure at the M2-M2 position;

[0048] Figure 5e As shown Figure 5b A schematic diagram of a cross-sectional structure at the M3-M3 position;

[0049] Figure 5f As shown Figure 5b A schematic diagram of a cross-sectional structure at the M4-M4 position;

[0050] Figure 6a The diagram shown is a planar structure schematic of a display substrate provided in an exemplary embodiment of this disclosure;

[0051] Figure 6b As shown Figure 6a A schematic diagram of a planar structure consisting of a fifth conductive layer, an anode conductive layer, and a pixel opening;

[0052] Figure 6c As shown Figure 6b A schematic diagram of a cross-sectional structure at the M5-M5 position;

[0053] Figure 6d The diagram shown is a planar structure schematic of a fifth conductive layer, an anode conductive layer, and a pixel opening provided in an exemplary embodiment of this disclosure.

[0054] Figure 6e The diagram shown is a planar structure schematic of a fifth conductive layer, an anode conductive layer, and a pixel opening provided in an exemplary embodiment of this disclosure.

[0055] Figure 7a The diagram shown is a planar structure schematic of a display substrate provided in an exemplary embodiment of this disclosure;

[0056] Figure 7b As shown Figure 7a A schematic diagram of a planar structure consisting of a fifth conductive layer, an anode conductive layer, and a pixel opening;

[0057] Figure 8 The diagram shown is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of this disclosure.

[0058] Figure 9a The diagram shown is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0059] Figure 9b The diagram shown is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of this disclosure;

[0060] Figure 10aA schematic view of a display substrate after forming a second conductive layer pattern is shown according to an example embodiment of the present disclosure;

[0061] Figure 10b A schematic view of a second conductive layer in a display substrate is shown according to an example embodiment of the present disclosure;

[0062] Figure 11a A schematic view of a display substrate after forming a second semiconductor layer pattern is shown according to an example embodiment of the present disclosure;

[0063] Figure 11b A schematic view of a second semiconductor layer in a display substrate is shown according to an example embodiment of the present disclosure;

[0064] Figure 12a A schematic view of a display substrate after forming a third conductive layer pattern is shown according to an example embodiment of the present disclosure;

[0065] Figure 12b A schematic view of a third conductive layer in a display substrate is shown according to an example embodiment of the present disclosure;

[0066] Figure 13 A schematic view of a display substrate after forming a fifth insulating layer pattern is shown according to an example embodiment of the present disclosure;

[0067] Figure 14a A schematic view of a display substrate after forming a fourth conductive layer pattern is shown according to an example embodiment of the present disclosure;

[0068] Figure 14b A schematic view of a fourth conductive layer in a display substrate is shown according to an example embodiment of the present disclosure;

[0069] Figure 15 A schematic view after forming a first planarization layer pattern is shown according to an example embodiment of the present disclosure;

[0070] Figure 16a A schematic view of a display substrate after forming a fifth conductive layer pattern is shown according to an example embodiment of the present disclosure;

[0071] Figure 16b A schematic view of a fifth conductive layer in a display substrate is shown according to an example embodiment of the present disclosure;

[0072] Figure 17 A schematic view of a display substrate after forming a second planarization layer is shown according to an example embodiment of the present disclosure;

[0073] Figure 18a A schematic view of a display substrate after forming an anode conductive layer pattern is shown according to an example embodiment of the present disclosure;

[0074] Figure 18b FIG. 1 shows a schematic diagram of an anode conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0075] Figure 19a FIG. 2 shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0076] Figure 19b FIG. 3 shows a schematic diagram of a pixel definition layer in a display substrate according to an example embodiment of the present disclosure;

[0077] Figure 20a FIG. 4 shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0078] Figure 20b FIG. 5 shows a schematic diagram of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0079] Figure 20c FIG. 6 shows a schematic diagram of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0080] Figure 20d FIG. 7 shows a schematic diagram of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0081] Figure 21a FIG. 8 shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0082] Figure 21b FIG. 9 shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0083] Figure 21c FIG. 10 shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0084] Figure 22a FIG. 11 shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0085] Figure 22b FIG. 12 shows a schematic diagram of a fifth conductive layer in a display substrate according to an example embodiment of the present disclosure;

[0086] Figure 23 FIG. 13 shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0087] Figure 24 FIG. 14 shows a schematic diagram of a display device according to an example embodiment of the present disclosure. Detailed Implementation

[0088] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0089] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0090] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0091] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0092] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0093] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, a channel region refers to a region where current flows mainly.

[0094] In this specification, a first electrode can be a drain electrode and a second electrode can be a source electrode, or a first electrode can be a source electrode and a second electrode can be a drain electrode. In the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other. In this embodiment of the disclosure, a gate electrode can be referred to as a control electrode.

[0095] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. An element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of an element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and an element having another function.

[0096] In this specification, "parallel" refers to a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0097] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0098] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not strictly a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, but can be an approximately triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, and can have some small deformation due to a tolerance, a rounded corner, a curved side, or the like.

[0099] In this embodiment of the disclosure, "approximately" means that a limit is not strictly defined, and a value within a range of a process and measurement error is allowed.

[0100] Figure 1A structural diagram of a display device is shown. The display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit, respectively. The data signal driving circuit is connected to a plurality of data signal lines (D1 to Dn), respectively. The scan signal driving circuit is connected to a plurality of scan signal lines (G1 to Gm), respectively. The light emission signal driving circuit is connected to a plurality of light emission signal lines (E1 to Eo), respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers. At least one sub-pixel Pxij can include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit can include a pixel driving circuit. The pixel driving circuit can be connected to a scan signal line, a light emission signal line, and a data signal line (which can be referred to as a data line), respectively. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray value using the clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide the scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register and can generate the scan signal in such a manner that the scan start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal. m can be a natural number. The light emission signal driving circuit can generate an emission signal to be provided to the light emission signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emission signal driving circuit can sequentially provide the emission signal having an off-level pulse to the light emission signal lines E1 to Eo. For example, the light emission driver can be configured in the form of a shift register and can generate the emission signal in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of the clock signal. o can be a natural number.

[0101] Figure 2aThis is a schematic diagram of a planar structure of a display substrate. Figure 2a As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting device under the control of the scan signal line and the light-emitting signal line. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0102] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0103] Figure 2b The diagram shown is a structural schematic of a display panel. Figure 2b As shown, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (bottom border) B1 and a second border area (top border) B2 arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a first edge (bottom edge) and a second edge (top edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixels may include pixel driving circuits and light-emitting devices. The first border area B1 may include a bonding circuit that connects signal lines to an external driving device. The third border area B3 and the fourth border area B4 may include gate driving circuits and a second power supply line VSS that transmits voltage signals to the plurality of sub-pixels.

[0104] Figure 2c The diagram shows a planar structural schematic of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along a direction away from the display area AA. The bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along a direction away from the bending area 12 from the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines configured to connect to the data signal lines (Data Line) of the display area AA in a fan-out routing manner. The first power line is configured to connect to the high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to connect to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to bond to the flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with a pad including a plurality of pins, and the flexible circuit board 30 may be bonded to the pad.

[0105] Figure 3 This is a cross-sectional structural diagram of a display substrate, illustrating the structure of three sub-pixels in an OLED display substrate. Figure 3As shown, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on the base 101, a light-emitting structure layer 103 disposed on the driving circuit layer 102 away from the base 101, and an encapsulation layer 104 disposed on the light-emitting structure layer 103 away from the base 101. In some possible implementation manners, the display substrate can include other film layers such as a spacer, and the present disclosure does not limit the same.

[0106] In the example implementation, the base 101 can be a flexible base or a rigid base. The driving circuit layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 103 can include an anode 301 connected to the drain electrode of the driving transistor 210 through a via, an organic light-emitting layer 302 connected to the anode 301, and a cathode 303 connected to the organic light-emitting layer 302, the organic light-emitting layer 302 emitting light of a corresponding color under the driving of the anode 301 and the cathode 303. The encapsulation layer 104 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together, the first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic materials, the second encapsulation layer 402 can be made of an organic material, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0107] In the example implementation, the organic light-emitting layer 302 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked together. In the example implementation, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap or can be isolated.

[0108] In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T1C, or 7T2C structure. For example... Figure 4 As shown, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T76) and two capacitors C (first capacitor C1 and second capacitor C2). The pixel driving circuit can be connected to ten signal lines (data signal line DL, scan control line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, first light emission control line EM1, second light emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS). In an exemplary embodiment, the third reset control line Reset3 can receive the signal from the first reset control line Reset1, which can reduce the number of gate driving circuits (GOA circuits) and is beneficial for narrowing the bezel. The following is in conjunction with... Figure 4 The pixel driving circuit is described below:

[0109] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the control electrode of the third transistor T3, the first terminal of the first capacitor C1, and the second electrode of the first transistor T1. The second node N2 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is connected to the second terminal of the first capacitor C1, the first terminal of the second capacitor C2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the second capacitor C2, the second electrode of the second transistor T2, and the second electrode of the fourth transistor T4. The fifth node N5 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting device EL.

[0110] In an exemplary embodiment, the first end of the first capacitor C1 is connected to the first node N1, and the second end of the first capacitor C1 is connected to the third node N3; the first end of the second capacitor C2 is connected to the third node N3, and the second end of the second capacitor C2 may be connected to the fourth node N4.

[0111] The control electrode of the first transistor T1 is connected to a first reset control line Resetl, the first electrode of the first transistor T1 is connected to a first initial signal line Vinitl, and the second electrode of the first transistor is connected to a first node N1. When an on-level reset signal is applied to the first reset control line Resetl, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the amount of charge at the control electrode of the third transistor T3.

[0112] The control electrode of the second transistor T2 is connected to a third reset control line Reset3, the first electrode of the second transistor T2 is connected to the first initial signal line Vinitl, and the second electrode of the second transistor T2 is connected to a fourth node N4. When an on-level reset signal is applied to the third reset control line Reset3, the second transistor T2 transmits an initialization voltage to the fourth node N4 to initialize the amount of charge accumulated at the fourth node N4 or release the amount of charge accumulated at the fourth node N4.

[0113] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to a second node N2, and the second electrode of the third transistor T3 is connected to a third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0114] The control electrode of the fourth transistor T4 is connected to a scan control line Gate, the first electrode of the fourth transistor T4 is connected to a data signal line DL, and the second electrode of the fourth transistor T4 is connected to the fourth node N4. The fourth transistor T4 can be referred to as a switching transistor, and when an on-level scan signal is applied to the scan control line Gate, the fourth transistor T4 inputs a data voltage of the data signal line DL to the pixel driving circuit.

[0115] The control electrode of the fifth transistor T5 is connected to a first emission control line EMl, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to a second emission control line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device (also the fifth node N5). The fifth transistor T5 and the sixth transistor T6 can be referred to as emission control transistors (or can be referred to as emission transistors). When on-level emission signals are applied to the first emission control line EMl and the second emission control line EM2, the fifth transistor T5 and the sixth transistor T6 are turned on to form a driving current path between the first power supply line VDD and the second power supply line VSS to cause the light emitting device to emit light.

[0116] The control electrode of the seventh transistor T7 is connected with the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected with the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected with the first electrode of the light emitting device (also the fifth node N5). When the turn-on level reset signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device EL, so as to initialize the amount of charge accumulated in the first electrode of the light emitting device EL or release the amount of charge accumulated in the first electrode of the light emitting device.

[0117] In the example embodiment, the second electrode of the light emitting device EL is connected with the second power supply line VSS, and the signal of the second power supply line VSS is a low level signal, and the signal of the first power supply line VDD is a high level signal continuously provided.

[0118] In the example embodiment, the first transistor T1 to the seventh transistor T7 can be a low temperature poly-silicon thin film transistor (which can be referred to as a P-type transistor), or can be an oxide thin film transistor (which can be referred to as an N-type transistor), or can be a low temperature poly-silicon thin film transistor and an oxide thin film transistor, for example, Figure 4 In the example embodiment, the first transistor T1 to the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7 can be oxide thin film transistors, and the fifth transistor T5 can be a low temperature poly-silicon thin film transistor. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current, low frequency driving, and low power consumption. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO) display substrate, which can take advantage of both and can realize low frequency driving, reduce power consumption, and improve display quality.

[0119] In the example embodiment, the light emitting device EL can be an organic electroluminescence diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0120] In a direction perpendicular to a plane where the display substrate is located, a planar layer is arranged between the anode and a second source-drain metal layer (a conductive layer in the driving circuit layer that is closest to the anode), the second source-drain metal layer is provided with a plurality of traces, and the traces of the second source-drain metal layer are unevenly arranged at a position where the second source-drain metal layer overlaps the anode at a pixel opening position (for example, some traces have a larger area, and some traces have a smaller area, the planar layer corresponding to the traces with a larger area is convex on a side close to the anode, which causes the corresponding anode to be convex, and the surface of the anode on a side away from the planar layer is relatively high with respect to the base; the planar layer corresponding to the traces with a smaller area and the space between the traces is relatively low on a side close to the anode, which causes the surface of the anode on a side away from the planar layer to be relatively low with respect to the base), so that the side of the anode away from the planar layer is unevenly distributed in height according to the shape of the traces of the second source-drain metal layer. Because the surface of the anode on a side away from the planar layer is not uniform in height with respect to the base, the pixel opening of the display substrate often has a problem of symmetrical color cast, that is, asymmetrical color cast, which affects the visual effect, and this problem of asymmetrical color cast is particularly serious in a display substrate with a medium-large size Real RGB pixel architecture.

[0121] The display substrate provided by the example embodiments of the present disclosure can include a base and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer arranged on the base, the driving circuit layer is located between the base and the pixel definition layer in a direction perpendicular to a plane where the display substrate is located, the driving circuit layer includes a plurality of conductive layers, and the pixel definition layer has a plurality of pixel openings formed therein, and the sub-pixel includes at least one pixel opening.

[0122] In at least one conductive layer of the plurality of conductive layers, at least one signal line in the same conductive layer corresponds to at least one pixel opening, the at least one signal line and the corresponding pixel opening have an overlapping area, in the area corresponding to the same pixel opening, the at least one signal line is symmetrical with respect to a first middle line of the pixel opening, and the first middle line is a middle line of the pixel opening extending in a second direction.

[0123] The display substrate provided by the example embodiments of the present disclosure can include a base and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer arranged on the base, the driving circuit layer is located between the base and the pixel definition layer in a direction perpendicular to a plane where the display substrate is located, the driving circuit layer includes a plurality of conductive layers, and the pixel definition layer has a plurality of pixel openings formed therein, and the sub-pixel includes at least one pixel opening.

[0124] As Figure 5a , Figure 6a and Figure 7aAs shown in FIG. 1, a schematic diagram of a planar structure of a display substrate provided by an embodiment of the present disclosure is shown, the display substrate provided by the embodiment of the present disclosure can include a substrate, and a plurality of sub-pixels Pxij, a driving circuit layer, and a pixel definition layer disposed on the substrate, the driving circuit layer is located between the substrate and the pixel definition layer in a direction perpendicular to a plane on which the display substrate is located, the driving circuit layer can include a plurality of conductive layers, and a plurality of pixel openings K are formed in the pixel definition layer, the sub-pixel Pxij includes at least one pixel opening K;

[0125] In at least one conductive layer of the plurality of conductive layers, at least one signal line SL in the same conductive layer corresponds to at least one pixel opening K, and the at least one signal line SL and the corresponding pixel opening K have an overlapping area, in the area corresponding to the same pixel opening K, the at least one signal line SL is symmetrical with respect to a first median line Q1-Q1 (such as Figure 5a as shown) of the pixel opening K.

[0126] In the exemplary embodiment, in the area corresponding to the same pixel opening K, the at least one signal line SL is symmetrical with respect to the first median line Q1-Q1 of the pixel opening K, which can make the height of the anode on the side away from the substrate in the pixel opening relative to the substrate symmetrical, thereby reducing asymmetric color deviation.

[0127] In the exemplary embodiment, the at least one conductive layer can include a conductive layer in the driving circuit layer that is closest to the pixel definition layer, and the at least one signal line SL can be located in the conductive layer in the driving circuit layer that is closest to the pixel definition layer. For example, the conductive layer in the driving circuit layer that is closest to the pixel definition layer is a second source-drain metal layer (usually located in the fifth conductive layer of the pixel driving circuit), and the at least one signal line can be located in the second source-drain metal layer.

[0128] In the exemplary embodiment, as shown in FIG. 2, Figure 5b to Figure 5f Figure 5b for example, Figure 5a a schematic diagram of a planar structure of a second source-drain metal layer, an anode conductive layer, and a pixel definition layer in the embodiment, Figure 5c for example, Figure 5b a schematic diagram of a cross-sectional structure along the position of M1-M1 in the embodiment, Figure 5d for example, Figure 5b a schematic diagram of a cross-sectional structure along the position of M2-M2 in the embodiment, Figure 5e for example, Figure 5b a schematic diagram of a cross-sectional structure along the position of M3-M3 in the embodiment, Figure 5f for example, Figure 5b ​A cross-sectional structural diagram along the M4-M4 position shows that the display substrate may also include an anode conductive layer. In the direction perpendicular to the plane of the display substrate, the anode conductive layer may be located between the driving circuit layer and the pixel definition layer. The anode conductive layer may include multiple anodes AN, and the multiple anodes AN correspond one-to-one with multiple pixel openings K. The orthogonal projection of the pixel opening K on the substrate may be located within the range of the orthogonal projection of the corresponding anode AN on the substrate.

[0129] At least one signal line SL corresponds to at least one anode AN, and at least one signal line SL overlaps with the corresponding anode AN. In the region corresponding to the same anode AN, at least one signal line SL is symmetrical with respect to the second center line Q2-Q2 of the main body of the anode AN. The second center line Q2-Q2 is the center line extending along the second direction Y of the main body of the anode AN. In the same sub-pixel Pxij, the first center line Q1-Q1 can overlap with the orthographic projection of the second center line Q2-Q2 onto the substrate, such as... Figure 5a As shown, the first median line Q1-Q1 overlaps with the second median line Q2-Q2.

[0130] In an exemplary embodiment, in the region corresponding to the same anode AN, at least one signal line SL is symmetrical with respect to the second center line Q2-Q2 of the anode AN body, which can improve the flatness of the anode away from the substrate, reduce color asymmetry, and improve display uniformity.

[0131] In an exemplary embodiment, Figure 5c for Figure 5b A cross-sectional view of the pixel opening K01 of the first sub-pixel P1. Figure 5d for Figure 5b A cross-sectional view of the pixel opening K02 position of the second sub-pixel P2. Figure 5e for Figure 5b A cross-sectional view of the pixel opening K03 of the third sub-pixel P3. Figure 5f for Figure 5b A cross-sectional view of the second sub-pixel P2 at position M4-M4, through... Figure 5b floor plan and Figure 5c to Figure 5f The cross-sectional view clearly shows that, without the cutout structure KL on the first type of signal line SL1, multiple signal lines SL in the region corresponding to the pixel opening K in each first sub-pixel Pxij are symmetrical with respect to the midline extending along the second direction Y of the corresponding pixel opening K. This can improve the flatness of the anode side of the pixel opening K away from the substrate, thereby reducing color shift asymmetry. Figure 5cIn the structure shown, in the first direction X, the dimensions of distance a1 and distance b1 are substantially the same, the dimensions of distance a2 and distance b2 are substantially the same, the dimensions of distance a3 and distance b3 are substantially the same, the dimensions of distance a4 and distance b5 are substantially the same, and the dimensions of distance a5 and distance b5 are substantially the same. In an exemplary embodiment, Figure 5c to Figure 5f In this context, PDL is the pixel definition layer, and PLN2 is the second flattening layer.

[0132] In an exemplary implementation, such as Figure 5a , Figure 6a and Figure 7a As shown, at least one signal line SL may include at least one first-type signal line SL1 and at least one second-type signal line SL2. The at least one first-type signal line SL1 and the at least one second-type signal line SL2 are spaced apart along a first direction X and extend along a second direction Y, as shown. Figure 5b and Figure 5c As shown, Figure 5c for Figure 5b A cross-sectional structural diagram at position M1-M1 shows that, in the first direction X, the size f1 of the first type of signal line SL1 is larger than the size f2 of the second type of signal line SL2. In a plane parallel to the substrate, the first direction X intersects with the second direction Y.

[0133] In an exemplary implementation, such as Figure 6b and Figure 7b As shown, Figure 6b for Figure 6a A schematic diagram of the planar structure of the second source / drain metal layer, the anode conductive layer, and the pixel definition layer. Figure 7b for Figure 7a A schematic diagram of the planar structure of the second source / drain metal layer, the anode conductive layer, and the pixel definition layer shows that at least a portion of the structure of the region corresponding to at least a portion of the first type signal lines SL1 and the pixel opening K can be set as a hollow structure LK. The hollow structure LK can divide the first type signal lines SL1 into multiple lines L0 arranged at intervals along the first direction X. In the region corresponding to the same pixel opening K, along the first direction X, among the multiple lines L0 and at least one second type signal line SL2, the size w1 of at least a portion of the lines L0 is the same as the size w2 of at least a portion of the second type signal lines SL2. Figure 6c As shown, Figure 6b A cross-sectional structural diagram at position M5-M5 shows that in the region corresponding to the same pixel opening K, in the first direction X, the size w1 of line L0 is the same as the size w2 of the second type signal line SL2. Figure 7b Schematic diagram of the cross-sectional structure at position M6-M6 in the middle and Figure 6c same.

[0134] In an exemplary implementation, such asFigure 6b and Figure 6c As shown, in the region corresponding to the same pixel opening K: multiple first spacings h1 are provided between multiple lines L0 and at least one second-type signal line SL2. The multiple first spacings h1 have the same size. The first spacing h1 is the distance between two adjacent lines L0 and at least one second-type signal line SL2. For example, the first spacing h1 may include Figure 6c The numbers s2, s3, s4, s5, and s6 are given.

[0135] In an exemplary implementation, such as Figure 6c As shown, in the region corresponding to the same pixel opening K, multiple lines L0 and at least one second-type signal line SL2 are uniformly arranged along the first direction X, which can improve the flatness of the anode away from the substrate and reduce color asymmetry to a certain extent.

[0136] In an exemplary implementation, such as Figure 6c As shown, in the region corresponding to the same pixel opening K, in the first direction X, the size w1 of line L0 is consistent with the size w2 of the second type signal line SL, and the sizes of multiple first spacings h1 are consistent (consistency can be basically the same or have a certain error). This ensures that multiple lines L0 and at least one second type signal line SL2 are evenly distributed along the first direction X, which can improve the flatness of the side of the anode away from the substrate and help reduce color shift asymmetry. In actual design, s1 is usually the same as s7, and the value of pixel opening K along the first direction X is fixed. The closer the values ​​of w1 and w2 are, the better the color shift asymmetry problem is solved. The closer the values ​​of s2, s3, s4, s5, and s6 are, the better the color shift asymmetry problem is solved. The number of lines L0 corresponding to each pixel opening K can be set according to the values ​​of s2 to s6 and the value of w1. Figure 6c The pixel opening K01 of the first sub-pixel P1 shown corresponds to four lines L0, one anode connecting electrode ZL, and one data signal line DL, but is not limited to this. It can be designed by combining the pixel opening size and the size of the signal line SL corresponding to the pixel opening.

[0137] In an exemplary implementation, such as Figure 6c As shown, in the region corresponding to pixel opening K, the dimension w1 of line L0 along the first direction X and the dimension w2 of the second type signal line SL2 along the first direction X are both greater than or equal to 1 micrometer and less than or equal to 15 micrometers, and the dimension h1 of the first spacing along the first direction X is greater than or equal to 1 micrometer and less than or equal to 15 micrometers. For example, as Figure 6cAs shown, the dimension w1 of the line L0 along the first direction X can be greater than or equal to 1.5 microns or less than or equal to 10 microns, the dimension w2 of the second type of signal line SL2 along the first direction X can be greater than or equal to 1.5 microns or less than or equal to 10 microns, and the dimension of the first spacing h1 along the first direction X can be greater than or equal to 2 microns or less than or equal to 12 microns. For example, w1 and w2 can be about 2 microns, and h1 can be about 3 microns.

[0138] In an example embodiment, as shown in Figure 2b The substrate can include a display area AA, and a plurality of sub-pixels Pxij can be located in the display area AA, as shown in Figure 6b As shown, the same first type of signal line SL1 can be provided with at least one connection node L1 in the display area AA, and a plurality of line segments L0 in the same first type of signal line SL1 can be connected to each other at the position of the connection node L1. This can avoid an increase in the resistance of the corresponding first type of signal line SL1 due to the breakage of one or more line segments L0, and can reduce the impedance of the corresponding first type of signal line SL1 in the case of breakage of a line segment at a certain position, thereby improving display uniformity.

[0139] In an example embodiment, as shown in Figure 2b , Figure 6e and Figure 6d The display substrate can further include a frame area BB surrounding the display area AA and a plurality of first connection structures LH1. In the second direction Y: the first connection structures LH1 can be located on the side of the display area AA close to the frame area BB, and in at least some of the plurality of first connection structures LH1, each first connection structure LH1 corresponds to one of the first type of signal lines SL1. A plurality of line segments L0 in the same first type of signal line SL1 can be connected to each other through the corresponding first connection structure LH1 on the side close to the frame area BB, which can avoid an increase in the impedance of the corresponding first type of signal line SL1 due to the breakage of a line segment L0 at a certain position. For example, Figure 6d As shown in the side of the first row of sub-pixels close to the second frame area B2, each first type of signal line SL1 is provided with a corresponding first connection structure LH1, and a plurality of line segments L0 in the corresponding first type of signal line SL1 are connected as an integral structure through the first connection structure LH1 on the side close to the second frame area B2. Figure 6e As shown in the side of the last row of sub-pixels close to the first frame area B1, each first type of signal line SL1 is provided with a corresponding first connection structure LH1, and a plurality of line segments L0 in the corresponding first type of signal line SL1 are connected as an integral structure through the first connection structure LH1 on the side close to the first frame area B1.

[0140] In an example embodiment, as shown in Figure 7b , Figure 7bFor Figure 7a FIG. 6 is a schematic diagram of a planar structure of a second source-drain metal layer, an anode conductive layer, and a pixel definition layer in the display substrate of FIG. 5. The display substrate can further include a plurality of first connection structures LH1. In at least some of the plurality of first connection structures LH1, each first connection structure LH1 corresponds to one of the first-type signal lines SL1. In the second direction Y: the first connection structure LH1 can be located between two adjacent pixel openings K. In at least some of the plurality of pixel openings K, at least one first connection structure LH1 is provided on each side of the pixel opening K. In the same first-type signal line SL1, a plurality of line segments L0 located between two adjacent pixel openings K are connected to each other by the corresponding first connection structure LH1. In other words, in the region where the first-type signal line SL1 extends beyond the corresponding pixel opening K, the plurality of line segments can be connected to each other by the first connection structure LH1. This can avoid an increase in impedance of the corresponding first-type signal line SL1 caused by a disconnection of a certain line segment, and can improve display uniformity.

[0141] Figure 6d 、 Figure 6e With Figure 7b the difference is that: Figure 6d and Figure 6e in the display area AA close to one side of the frame area AA, the plurality of line segments L0 in the corresponding first-type signal line SL1 are connected by the first connection structure LH1. Figure 7b In the structure shown in FIG. 6, the plurality of line segments L0 in the corresponding first-type signal line SL1 can be connected by the first connection structure LH1 not only on the side of the display area AA close to the frame area BB, but also on both sides of each pixel opening K in the display area AA along the second direction Y.

[0142] In an example embodiment, the at least one sub-pixel Pxij can include a pixel driving circuit, which can be located on a driving circuit layer. The at least one pixel driving circuit can include a plurality of transistors and at least one capacitor. The plurality of transistors can include at least one first-type transistor and at least one second-type transistor.

[0143] In a direction perpendicular to the plane of the substrate, the capacitor includes: a first electrode plate located on one side of the substrate, and a second electrode plate located on a side of the first electrode plate away from the substrate. The first-type transistor includes: an active layer located on a side of the first electrode plate close to the substrate, a control electrode disposed in the same layer as the first electrode plate, a first electrode and a second electrode located on a side of the control electrode away from the substrate. The second-type transistor includes: an active layer located on a side of the second electrode plate away from the substrate, a control electrode located on a side of the active layer away from the substrate, a first electrode and a second electrode located on a side of the control electrode away from the substrate. The first electrode and the second electrode of the first-type transistor are disposed in the same layer as the first electrode and the second electrode of the second-type transistor. The at least one signal line SL is located on a side of the first electrode and the second electrode away from the substrate.

[0144] In an example embodiment, the first type of transistor can be a P-type transistor, and the second type of transistor can be an N-type transistor.

[0145] In an example embodiment, as shown in Figure 5a , Figure 6a and Figure 7a , several planar structure diagrams of the pixel driving circuit shown in Figure 4 , the first type of transistor can include a fifth transistor T5 as a light-emitting control transistor, and the second type of transistor can include a first transistor T1 as a reset transistor, a second transistor T2 as a reset transistor, a third transistor T3 as a control transistor, a fourth transistor T4 as a data writing transistor, a sixth transistor T6 as a light-emitting control transistor, and a seventh transistor T7 as a reset transistor; in the same sub-pixel, in the first direction X, the fifth transistor T5, the first transistor T1, the second transistor T2, and the fourth transistor T4 are located on the same side of the third transistor T3, and in the second direction Y, the seventh transistor T7, the sixth transistor T6, the fourth transistor T4, the sixth transistor T6, the third transistor T3, and the fifth transistor T5 are arranged in sequence along the second direction Y; the capacitor in the pixel driving circuit can include a first capacitor C1 and a second capacitor C2, in the first direction X, the fifth transistor T5, the first transistor T1, the second transistor T2, and the fourth transistor T4 are located on the same side of the first capacitor C1 and the second capacitor C2, and in the second direction Y, the second capacitor C2 and the first capacitor C1 are arranged in sequence, and the orthographic projection of the third transistor T3 on the base can be located within the orthographic projection of the first capacitor C1 on the base. The connection relationship of the first transistor T1 to the seventh transistor T7, the first capacitor C1, and the second capacitor C2 can refer to the description of Figure 4 .

[0146] In an example embodiment, as shown in Figure 5b , Figure 6b , Figure 7b , the at least one signal line SL can include a plurality of first power supply lines VDD and a plurality of first initial signal connection lines Vinit1L, the at least one signal line SL extends along the second direction Y and is arranged along the first direction X; the plurality of sub-pixels Pxij includes at least a plurality of first sub-pixels P1, a plurality of second sub-pixels P2, and a plurality of third sub-pixels P3, and the plurality of sub-pixels Pxij forms a plurality of pixel units P, each pixel unit P includes at least one first sub-pixel P1, one second sub-pixel P2, and one third sub-pixel P3;

[0147] In the same pixel unit P: in the second direction Y, the pixel opening K02 of the second sub-pixel P2 and the pixel opening K03 of the third sub-pixel P3 can be arranged in sequence with intervals; in the first direction X, the pixel driving circuit of the first sub-pixel P1, the pixel driving circuit of the second sub-pixel P2, and the pixel driving circuit of the third sub-pixel P3 can be arranged in sequence, the pixel opening K02 of the second sub-pixel P2 and the pixel opening K03 of the third sub-pixel P3 can be located on the same side of the pixel opening K01 of the first sub-pixel P1, the first initial signal connection line Vinit1L can be located between the pixel driving circuit of the second sub-pixel P1 and the pixel driving circuit of the third sub-pixel P2, and in the region corresponding to the pixel opening K02 of the second sub-pixel P2 and the pixel opening K03 of the third sub-pixel P3, the two first power lines VDD in the second sub-pixel P2 and the third sub-pixel P3 are symmetrical with respect to the first initial signal connection line Vinit1L.

[0148] In Figure 5a 、 Figure 6a 、 Figure 7a In the structure shown in the structure, the pixel driving circuits of the plurality of sub-pixels can form a plurality of columns, Figure 5a 、 Figure 6a 、 Figure 7a The Nth to (N+5)th columns of pixel driving circuits in the Mth row of sub-pixels are shown.

[0149] In an exemplary embodiment, as shown in Figure 5b 、 Figure 6b 、 Figure 7b The at least one signal line SL can also include a plurality of first second initial signal connection lines Vinit2L-B and a plurality of second power lines VSS.

[0150] The first second initial signal line Vinit2L-B can be located at the pixel driving circuit of the first sub-pixel P1, and each sub-pixel P1 is provided with one second power line VSS, and in the same pixel unit P: in the region corresponding to the pixel opening K01 of the first sub-pixel P1, the first second initial signal line Vinit2L-B and the second power line VSS in the first sub-pixel P1 are symmetrical with respect to the third center line Q3-Q3, and the third center line Q3-Q3 (as shown in Figure 7a The first second initial signal line Vinit2L-B can be located at the pixel driving circuit of the first sub-pixel P1, and each sub-pixel P1 is provided with one second power line VSS, and in the same pixel unit P: in the region corresponding to the pixel opening K01 of the first sub-pixel P1, the first second initial signal line Vinit2L-B and the second power line VSS in the first sub-pixel P1 are symmetrical with respect to the third center line Q3-Q3, and the third center line Q3-Q3 (as shown in

[0151] In an exemplary embodiment, as shown in Figure 5a 、 Figure 6a 、 Figure 7aAs shown, the display substrate can further include a plurality of anode connection electrodes ZL, a plurality of data signal lines DL, and a plurality of anodes AN, the plurality of anodes AN can be located between the driving circuit layer and the pixel opening K in a direction perpendicular to the plane of the display substrate, the plurality of anode connection electrodes ZL and the plurality of anodes AN can correspond one-to-one, the sub-pixel Pxij can further include at least one anode AN connection electrode ZL and at least one anode AN, in the same sub-pixel Pxij, the pixel driving circuit is electrically connected to the corresponding anode AN through the corresponding anode connection electrode ZL; the at least one signal line SL can further include a plurality of anode connection electrodes ZL;

[0152] In the same pixel unit P: in the region corresponding to the pixel opening K01 of the first sub-pixel P1, the data signal line DL and the anode connection electrode ZL of the first sub-pixel P1 are symmetrical with respect to the third median line Q3-Q3, in the first direction X, the data signal line DL can be located on the side of the first second initial signal connection line Vinit2L-B away from the second power supply line VSS, and the anode connection electrode ZL of the first sub-pixel P1 can be located on the side of the second power supply line VSS away from the first second initial signal connection line Vinit2L-B.

[0153] In the exemplary embodiments, as shown in Figure 5a , Figure 6a , Figure 7a In the same pixel unit P: in the region corresponding to the anode AN2 of the second sub-pixel P2, the anode connection electrodes ZL in the second sub-pixel P2 and the third sub-pixel P3 can be symmetrical with respect to the first initial signal connection line Vinit2L-B; in the first direction X, in any one of the sub-pixels Pxij of the second sub-pixel P2 and the third sub-pixel P2, the anode connection electrode ZL is located on the side of the first power supply line VDD away from the first initial signal connection line Vinit2L-B, for example, in the first direction X, in the second sub-pixel P2, the anode connection electrode ZL is located on the side of the first power supply line VDD away from the first initial signal connection line Vinit2L-B, and in the third sub-pixel P2, the anode connection electrode ZL is located on the side of the first power supply line VDD away from the first initial signal connection line Vinit2L-B.

[0154] In the exemplary embodiments, as shown in Figure 5a , Figure 5c , Figure 6a , Figure 7a The at least one signal line SL can include a plurality of first type signal lines SL1 and a plurality of second type signal lines SL2, as shown in Figure 5c In the first direction X, the size f1 of the first type signal line SL1 is greater than the size f2 of the second type signal line SL2.

[0155] In an example embodiment, as shown in Figure 5a , Figure 6a , Figure 7a The plurality of first type signal lines SL1 can include a first second initial signal line Vinit2L-B and a second power supply line VSS in the pixel driving circuit of the first sub-pixel P1, and a first power supply line VDD in the pixel driving circuit of the second sub-pixel P2 and the pixel driving circuit of the third sub-pixel P3. The plurality of second type signal lines SL2 can include a data signal line DL and an anode connecting electrode ZL in the pixel driving circuit of the first sub-pixel P1, and a first initial signal connecting line Vinit1L between the pixel driving circuit of the second sub-pixel P2 and the pixel driving circuit of the third sub-pixel P3.

[0156] As shown in Figure 6b , Figure 6c and Figure 7b The region corresponding to the pixel opening K of the first type signal line SL1 can be provided as a hollow structure LK, which can divide the first type signal line SL1 into a plurality of lines L0 arranged at intervals along the first direction X. In the region corresponding to the same pixel opening K, the size w1 of the plurality of lines L0 in the first direction X is consistent with the size w2 of the second type signal line SL. In the same sub-pixel, the flatness of the anode away from the base side can be improved, and the color deviation asymmetry can be reduced to a certain extent.

[0157] In an example embodiment, as shown in Figure 5a , Figure 6a , Figure 7a The display substrate can further include a plurality of second power supply connecting lines VSSL, which can extend along the first direction X, and the second power supply connecting lines VSSL can be provided in the same layer as the first electrode and the second electrode.

[0158] As shown in Figure 6a , Figure 7a The plurality of second power supply lines VSS and the plurality of second power supply connecting lines VSSL are connected to each other through a second power supply via hole KVSS to form a grid-like structure, which can reduce the voltage drop of the second power supply line VSS. The pixel opening K01 of the first sub-pixel P has an overlapping region with the second power supply via hole KVSS. In the region corresponding to the first pixel opening K01, the size of the line L0 in the second power supply connecting line VSSL along the first direction X at the position of the second power supply via hole KVSS is greater than the size along the first direction at the position without the second power supply via hole KVSS.

[0159] In an example embodiment, as shown in Figure 6a , Figure 7aAs shown, in the same sub-pixel Pxij, a plurality of anode vias KAN are provided, which can include a first anode via KAN1 and a second anode via KAN2. The anode connection electrode ZL is electrically connected to the corresponding pixel driving circuit through the first anode via KAN1, and is electrically connected to the corresponding anode AN through the second anode via KAN2. The first type of signal line SL1 can be bent away from the anode via KAN at the position adjacent to the line L0 of the anode via KAN in a direction away from the anode via KAN.

[0160] In an exemplary embodiment, in the same pixel unit P: in the second power supply line VSS corresponding to the anode AN1 of the first sub-pixel P1, at least one line L0 in the second power supply line VSS corresponding to the position of the anode via KAN in the first sub-pixel P1 is bent in a direction away from the corresponding anode via KAN in the first direction X, and is combined with the line L0 of the second power supply line VSS away from the corresponding anode via KAN; in the first power supply line VDD corresponding to the anode AN2 of the second sub-pixel P2, at least one line L0 in the first power supply line VDD corresponding to the position of the anode via KAN in the second sub-pixel P1 is bent in a direction away from the corresponding anode via KAN in the first direction X, and is combined with the line L0 of the first power supply line VDD away from the corresponding anode via KAN.

[0161] In an exemplary embodiment, Figure 5c to Figure 5f 、 Figure 6c The direction represented by Z is the direction perpendicular to the plane on which the substrate is located.

[0162] The following is an exemplary description of the preparation process of the display substrate. The "patterning process" of the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development, etc. for organic materials. Deposition can use any one or more of sputtering, evaporation, chemical vapor deposition, coating can use any one or more of spraying, spin coating and inkjet printing, etching can use any one or more of dry etching and wet etching, and the present disclosure does not limit. "Thin film" refers to a layer of film made of a certain material on a substrate (or substrate) using deposition, coating or other processes. If the "thin film" does not need to be patterned during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs to be patterned during the entire manufacturing process, it is called "thin film" before the patterning process, and it is called "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are disposed in the same layer" of the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0163] In an exemplary embodiment, taking six sub-pixels (1 sub-pixel row, six sub-pixel columns, pixel driving circuit using 7T2C structure as shown in FIG. 7) in the display area (AA) as an example, the preparation process of a display substrate can include the following operations: Figure 4

[0164] ​(101) A substrate is prepared on a glass carrier. In an exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also called barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an exemplary embodiment, taking the laminated structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing into a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing into a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0165] (102) A first semiconductor layer pattern is formed. In an exemplary embodiment, forming the first semiconductor layer pattern can include: depositing a first semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form the first semiconductor layer pattern, as shown in Figure 8 Figure 8 The planar schematic view after the six sub-pixels form the first semiconductor layer is shown.

[0166] In an exemplary embodiment, the first semiconductor layer pattern in at least part of the sub-pixels at least includes an active layer AT5 of a fifth transistor T5.

[0167] In an exemplary embodiment, the shape of the active layer AT5 of the fifth transistor T5 can be an "L" shape.

[0168] ​In an exemplary embodiment, the active layer of at least some of the transistors may include a first region, a second region, and a channel region located between the first region and the second region. The first region AT51 and the second region AT52 of the active layer AT5 of the fifth transistor T5 may be separately provided.

[0169] In an exemplary embodiment, pixel driving circuits of multiple sub-pixels are formed in multiple rows and multiple columns, and multiple pixel driving circuits form multiple circuit units. In the pixel driving circuits of the same row, three adjacent pixel driving circuits may constitute a circuit unit, and multiple circuit units may form multiple rows and multiple columns.

[0170] In an exemplary embodiment, in the circuit units of the same row, the first semiconductor layer in the two closest pixel driving circuits of two adjacent circuit units is mirror symmetric with respect to a first center line. The first center line may be a straight line along which two adjacent circuit units extend in the second direction Y. Taking the pixel driving circuits of M rows as an example: three pixel driving circuits, namely the pixel driving circuit of the Nth column, the pixel driving circuit of the N + 1th column, and the pixel driving circuit of the N + 2th column, constitute a circuit unit; three pixel driving circuits, namely the pixel driving circuit of the N + 3th column, the pixel driving circuit of the N + 4th column, and the pixel driving circuit of the N + 5th column, constitute another circuit unit. The two closest pixel driving circuits of two adjacent circuit units are the pixel driving circuit of the N + 2th column and the pixel driving circuit of the N + 3th column. The first semiconductor layer in the pixel driving circuit of the N + 2th column and the first semiconductor layer in the pixel driving circuit of the N + 3th column may be symmetric with respect to the first center line between the pixel driving circuit of the N + 2th column and the pixel driving circuit of the N + 3th column.

[0171] In an exemplary embodiment, the active layers AT5 of the two closest fifth transistors T5 in two adjacent circuit units are connected to each other to form a "Ji" - shaped structure. For example, in the pixel driving circuits of the Mth row, the active layer AT5 of the fifth transistor T5 in the pixel driving circuit of the N + 2th column is connected to the active layer AT5 of the fifth transistor T5 in the pixel driving circuit of the N + 2th column to form a "Ji" - shaped structure.

[0172] In an exemplary embodiment, a pixel driving circuit of a first sub - pixel, a pixel driving circuit of a second sub - pixel, and a pixel driving circuit of a third sub - pixel may be included in the same circuit unit.

[0173] In an exemplary embodiment, the first semiconductor layer can adopt polycrystalline silicon (p-Si), i.e., the fifth transistor T5 can be an LTPS thin film transistor. In an exemplary embodiment, the patterning of the first semiconductor thin film by the patterning process can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment, and forming a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the first semiconductor layer pattern.

[0174] (103) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: sequentially depositing a first insulating thin film and a first conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the first conductive thin film by a patterning process to form a first conductive layer pattern covering the first semiconductor layer pattern, as shown in Figure 9a and Figure 9b , Figure 9a is a planar structure schematic diagram of six sub-pixels after forming the first conductive layer, Figure 9b is Figure 9a a planar schematic diagram of the first conductive layer in

[0175] In an exemplary embodiment, the first conductive layer pattern can at least include: a first plate C11 of a first capacitor C1, a first plate C21 of a second capacitor C2, a first second initial signal line Vinit2-B, and a control electrode T5g of the fifth transistor T5.

[0176] In an exemplary embodiment, the first second initial signal line Vinit2-B can have a polyline structure or a strip structure extending along the first direction X; in the same sub-pixel, in the second direction Y, the first second initial signal line Vinit2-B can be located on the side of the first plate C21 of the second capacitor C2 away from the first plate C11 of the first capacitor C1.

[0177] In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can have a block structure, and the shape of the block structure can be a polygon, for example, can be approximately a rectangular structure. In an exemplary embodiment, in the same sub-pixel, in the second direction Y, the first plate C21 of the second capacitor C2 and the first plate C11 of the first capacitor C1 can be arranged in sequence.

[0178] In an exemplary embodiment, the first plate C11 of the first capacitor C1 can be provided with a first connecting portion CL1, the first connecting portion CL1 is configured to accommodate a twelfth via hole formed subsequently, the orthogonal projection of the twelfth via hole on the substrate is within the range of the orthogonal projection of the first connecting portion CL1 on the substrate, and exposes the surface of the first connecting portion CL1, so that the second electrode of the first transistor T1 formed subsequently is connected with the first plate C11 of the first capacitor C1 through the twelfth via hole and the first connecting portion CL1.

[0179] In an exemplary embodiment, the first plate C21 of the second capacitor C2 can be provided with a second connecting portion CL2, the second connecting portion CL2 is configured to accommodate a thirteenth via hole formed subsequently, the orthogonal projection of the thirteenth via hole on the substrate is within the range of the orthogonal projection of the second connecting portion CL2 on the substrate, and exposes the surface of the second connecting portion CL2, so that the second electrode of the second transistor T2 and the second electrode of the fourth transistor T4 formed subsequently are connected with the first plate C21 of the second capacitor C2 through the thirteenth via hole and the second connecting portion CL2.

[0180] Taking the Mth row and the Nth column sub-pixel as an example: in the second direction Y, the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 in the same sub-pixel close to the M-1th row sub-pixel, and the control electrode T5g of the fifth transistor T5 can be located on the main part of the first plate C11 of the first capacitor C1 in the same sub-pixel close to the M-1th row sub-pixel; in the first direction X, the control electrode T5g of the fifth transistor T5 is located on at least part of the structure of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 close to the N-1th column sub-pixel.

[0181] In an exemplary embodiment, the control electrode T5g of the fifth transistor T5 at least partially overlaps the active layer AT5 of the fifth transistor T5, for example, the control electrode T5g of the fifth transistor T5 overlaps the channel region of the active layer AT5 of the fifth transistor T5. In the same sub-pixel, in the first direction X, the control electrode T5g of the fifth transistor T5 can be located on one side of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2, and in the second direction Y, the control electrode T5g of the fifth transistor T5 can be located on the side of the first connecting portion CL1 away from the first plate C21 of the second capacitor C2.

[0182] In an exemplary embodiment, in the same row of circuit units, the first conductive layer in the first two pixel driving circuits of two adjacent circuit units can be mirror-symmetrical relative to the first center line, for example, the first conductive layer in the N+2th column of pixel driving circuits and the first conductive layer in the N+3th column of pixel driving circuits can be symmetrical relative to the first center line between the N+2th column of pixel driving circuits and the N+3th column of pixel driving circuits.

[0183] In an exemplary embodiment, after the first conductive layer pattern is formed, the first semiconductor layer can be conductorized using the first conductive layer as a shield. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the fifth transistor T5, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, i.e., the first and second regions of the active layer AT5 of the fifth transistor T5 are both conductorized.

[0184] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a second insulating film and a second conductive film on the substrate on which the aforementioned patterns are formed, patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer and a second conductive layer pattern disposed on the second insulating layer, as shown in Figure 10a to Figure 10b Figure 10a for the planar structure of the six sub-pixels after the second conductive layer is formed, Figure 10b Figure 10a for the planar schematic diagram of the second conductive layer. In an exemplary embodiment, the second conductive layer can be referred to as the second gate metal (GATE2) layer.

[0185] In an exemplary embodiment, the second conductive layer pattern can include at least: a second plate C12 of the first capacitor C1, a second plate C22 of the second capacitor C2, and a third connection portion CL3.

[0186] ​​In an example embodiment, the profile of the second plate C12 of the first capacitor C1 can be consistent with the profile of the first plate C11 of the first capacitor C1, the profile of the second plate C22 of the second capacitor C2 can be consistent with the profile of the first plate C21 of the second capacitor C2, for example, the profile of the second plate C12 of the first capacitor C1 and the profile of the second plate C22 of the second capacitor C2 can be polygonal (such as rectangular). In an example embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate, for example, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate can cover the orthographic projection of the main part of the first plate C11 of the first capacitor C1 on the substrate, the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate can cover the orthographic projection of the main part of the first plate C21 of the second capacitor C2 on the substrate. In an example embodiment, the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0187] In an example embodiment, the second plate C22 of the second capacitor C2 is provided with a receiving opening K0, the orthographic projection of the receiving opening K0 on the substrate at least partially overlaps with the second connecting portion CL2, the receiving opening K0 is arranged to accommodate the thirteenth via hole formed subsequently, the orthographic projection of the thirteenth via hole on the substrate is within the range of the orthographic projection of the receiving opening K0 on the substrate, and exposes the surface of the second connecting portion CL2, so that the second electrode of the second transistor T2 and the second electrode of the fourth transistor T4 formed subsequently are connected with the first plate C21 of the second capacitor C2 through the thirteenth via hole and the second connecting portion CL2.

[0188] In an example embodiment, in the same sub-pixel, the second plate C22 of the second capacitor C2, the second plate C12 of the first capacitor C1 can be arranged in sequence in the second direction Y, the second plate C22 of the second capacitor C2 can be connected with the second plate C12 of the first capacitor C1 through the third connecting portion CL3, in an example embodiment, the second plate C22 of the second capacitor C2, the third connecting portion CL3, and the second plate C12 of the first capacitor C1 can be integrally formed.

[0189] In an example embodiment, the first plate C11 of the first capacitor C1 can shield the channel of the third transistor T3, and ensure the electrical performance of the oxide third transistor T3.

[0190] In an example embodiment, in the same row of circuit units, the second conductive layers in the two pixel driving circuits closest to the two adjacent circuit units can be mirror symmetrical with respect to the first center line, for example, the second conductive layer in the N+2th column of pixel driving circuits and the second conductive layer in the N+3th column of pixel driving circuits can be symmetrical with respect to the first center line between the N+2th column of pixel driving circuits and the N+3th column of pixel driving circuits.

[0191] (105) Forming a second semiconductor layer pattern. In an example embodiment, forming a second semiconductor layer pattern can include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a third insulating thin film and a second semiconductor thin film, patterning the semiconductor thin film through a patterning process, forming a third insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the second insulating layer, as shown in Figure 11a to Figure 11b Figure 11a a planar structure diagram of six sub-pixels after forming the second semiconductor layer, Figure 11b Figure 11a a planar schematic diagram of the semiconductor layer in the middle.

[0192] In an example embodiment, the second semiconductor layer pattern in at least part of the sub-pixels at least includes: an active layer AT1 of the first transistor T1, an active layer AT2 of the second transistor T2, an active layer AT3 of the third transistor T3, an active layer AT4 of the fourth transistor T4, an active layer AT6 of the sixth transistor T6, and an active layer AT7 of the seventh transistor T7.

[0193] In an example embodiment, in the same sub-pixel, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be connected to each other, for example, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be an integrated structure connected to each other.

[0194] ​​In the exemplary embodiments, in the same sub-pixel, in the first direction X, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, and the active layer AT5 of the fifth transistor T5 can be located on the same side of the active layer AT3 of the third transistor T3; in the second direction Y, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT3 of the third transistor T3 can be located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT7 of the seventh transistor T7, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, and the active layer AT6 of the sixth transistor T6 can be located between the active layer AT5 of the fifth transistor T5 and the active layer AT7 of the seventh transistor T7, the active layer AT2 of the second transistor T2 can be located between the active layer AT1 of the first transistor T1 and the active layer AT4 of the fourth transistor T4, and the active layer AT3 of the third transistor T3 can be located on the side of the active layer AT1 of the first transistor T1 away from the active layer AT2 of the second transistor T2.

[0195] In the exemplary embodiments, taking the sub-pixel in the Mth row and the Nth column as an example for description: in the first direction X, the active layer of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, and the active layer AT5 of the fifth transistor T5 can be located on the side of the active layer AT3 of the third transistor T3 away from the sub-pixel in the N+1th column; in the second direction Y, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT3 of the third transistor T3 can be located on the side of the active layer AT6 of the sixth transistor T6 close to the sub-pixel in the M-1th row, the active layer AT1 of the first transistor T1 can be located on the side of the active layer AT2 of the second transistor T2 away from the sub-pixel in the M+1th row, the active layer AT4 of the fourth transistor T4 can be located on the side of the active layer AT2 of the second transistor T2 close to the sub-pixel in the M+1th row, the active layer AT5 of the fifth transistor T5 and the active layer AT3 of the third transistor T3 can be located on the side of the active layer AT6 of the sixth transistor T6 away from the sub-pixel in the M+1th row, and the active layer AT7 of the seventh transistor T7 can be located on the side of the active layer AT6 of the sixth transistor T6 close to the sub-pixel in the M+1th row.

[0196] In the example embodiment, the active layers AT1, AT2, AT4, and AT6 of the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 can be in an "I" shape or a strip shape, and the active layer AT3 of the third transistor T3 can be in a "middle" shape or a strip shape or a broken line shape extending in the second direction Y.

[0197] In the example embodiment, the active layers of the at least some transistors can include a first region, a second region, and a channel region between the first region and the second region. In the example embodiment, the first region AT11 of the active layer AT1 of the first transistor T1 can serve as the first region AT21 of the active layer AT2 of the second transistor T2, the second region AT22 of the active layer AT2 of the second transistor T2 can serve as the second region AT42 of the active layer AT4 of the fourth transistor T4, and the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT72 of the active layer AT7 of the seventh transistor T7. The second region AT12 of the active layer AT1 of the first transistor T1, the first region AT31 and the second region AT32 of the active layer AT3 of the third transistor T3, the first region AT41 of the active layer AT4 of the fourth transistor T4, the first region AT61 of the active layer AT6 of the sixth transistor T6, and the first region AT71 of the active layer AT7 of the seventh transistor T7 can be separately provided.

[0198] In the example embodiment, the second semiconductor layer can be an oxide, i.e., the first transistor T1 to the fourth transistor T4 and the sixth transistor T6 to the seventh transistor T7 are oxide thin film transistors. In the example embodiment, the oxide can be any one or more of indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0199] (106) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: on the substrate on which the aforementioned patterns are formed, sequentially depositing a fourth insulating thin film and a third conductive thin film, patterning the third conductive thin film by using a patterning process, forming a fourth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the third insulating layer, as shown in Figure 12a to Figure 12b Figure 12a for a planar structure of six sub-pixels after forming the third conductive layer, Figure 12b Figure 12a for a planar schematic diagram of the third conductive layer. In an exemplary embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0200] In an exemplary embodiment, the third conductive layer pattern at least includes: a second reset control line Reset2, a second emission control line EM2, a third reset control line Reset3, a control electrode T1g of a first transistor T1, a control electrode T3g of a third transistor T3, and a control electrode T4g of a fourth transistor T4.

[0201] In an exemplary embodiment, the second emission control line EM2 can be a polyline or a strip shape extending along the first direction X in the body portion, in the same row of sub-pixels, in the second direction Y, the second reset control line Reset2 and the third reset control line Reset3 can be located on both sides of the second emission control line EM2, the control electrode T3g of the third transistor T3 can be located on the side of the control electrode T1g of the first transistor T1 away from the third reset control line Reset3, and the control electrode T4g of the fourth transistor T4 can be located between the second reset control line Reset2 and the third reset control line Reset3; in the first direction X, the control electrode T4g of the fourth transistor T4 and the control electrode T1g of the first transistor T1 can be located on the same side of the control electrode T3g of the third transistor T3; taking the Mth row and the Nth column of sub-pixels as an example: in the second direction Y, the control electrode T1g of the first transistor T1 can be located on the side of the third reset control line Reset3 away from the M+1th row of sub-pixels, the control electrode T3g of the third transistor T3 can be located on the side of the control electrode T1g of the first transistor T1 away from the M+1th row of sub-pixels, the control electrode T4g of the fourth transistor T4 can be located on the side of the third reset control line Reset3 close to the M+1th row of sub-pixels, the second emission control line EM2 can be located on the side of the control electrode T4g of the fourth transistor T4 close to the M+1th row of sub-pixels, and the second reset control line Reset2 can be located on the side of the second emission control line EM2 close to the M+1th row of sub-pixels; in the first direction X, the control electrode T4g of the fourth transistor T4 and the control electrode T1g of the first transistor T1 can be located on the side of the control electrode T3g of the third transistor T3 close to the N-1th column of sub-pixels. ​​

[0202] In the example embodiment, the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the control electrode T6g of the sixth transistor T6.

[0203] In the example embodiment, the orthogonal projection of the control electrode T1g of the first transistor T1 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT1 of the first transistor T1 on the substrate; the orthogonal projection of the control electrode T3g of the third transistor T3 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT3 of the third transistor T3 on the substrate; and the orthogonal projection of the control electrode T4g of the fourth transistor T4 on the substrate at least partially overlaps with the orthogonal projection of the active layer AT4 of the fourth transistor T4 on the substrate.

[0204] In the example embodiment, after forming the third conductive layer pattern, the second semiconductor layer can be subjected to a conductorization process using the third conductive layer as a shield. The second semiconductor layer in the region shielded by the third conductive layer forms the channel region of the first transistor T1 to the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7. The semiconductor layer in the region not shielded by the third conductive layer is conductorized, i.e., the active layer AT1 of the first transistor T1 to the active layer AT4 of the fourth transistor T4, the first region and the second region of the active layer AT6 of the sixth transistor T6 are all conductorized.

[0205] (107) Forming a fifth insulating layer pattern. In the example embodiment, forming the fifth insulating layer pattern can include: depositing a fifth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating thin film using a patterning process to form a fifth insulating layer covering the third conductive layer, the fifth insulating layer being provided with a plurality of vias, as shown in Figure 13 . Figure 13 A planar structure diagram of the six sub-pixels after forming the fifth insulating layer.

[0206] In the example embodiment, the plurality of vias in at least some of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, and a twentieth via V20.

[0207] In an example embodiment, the first via V1 is located within the footprint of the active layer AT1 of the first transistor T1 on the substrate, the fifth insulating layer and the fourth insulating layer within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1 (also the surface of the first region AT21 of the active layer AT2 of the second transistor T2). The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to connect to the active layer AT1 of the first transistor T1 through the via, and the first electrode of the subsequently formed second transistor T2 to connect to the active layer AT2 of the second transistor T2 through the via.

[0208] In an example embodiment, the second via V2 is located within the footprint of the active layer AT1 of the first transistor T1 on the substrate, the fifth insulating layer and the fourth insulating layer within the second via V2 are etched away, exposing the surface of the second region AT12 of the active layer AT1 of the first transistor T1. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to connect to the active layer AT1 of the first transistor T1 through the via.

[0209] In an example embodiment, the third via V3 is located within the footprint of the active layer AT2 of the second transistor T2 on the substrate, the fifth insulating layer and the fourth insulating layer within the third via V3 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2 (also the surface of the second region AT42 of the active layer AT4 of the fourth transistor T4). The third via V3 is configured to allow the second electrode of the subsequently formed second transistor T2 to connect to the active layer AT2 of the second transistor T2 through the via, and the second electrode of the subsequently formed fourth transistor T4 to connect to the active layer AT4 of the fourth transistor T4 through the via.

[0210] In an example embodiment, the fourth via V4 is located within the footprint of the active layer AT3 of the third transistor T3 on the substrate, the fifth insulating layer and the fourth insulating layer within the fifth via V5 are etched away, exposing the surface of the first region AT31 of the active layer AT3 of the third transistor T3. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor T3 to connect to the active layer AT3 of the third transistor T3 through the via.

[0211] In the example embodiment, the fifth via V5 is configured such that the second electrode of the third transistor T3 to be formed later is connected to the active layer AT3 of the third transistor T3 through the via. The normal projection of the fifth via V5 on the substrate is located within the range of the normal projection of the active layer AT3 of the third transistor T3 on the substrate. The fifth insulating layer, the fourth insulating layer within the fifth via V5 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3.

[0212] In the example embodiment, the sixth via V6 is configured such that the first electrode of the fourth transistor T4 to be formed later is connected to the active layer AT4 of the fourth transistor T4 through the via. The normal projection of the sixth via V6 on the substrate is located within the range of the normal projection of the active layer AT4 of the fourth transistor T4 on the substrate. The fifth insulating layer, the fourth insulating layer within the sixth via V6 are etched away, exposing the surface of the first region AT41 of the active layer AT4 of the fourth transistor T4.

[0213] In the example embodiment, the seventh via V7 is configured such that the second electrode of the fourth transistor T4 to be formed later is connected to the active layer AT4 of the fourth transistor T4 through the via. The normal projection of the seventh via V7 on the substrate is located within the range of the normal projection of the active layer AT4 of the fourth transistor T4 on the substrate. The fifth insulating layer, the fourth insulating layer within the seventh via V7 are etched away, exposing the surface of the second region AT42 of the active layer AT4 of the fourth transistor T4.

[0214] In the example embodiment, the seventh via V7 is configured such that the second electrode of the fifth transistor T5 to be formed later is connected to the active layer AT5 of the fifth transistor T5 through the via. The normal projection of the seventh via V7 on the substrate is located within the range of the normal projection of the active layer AT5 of the fifth transistor T5 on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, the first insulating layer within the seventh via V7 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5.

[0215] In the example embodiment, the eighth via V8 is configured such that the second electrode of the fifth transistor T5 to be formed later is connected to the active layer AT5 of the fifth transistor T5 through the via. The normal projection of the eighth via V8 on the substrate is located within the range of the normal projection of the active layer AT5 of the fifth transistor T5 on the substrate. The fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, the first insulating layer within the eighth via V8 are etched away, exposing the surface of the second region AT52 of the active layer AT5 of the fifth transistor T5.

[0216] In the exemplary embodiment, the ninth via V9 is configured such that the first electrode of the sixth transistor T6 to be formed later is connected to the active layer AT6 of the sixth transistor T6 through the via.

[0217] In the exemplary embodiment, the tenth via V10 is configured such that the second electrode of the sixth transistor T6 to be formed later is connected to the active layer AT6 of the sixth transistor T6 through the via, and the second electrode of the seventh transistor T7 to be formed later is connected to the active layer AT7 of the seventh transistor T7 through the via.

[0218] In the exemplary embodiment, the eleventh via V11 is configured such that the first electrode of the seventh transistor T7 to be formed later is connected to the active layer AT7 of the seventh transistor T7 through the via.

[0219] In the exemplary embodiment, the twelfth via V12 is configured such that the second electrode of the first transistor T1 to be formed later is connected to the first plate C11 of the first capacitor C1 through the via.

[0220] In the exemplary embodiment, the thirteenth via V13 is located within the range of the orthogonal projection of the first plate C21 of the second capacitor C2 on the substrate (the thirteenth via V13 can be located within the range of the orthogonal projection of the second connection portion CL2 on the substrate), the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the thirteenth via V13 are etched to expose the surface of the first plate C21 of the second capacitor C2. The thirteenth via V13 is configured to connect the second electrode of the second transistor T2 and the second electrode of the fourth transistor T4 formed subsequently to the first plate C21 of the second capacitor C2 through the via.

[0221] In the exemplary embodiment, the fourteenth via V14 is located within the range of the orthogonal projection of the first second initial signal line Vinit2-B on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the fourteenth via V14 are etched to expose the surface of the first second initial signal line Vinit2-B. The fourteenth via V14 is configured to connect the first electrode of the seventh transistor T7 in the first sub-pixel formed subsequently to the first second initial signal line Vinit2-B through the via. In the exemplary embodiment, the fourteenth via V14 can be provided in the first sub-pixel, and the second sub-pixel and the third sub-pixel can not be provided with the fourteenth via V14.

[0222] In the exemplary embodiment, the fifteenth via V15 is located within the range of the orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate, the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the fifteenth via V15 are etched to expose the surface of the second plate C12 of the first capacitor C1. The fifteenth via V15 is configured to connect the second electrode of the third transistor T3 formed subsequently to the second plate C12 of the first capacitor C1 through the via.

[0223] In the exemplary embodiment, the sixteenth via V16 is located within the range of the orthogonal projection of the second plate C22 of the second capacitor C2 on the substrate, the fifth insulating layer, the fourth insulating layer, and the third insulating layer in the sixteenth via V16 are etched to expose the surface of the second plate C22 of the second capacitor C2. The sixteenth via V16 is configured to connect the first electrode of the sixth transistor T6 formed subsequently to the second plate C22 of the second capacitor C2 through the via.

[0224] In the exemplary embodiment, the normal projection of the seventeenth via V17 on the substrate is within the normal projection of the control electrode T1g of the first transistor T1 on the substrate, the fifth insulating layer in the seventeenth via V17 is etched away, exposing the surface of the control electrode T1g of the first transistor T1. The seventeenth via V17 is configured to allow the first reset control line Reset1 formed subsequently to pass through the via and connect with the control electrode T1g of the first transistor T1.

[0225] In the exemplary embodiment, the normal projection of the eighteenth via V18 on the substrate is within the normal projection of the control electrode T4g of the fourth transistor T4 on the substrate, the fifth insulating layer in the eighteenth via V18 is etched away, exposing the surface of the control electrode T4g of the fourth transistor T4. The eighteenth via V18 is configured to allow the scan control line Gate formed subsequently to pass through the via and connect with the control electrode T4g of the fourth transistor T4.

[0226] In the exemplary embodiment, the normal projection of the nineteenth via V19 on the substrate is within the normal projection of the control electrode T5g of the fifth transistor T5 on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the nineteenth via V19 are etched away, exposing the surface of the control electrode T5g of the fifth transistor T5. The nineteenth via V19 is configured to allow the first emission control line EM1 formed subsequently to pass through the via and connect with the control electrode T5g of the fifth transistor T5.

[0227] In the exemplary embodiment, the normal projection of the twentieth via V20 on the substrate is within the normal projection of the control electrode T3g of the third transistor T3 on the substrate, the fifth insulating layer in the twentieth via V20 is etched away, exposing the surface of the control electrode T3g of the third transistor T3. The twentieth via V20 is configured to allow the second electrode of the first transistor T1 formed subsequently to pass through the via and connect with the control electrode T3g of the third transistor T3.

[0228] (108) Forming a fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, patterning the fourth conductive thin film using a patterning process, forming a fourth conductive layer disposed on the fifth insulating layer, as shown in Figure 14a to Figure 14b , Figure 14a is a planar structure diagram of the six sub-pixels after the fourth conductive layer is formed, Figure 14b is Figure 14a is a planar diagram of the fourth conductive layer. In the exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0229] In the exemplary embodiment, the fourth conductive layer at least includes: a second second initial signal line Vinit2-RG, a scan control line Gate, a second power connection line VSSL, a first initial signal line Vinit1, a first reset control line Reset1, a first light-emitting control line EM1, a first power connection line VDDL, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, a fifth connection electrode L5, a sixth connection electrode L6, a seventh connection electrode L7, and an eighth connection electrode L8.

[0230] In the exemplary embodiment, the main body part of the second second initial signal line Vinit2-RG, the scan control line Gate, the second power connection line VSSL, the first initial signal line Vinit1, the first reset control line Reset1, the first light-emitting control line EM1, and the first power connection line VDDL can be in a strip-shaped structure or a zigzag-shaped structure extending along the first direction X, and in the same row of sub-pixels, the second second initial signal line Vinit2-RG, the scan control line Gate, the second power connection line VSSL, the first initial signal line Vinit1, the first reset control line Reset1, the first light-emitting control line EM1, and the first power connection line VDDL can be arranged in sequence along the second direction Y.

[0231] In the exemplary embodiment, in the same sub-pixel, along the second direction Y, the first connection electrode L1, the third connection electrode L3, and the sixth connection electrode L6 can be located between the first reset control line Reset1 and the first light-emitting control line EM1, the first connection electrode L1 can be located between the third connection electrode L3 and the sixth connection electrode L6, and the third connection electrode L3 can be located between the first connection electrode L1 and the first reset control line Reset1; the second connection electrode L2, the fourth connection electrode L4, the seventh connection electrode L7, and the eighth connection electrode L8 can be located between the scan control line Gate and the second second initial signal line Vinit2-RG, the fourth connection electrode L4 and the seventh connection electrode L7 can be located on the side of the second connection electrode L2 and the eighth connection electrode L8 away from the second second initial signal line Vinit2-RG; the fifth connection electrode L5 can be located between the scan control line Gate and the second power connection line VSSL; along the first direction X, the fourth connection electrode L4 and the eighth connection electrode L8 can be located on the same side of the second connection electrode L2, the third connection electrode L3, and the seventh connection electrode L7.

[0232] In an example embodiment, the second second initial signal line Vinit2-RG can be connected with the first area AT71 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels in a row of sub-pixels through the eleventh via V1 in the second and third sub-pixels in the row, and is configured to provide the second initial signal to the seventh transistor T7 in the second and third sub-pixels in the row. In an example embodiment, the second second initial signal line Vinit2-RG can serve as the first electrode of the second transistor T2 in the second and third sub-pixels.

[0233] In an example embodiment, the scan control line Gate can be connected with the control electrode T4g of the fourth transistor T4 in a row of sub-pixels through the eighteenth via V18 in the row of sub-pixels, and is configured to provide the scan signal to the control electrode T4g of the plurality of fourth transistors T4 in the row of sub-pixels.

[0234] In an example embodiment, the main body part of the second power connection line VSSL can extend along the first direction X, and a plurality of second power connection lines VSSL are arranged at intervals along the second direction Y. The plurality of second power connection lines VSSL are connected with the plurality of second power lines formed subsequently to form a grid-shaped structure, which can reduce the voltage drop of the second power line and improve display uniformity. In an example embodiment, a plurality of shielding structures ZD are arranged on the second power connection line VSSL. The shielding structure ZD can be located in the first sub-pixel, and the orthogonal projection of the shielding structure ZD on the substrate at least partially overlaps with the orthogonal projection of the second capacitor on the substrate. The shielding structure ZD can be a strip-shaped structure or a polyline structure extending along the second direction Y. In the same first sub-pixel, the shielding structure ZD can be located on the side of the second power connection line VSSL close to the scan control line Gate in the second direction Y.

[0235] In an example embodiment, the first initial signal line Vinit1 can be connected with the first area AT11 of the active layer AT1 of the first transistor T1 (also the first area AT21 of the active layer AT2 of the second transistor T2) in a row of sub-pixels through the first via V1 in the row of sub-pixels, and is configured to provide the first initial signal to the first transistor T1 and the second transistor T2 in the row of sub-pixels. In an example embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0236] In an example embodiment, the first reset control line Reset1 can be connected with the control electrode T1g of the first transistor T1 in a row of sub-pixels through the seventeenth via V17 in the row of sub-pixels, and is configured to provide the first reset control signal to the control electrode T1g of the plurality of first transistors T1 in the row of sub-pixels.

[0237] In the example embodiment, the first light emitting control line EM1 can be connected to the control electrode T5g of the fifth transistor T5 in a row of sub-pixels through the nineteenth via V19 in the row of sub-pixels, and configured to provide a light emitting control signal to the control electrodes T5g of the plurality of fifth transistors T5 in the row of sub-pixels.

[0238] In the example embodiment, the first power connection line VDDL can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in a row of sub-pixels through the seventh via V7 in the row of sub-pixels, and configured to provide a first power signal to the active layers AT5 of the plurality of fifth transistors T5 in the row of sub-pixels. In the example embodiment, the first power connection line VDDL can be the first electrode of the fifth transistor T5.

[0239] In the example embodiment, the first connection electrode L1 has a shape of a "L" letter rotated 90° clockwise, and the first connection electrode L1 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 through the second via V2, to the first plate C11 of the first capacitor C1 (a first connection portion CL1 on the first plate C11 of the first capacitor C1) through the twelfth via V12, and to the control electrode T3g of the third transistor T3 through the twentieth via V20, the second region AT12 of the active layer AT1 of the first transistor T1, the first plate C11 of the first capacitor C1, and the control electrode T3g of the third transistor T3 can be electrically connected through the first connection electrode L1, so that the second electrode of the first transistor T1, the first plate C11 of the first capacitor C1, and the control electrode T3g of the third transistor T3 in the same sub-pixel have the same potential. In the example embodiment, the first connection electrode L1 can be the second electrode of the first transistor T1.

[0240] In the example embodiment, the second connection electrode L2 has a shape of a strip or a broken line extending in the first direction X, and the second connection electrode L2 can be connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the tenth via V10. In the example embodiment, the second connection electrode L2 can be the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the second connection electrode L2 is configured to be connected to the anode connection electrode of the light emitting element formed subsequently.

[0241] In the example embodiment, the third connection electrode L3 has a shape of a strip structure or a zigzag structure extending along the first direction X, and the third connection electrode L3 can be connected to the second region AT32 of the active layer AT3 of the third transistor T3 through the fifth via V5 and connected to the second plate C12 of the first capacitor C1 through the fifteenth via V15, so that the second region AT32 of the active layer AT3 of the third transistor T3 and the second plate C12 of the first capacitor C1 in the same sub-pixel have the same potential. In the example embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3.

[0242] In the example embodiment, the fourth connection electrode L4 has a shape of a block structure or a strip structure extending along the first direction X, and the fourth connection electrode L4 can be connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In the example embodiment, the first connection electrode L1 can serve as the first electrode of the fourth transistor T4 and be configured to be connected to a data signal line formed subsequently.

[0243] In the example embodiment, the fifth connection electrode L5 has a shape of a strip structure or a zigzag structure extending along the first direction X, and the fifth connection electrode L5 can be connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 (also the second region AT22 of the active layer AT2 of the second transistor T2) through the third via V3 and connected to the first plate C21 of the second capacitor C2 (the second connection portion CL2 on the first plate C21 of the second capacitor C2) through the thirteenth via V13, so that the second region AT22 of the active layer AT2 of the second transistor T2, the first plate C21 of the second capacitor C2 and the second region AT42 of the active layer AT4 of the fourth transistor T4 in the same sub-pixel have the same potential. In the example embodiment, the fifth connection electrode L5 can serve as the second electrode of the second transistor T2 and the second electrode of the fourth transistor T4.

[0244] In the exemplary embodiment, the sixth connection electrode L6 has a shape of a strip or a broken line extending in the first direction X, and the sixth connection electrode L6 can be connected to the second region AT52 of the active layer AT5 of the fifth transistor T5 in a row of sub-pixels through the eighth via V8 in the row of sub-pixels, and connected to the first region AT31 of the active layer AT3 of the third transistor T3 in the row of sub-pixels through the fourth via V4 in the row of sub-pixels. In the exemplary embodiment, the sixth connection electrode L6 can serve as the second electrode of the fifth transistor T5. In the same sub-pixel, the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 can be electrically connected through the sixth connection electrode L6, so that the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 in the same sub-pixel have the same electric potential.

[0245] In the exemplary embodiment, the seventh connection electrode L7 has a shape of a strip or a broken line extending in the first direction X, and the seventh connection electrode L7 can be connected to the first region AT61 of the active layer AT6 of the sixth transistor T6 through the ninth via V9, and connected to the second plate C22 of the second capacitor C2 through the sixteenth via V16. In the exemplary embodiment, the seventh connection electrode L7 can serve as the first electrode of the sixth transistor T6. In the same sub-pixel, the first region AT61 of the active layer AT6 of the sixth transistor T6 and the second plate C22 of the second capacitor C2 can be electrically connected through the seventh connection electrode L7, so that the first region AT61 of the active layer AT6 of the sixth transistor T6 and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same electric potential. Since the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are connected through the third connection portion CL3, and the second plate C12 of the first capacitor C1 is connected to the second region AT32 of the active layer AT3 of the third transistor T3 through the third connection electrode L3, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, the second region AT32 of the active layer AT3 of the third transistor T3, and the first region AT61 of the active layer AT6 of the sixth transistor T6 have the same electric potential.

[0246] In the exemplary embodiment, the eighth connection electrode L8 is substantially in the shape of a strip extending along the first direction X or a broken line, and the eighth connection electrode L8 can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the row of sub-pixels through the eleventh via V11 in the first sub-pixel in the row of sub-pixels, and connected to the first second initial signal line Vinit2-B in the row of sub-pixels through the fourteenth via V14 in the first sub-pixel in the row of sub-pixels. In the exemplary embodiment, the eighth connection electrode L8 can serve as the first electrode of the seventh transistor T7 in the first sub-pixel. In the exemplary embodiment, the eighth connection electrode L8 is arranged in the first sub-pixel, and the second sub-pixel and the third sub-pixel are not provided with the eighth connection electrode L8.

[0247] (109) Forming the sixth insulating layer and the first planar layer pattern. In the exemplary embodiment, forming the sixth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a sixth insulating thin film, then coating a first planar thin film, and patterning the first planar thin film and the sixth insulating thin film by using a patterning process to form the sixth insulating layer covering the fourth conductive layer pattern and the first planar layer arranged on the sixth insulating layer, and the sixth insulating layer and the first planar layer are provided with a plurality of vias, as shown in Figure 15 Figure 15 A plan view of the six sub-pixels after the first planar layer is formed.

[0248] In the exemplary embodiment, the plurality of vias on the sixth insulating layer and the first planar layer can at least include: the twenty-first via V21, the twenty-second via V22, the twenty-third via V23, the twenty-fourth via V24, the twenty-fifth via V25, and the twenty-sixth via V26.

[0249] In the exemplary embodiment, the orthogonal projection of the twenty-first via V21 on the substrate is within the range of the orthogonal projection of the first power connection line VDDL on the substrate, and the first planar layer and the sixth insulating layer in the twenty-first via V21 are etched away to expose the surface of the first power connection line VDDL. The twenty-first via V21 is configured to allow the first power line formed subsequently to be electrically connected to the first power connection line VDDL through the via. In the exemplary embodiment, the twenty-first via V21 can be arranged in the second sub-pixel and the third sub-pixel.

[0250] ​In an example embodiment, the second twenty-two via V22 is located within the range of the orthogonal projection of the second power connection line VSSL on the substrate, the first planar layer and the sixth insulating layer in the second twenty-two via V22 are etched away to expose the surface of the second power connection line VSSL. The second twenty-two via V22 is configured to allow the second power line formed subsequently to be electrically connected to the second power connection line VSSL through the via. In an example embodiment, the second twenty-two via V22 can be arranged in the first sub-pixel and the second sub-pixel. In an example embodiment, the second twenty-two via V22 can be used as the second power via KVSS described above.

[0251] In an example embodiment, the second twenty-three via V23 is located within the range of the orthogonal projection of the first initial signal line Vinit1 on the substrate, the first planar layer and the sixth insulating layer in the second twenty-three via V23 are etched away to expose the surface of the first initial signal line Vinit1. The second twenty-three via V23 is configured to allow the first initial signal connection line formed subsequently to be electrically connected to the first initial signal line Vinit1 through the via. In an example embodiment, the second twenty-three via V23 can be arranged between the second sub-pixel and the third sub-pixel.

[0252] In an example embodiment, the second twenty-four via V24 is located within the range of the orthogonal projection of the second second initial signal line Vinit2-RG on the substrate, the first planar layer and the sixth insulating layer in the second twenty-four via V24 are etched away to expose the surface of the second second initial signal line Vinit2-RG. The second twenty-four via V24 is configured to allow the second second initial signal connection line formed subsequently to be electrically connected to the second second initial signal line Vinit2-RG through the via. In an example embodiment, the second twenty-four via V24 can be arranged in the third sub-pixel.

[0253] In an example embodiment, the second twenty-five via V25 is located within the range of the orthogonal projection of the eighth connection electrode L8 on the substrate, the first planar layer and the sixth insulating layer in the second twenty-five via V25 are etched away to expose the surface of the eighth connection electrode L8. The second twenty-five via V25 is configured to allow the first second initial signal connection line formed subsequently to be electrically connected to the first second initial signal line Vinit2-B through the via. In an example embodiment, the second twenty-five via V25 can be arranged in the first sub-pixel.

[0254] In the exemplary embodiment, the orthogonal projection of the twenty-sixth via V26 on the substrate is located within the range of the orthogonal projection of the second connection electrode L2 on the substrate, the first planar layer and the sixth insulating layer in the twenty-sixth via V26 are etched away, and the surface of the second connection electrode L2 is exposed. The twenty-sixth via V26 is configured to allow the anode connection electrode of the light emitting element formed subsequently to pass through the via and be electrically connected to the second connection electrode L2. In the exemplary embodiment, the twenty-sixth via V26 can serve as the first anode via KAN1 described above.

[0255] (110) Forming a fifth conductive layer pattern. In the exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth conductive thin film, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in Figure 16a to Figure 16b Figure 16a is a plan view of the six sub-pixels after the fifth conductive layer is formed, Figure 16b Figure 16a is a plan view of the fifth conductive layer. In the exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0256] In the exemplary embodiment, the fifth conductive layer at least includes: a data signal line DL, a first power supply line VDD, a second power supply line VSS, an anode connection electrode ZL, a first initial signal connection line Vinit1L, a first second initial signal connection line Vinit2L-B, and a second second initial signal connection line Vinit2L-RG.

[0257] In the exemplary embodiment, the data signal line DL is a polyline or a strip shape extending along the second direction Y in the main body portion, and the data signal line DL is connected to the fourth connection electrode L4 through the twenty-first via V21. Since the fourth connection electrode L4 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection of the data signal line DL to the first electrode of the fourth transistor T4 is achieved, and the data signal is written into the fourth transistor T4. In the exemplary embodiment, in the same pixel unit, at least part of the structure of the shielding structure ZD in the first sub-pixel is located between the orthogonal projection of the second capacitor on the substrate and the orthogonal projection of the data signal line DL on the substrate in the second sub-pixel on the substrate, which can shield the signal interference of the data signal line DL in the second sub-pixel on the second capacitor C2 in the first sub-pixel to a certain extent, reduce signal crosstalk, and improve display effect.

[0258] ​​In the example embodiment, the first power supply line VDD is in a shape of a broken line or a strip extending along the second direction Y, and the first power supply line VDD is connected with the first power supply connection line VDDL through the twenty-first via V21. Since the first power supply connection line VDDL is connected with the first area AT51 of the active layer AT5 of the fifth transistor T5 through the via, the first power supply line VDD is connected with the fifth transistor T5, and the power supply signal is written into the first electrode of the fifth transistor T5.

[0259] In the example embodiment, the anode connection electrode ZL is in a shape of an "I" letter or a strip structure or a broken line structure extending along the second direction Y, and the anode connection electrode ZL is connected with the second connection electrode L2 through the twenty-sixth via V26. Since the second connection electrode L2 is connected with the second area AT62 of the active layer AT6 of the sixth transistor T6 (also the second area AT72 of the active layer AT7 of the seventh transistor T7) through the via, the anode connection electrode ZL is connected with the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0260] In the example embodiment, the first initial signal connection line Vinit1L is in a shape of a broken line or a strip extending along the second direction Y, and the first initial signal connection line Vinit1L is connected with the first initial signal line Vinit1 through the twenty-third via V23. Since the first initial signal line Vinit1 is connected with the first area AT11 of the active layer AT1 of the first transistor T1 and the first area AT21 of the active layer AT2 of the second transistor T2 through the via, the first initial signal connection line Vinit1L is connected with the first area AT11 of the active layer AT1 of the first transistor T1 and the first area AT21 of the active layer AT2 of the second transistor T2, and the initial signal is written into the first area AT11 of the active layer AT1 of the first transistor T1 and the first area AT21 of the active layer AT2 of the second transistor T2. A plurality of first initial signal connection lines Vinit1L and a plurality of first initial signal lines Vinit1 are connected with each other to form a grid structure, so that the first initial signals received by the adjacent first transistor T1 and the second transistor T2 are basically consistent, which is beneficial to improve the uniformity of the panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0261] In the example embodiment, the first second initial signal connection line Vinit2L-B can be a broken line shape or a strip shape extending along the second direction Y of the main body part, and the first second initial signal connection line Vinit2L-B can be connected to the eighth connection electrode L8 in the first sub-pixel through the twenty-fifth via V25. Since the eighth connection electrode L8 is connected to the first area AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the first second initial signal line Vinit2-B through the via, the connection of the first second initial signal connection line Vinit2L-B to the first area AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the first second initial signal line Vinit2-B is realized. The plurality of first second initial signal connection lines Vinit2L-B are connected to the plurality of first second initial signal lines Vinit2-B to form a grid-shaped structure, so that the second initial signals received by the seventh transistors T7 in the adjacent first sub-pixels are basically consistent, which is beneficial to improve the uniformity of the panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0262] In the example embodiment, the second second initial signal connection line Vinit2L-RG can be a broken line shape or a strip shape extending along the second direction Y of the main body part, and the second second initial signal connection line Vinit2L-RG can be connected to the second second initial signal line Vinit2-RG through the twenty-fourth via V24. Since the second second initial signal line Vinit2-RG is connected to the first area AT71 of the active layer AT7 of the seventh transistor T7 in the second sub-pixel and the third sub-pixel through the via, the connection of the second second initial signal connection line Vinit2L-RG to the first area AT71 of the active layer AT7 of the seventh transistor T7 in the second sub-pixel and the third sub-pixel is realized, and the initial signal is written into the first area AT71 of the active layer AT7 of the seventh transistor T7 in the second sub-pixel and the third sub-pixel. The plurality of second second initial signal connection lines Vinit2L-RG are connected to the plurality of second second initial signal lines Vinit2-RG to form a grid-shaped structure, so that the second initial signals received by the seventh transistors T7 in the adjacent second sub-pixels and third sub-pixels are basically consistent, which is beneficial to improve the uniformity of the panel display, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0263] In an exemplary embodiment, in the same pixel unit, in the first direction X, the first initial signal connection line Vinit1L can be located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel, and the signal line most adjacent to the first initial signal connection line Vinit1L on both sides is the first power line VDD, one first power line VDD is respectively arranged in the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel, one second power line VSS is respectively arranged in the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel, the second second initial signal connection line Vinit2L-RG can be located in the pixel driving circuit of the third sub-pixel, and the first second initial signal connection line Vinit2L-B can be located in the pixel driving circuit of the first sub-pixel.

[0264] In an exemplary embodiment, in the same pixel unit, in the first direction: the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the second sub-pixel, and the pixel driving circuit of the third sub-pixel are arranged in sequence, in the first sub-pixel, the data signal line DL, the first second initial signal connection line Vinit2L-B, and the second power line VSS can be arranged in sequence and spaced apart along the first direction X, and the anode connection electrode ZL can be located on the side of the second power line VSS away from the first second initial signal connection line Vinit2L-B; in the second sub-pixel, the data signal line DL, the second power line VSS, and the first power line VDD can be arranged in sequence and spaced apart along the first direction X, and the anode connection electrode ZL can be located between the second power line VSS and the first power line VDD; in the third sub-pixel, the first power line VDD and the second second initial signal connection line Vinit2L-RG can be arranged in sequence and spaced apart along the first direction X, and the anode connection electrode ZL can be located between the second second initial signal connection line Vinit2L-RG and the first power line VDD.

[0265] So far, the driving circuit layer has been prepared on the substrate, the driving circuit layer is provided with the pixel driving circuit of a plurality of sub-pixels, Figure 8 to Figure 16b The figure shows a planar structure schematic diagram of the pixel driving circuit of a sub-pixel in a display substrate. In an exemplary embodiment, in the direction perpendicular to the plane in which the display substrate is located, the driving circuit layer can include a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged in sequence on the substrate.

[0266] In the exemplary embodiment, in the direction perpendicular to the plane where the display substrate is located, the driving circuit layer can include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a first planar layer, the first insulating layer is arranged between the first semiconductor layer and the first conductive layer, the second insulating layer is arranged between the first conductive layer and the second conductive layer, the third insulating layer is arranged between the second conductive layer and the second semiconductor layer, the fourth insulating layer is arranged between the second semiconductor layer and the third conductive layer, the fifth insulating layer is arranged between the third conductive layer and the fourth conductive layer, and the sixth insulating layer and the first planar layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0267] In the exemplary embodiment, after the preparation of the driving circuit layer is completed, the light-emitting structure layer is prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer can include the following operations: forming a second planar layer pattern, the second planar layer being provided with at least an anode via hole; forming an anode pattern (i.e., an anode conductive layer), the anode being connected with the anode connecting electrode through the anode via hole; forming an anode pixel definition layer, the pixel definition layer being provided with a pixel opening, the pixel opening exposing the anode; forming an organic light-emitting layer by using an evaporation or inkjet printing process, and forming a cathode on the organic light-emitting layer; forming an encapsulation layer, the encapsulation layer can include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer which are stacked, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, so as to ensure that external water vapor cannot enter the light-emitting structure layer. The steps of preparing the light-emitting structure layer are as follows:

[0268] (111) Forming a second planar layer pattern. In the exemplary embodiment, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, and patterning the second planar film by using a patterning process to form a second planar layer covering the fifth conductive layer pattern, the second planar layer being provided with a plurality of via holes, as shown in FIG. 11B. Figure 17 Figure 17 A planar structure diagram of the six sub-pixels after the second planar layer is formed.

[0269] In the exemplary embodiment, the plurality of via holes can at least include a twenty-seventh via hole V27.

[0270] In the exemplary embodiment, the via hole of each sub-pixel at least includes the twenty-seventh via hole V27. The orthogonal projection of the twenty-seventh via hole V27 on the substrate is within the range of the orthogonal projection of the anode connecting electrode ZL on the substrate, the second planar layer in the twenty-seventh via hole V27 is removed to expose the surface of the anode connecting electrode ZL, and the twenty-seventh via hole V27 is configured to enable the subsequently formed anode to be electrically connected with the anode connecting electrode ZL through the via hole.

[0271] ​In an example embodiment, the twenty-seventh via V27 can serve as the second anode via KAN2 described above.

[0272] (112) Forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the pattern is formed, patterning the anode conductive thin film using a patterning process, and forming the anode conductive layer pattern disposed on the second planar layer, as shown in Figure 18a to and Figure 18b as shown, Figure 18a is a plan view of the six sub-pixels after forming the anode conductive layer, Figure 18b is Figure 18a is a plan view of the anode conductive layer in

[0273] In an example embodiment, the anode conductive layer pattern can include at least a plurality of anodes AN, which can include: a first anode AN1, a second anode AN2, and a third anode AN3. The region where the first anode AN1 is located can form a blue light emitting unit that emits blue light, the region where the second anode AN2 is located can form a green light emitting unit that emits green light, and the region where the third anode AN3 is located can form a red light emitting unit that emits red light.

[0274] In an example embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connection electrode ZL in the corresponding sub-pixel through the twenty-seventh via V27, respectively. Since the anode connection electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the seventh transistor T7) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connection electrode ZL, respectively, realizing that the pixel driving circuit drives the light emitting device to emit light.

[0275] In an example embodiment, the anode AN can include an anode main body part AN01 and an anode connection part AN02. The anode main body part AN01 can have a rectangular structure, and the anode connection part AN02 has one end connected to the anode main body part AN01 and the other end electrically connected to the anode connection electrode ZL through the twenty-seventh via V27. The anode connection part AN02 can have a strip-shaped structure or a block-shaped structure extending in the first direction X or the second direction Y. The anode connection part AN02 can be arranged to compensate for the difference in parasitic capacitance between the plurality of sub-pixels due to signal wiring. By arranging the anode connection part AN02, the parasitic capacitances of the plurality of sub-pixels can be kept substantially consistent, thereby improving the display uniformity of the display substrate.

[0276] (113) Forming a pixel definition layer pattern. In an example embodiment, forming the pixel definition layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a pixel definition layer thin film, patterning the pixel definition layer using a patterning process, and forming a pixel definition layer pattern disposed on the anode conductive layer, as shown in Figure 19a to Figure 19b , Figure 19a Fig. 6 is a plan view of a pixel definition layer after forming six sub-pixels. Figure 19b Fig. 7 is a plan view of a pixel definition layer. Figure 19a

[0277] In an example embodiment, the pixel definition layer pattern can include a plurality of pixel openings K, and the pixel openings K expose the anode AN. In an example embodiment, the orthographic projection of the pixel openings K on the substrate is within the orthographic projection of the anode AN on the substrate. In an example embodiment, the pixel openings K can include a pixel opening K01 of the first sub-pixel, a pixel opening K02 of the second sub-pixel, and a pixel opening K03 of the third sub-pixel, and the orthographic projection of the pixel opening K01 of the first sub-pixel on the substrate has an overlapping area with the orthographic projection of the first anode AN1 on the substrate; the orthographic projection of the pixel opening K02 of the second sub-pixel on the substrate has an overlapping area with the orthographic projection of the second anode AN2 on the substrate; and the orthographic projection of the pixel opening K03 of the third sub-pixel on the substrate has an overlapping area with the orthographic projection of the third anode AN3 on the substrate.

[0278] In an example embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, multiple layers, or a composite layer.

[0279] In an example embodiment, taking the six sub-pixels (one sub-pixel row, six sub-pixel columns, and a pixel driving circuit using a 7T2C structure as shown in Figure 4 Fig. 8) in the display area (AA) as an example, another preparation process of the display substrate can be the same as the above-mentioned steps (101) to (113), and the difference is as follows:

[0280] The fifth conductive layer formed in the above-mentioned step (110) can be as shown in Figure 20a to Figure 20d Fig. 9, Figure 20a ​This is a planar structure diagram of the six sub-pixels after the formation of the fifth conductive layer. Figure 20b to Figure 20d for Figure 20a A schematic diagram of the structure of the fifth conductive layer. Figure 20b The fifth conductive layer shown is Figure 16b The difference in the fifth conductive layer shown is: Figure 20b In the fifth conductive layer pattern shown, at least a portion of the signal traces corresponding to the pixel opening K in the fifth conductive layer are provided with a cutout structure. That is, the signal traces in the area overlapping with the pixel opening in the fifth conductive layer are uniformly arranged strip structures (slit-like), ensuring that the signal traces in the pixel opening K area are roughly evenly distributed. This reduces asymmetric color shift, and at the edge of the display area, the same signal lines can be interconnected, such as... Figure 20c As shown, in the fifth conductive layer of the first row of sub-pixels, at the edge of the display area, the same signal line is interconnected, as shown. Figure 20d As shown, the fifth conductive layer in the last row of sub-pixels is located at the edge of the display area, interconnected by the same signal line. Figure 20a Based on this, the structure after sequentially forming the second planarization layer, the anode conductive layer, and the pixel definition layer is as follows: Figure 21a As shown, in the formation Figure 20c The structure after forming the second planarization layer, the anode conductive layer, and the pixel definition layer sequentially on the fifth conductive layer shown in the figure is as follows: Figure 21b As shown, in the formation Figure 20d The structure after forming the second planarization layer, the anode conductive layer, and the pixel definition layer sequentially on the fifth conductive layer shown in the figure is as follows: Figure 21c As shown.

[0281] In an exemplary embodiment, six sub-pixels (one sub-pixel row and six sub-pixel columns) are used in the display area (AA), and the pixel driving circuit employs... Figure 4 Taking the 7T2C structure shown as an example, the preparation process of another display substrate can be the same as steps (101) to (113) above, with the following differences:

[0282] The fifth conductive layer formed in step (110) above can be as follows: Figure 22a to Figure 22b As shown, Figure 22a This is a planar structure diagram of the six sub-pixels after the formation of the fifth conductive layer. Figure 22b for Figure 20a A schematic diagram of the structure of the fifth conductive layer. Figure 22b The fifth conductive layer shown is Figure 20b The difference in the fifth conductive layer shown is: Figure 22bIn the fifth conductive layer pattern shown, the signal lines are connected as an integral structure in the area not overlapping the pixel openings, which can avoid the risk of signal floating caused by local disconnection to a certain extent under the premise of reducing asymmetric color cast, thereby avoiding the problem of increased resistance of the disconnected signal line after the signal line is disconnected at a certain position, and reducing the resistance and improving the display uniformity to a certain extent. Figure 22a The structure after sequentially forming the second planar layer, the anode conductive layer and the pixel definition layer is shown in Figure 23 .

[0283] In the exemplary embodiments, the sub-pixel row and the sub-pixel column described in the embodiments of the present disclosure can be understood as the row and the column of the pixel driving circuit in the sub-pixel. The anode in the sub-pixel is connected with the pixel driving circuit in the corresponding sub-pixel, but the position of the anode in the sub-pixel does not necessarily correspond to the row and the column of the pixel driving circuit connected therewith. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate can have an overlapping area with the orthographic projection of the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel on the substrate. The orthographic projection of the anode AN2 of the second sub-pixel on the substrate can have an overlapping area with the orthographic projection of the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel on the substrate. The orthographic projection of the anode AN1 of the first sub-pixel on the substrate can have an overlapping area with the orthographic projection of the pixel driving circuit of the first sub-pixel on the substrate.

[0284] The structure shown in the foregoing embodiments of the present disclosure and the preparation process thereof are merely exemplary descriptions. In the exemplary embodiments, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. The display substrate of the embodiments of the present disclosure can be applied to other display devices having pixel driving circuits, such as quantum dot displays, which are not limited in the present disclosure.

[0285] The present disclosure further provides a display device, as shown in Figure 24 , which can include the display substrate of any of the foregoing embodiments. The display device can be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator.

[0286] The display substrate and the display device provided by the embodiments of the present disclosure can improve the asymmetric color cast and solve the problem of asymmetric color cast to some extent, thereby improving the display effect.

[0287] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0288] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0289] Although the embodiments disclosed by the embodiments of the present disclosure are as above, the content is only the implementation adopted to facilitate the understanding of the embodiments of the present disclosure, and is not used to limit the embodiments of the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the implementation form and details without departing from the spirit and scope of the embodiments of the present disclosure. The patent protection scope of the embodiments of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized by, The display substrate comprises: a substrate and a plurality of sub-pixels, a driving circuit layer, and a pixel definition layer, the driving circuit layer is located between the substrate and the pixel definition layer in a direction perpendicular to a plane where the display substrate is located, the driving circuit layer comprises a plurality of conductive layers, and the pixel definition layer is formed with a plurality of pixel openings, and the sub-pixel comprises at least one pixel opening; in at least one conductive layer of the plurality of conductive layers, at least one signal line in the same conductive layer corresponds to at least one pixel opening, the at least one signal line and the corresponding pixel opening have an overlapping area, in the area corresponding to the same pixel opening, the at least one signal line is symmetrical to a first middle line of the pixel opening, and the first middle line is a middle line of the pixel opening extending in a second direction.

2. The display substrate of claim 1, wherein, The at least one conductive layer comprises a conductive layer in the driving circuit layer which is most adjacent to the pixel definition layer, and the at least one signal line is located in the conductive layer which is most adjacent to the pixel definition layer. 3.The display substrate of claim 1 or 2, wherein, Further comprising an anode conductive layer, the anode conductive layer is located between the driving circuit layer and the pixel definition layer in a direction perpendicular to the plane of the display substrate, the anode conductive layer comprises a plurality of anodes, the plurality of anodes correspond to the plurality of pixel openings one by one, and a projection of the pixel opening on the substrate is located within a projection range of the corresponding anode on the substrate; at least one signal line corresponds to at least one anode, the at least one signal line and the corresponding anode have an overlapping area, in the area corresponding to the same anode, the at least one signal line is symmetrical to a second middle line of a main body part of the anode, and the second middle line is a middle line of the main body part extending in the second direction; in the same sub-pixel, the first middle line and the second middle line overlap on the substrate.

4. The display substrate according to claim 1 or 2, characterized in that, The at least one signal line comprises at least one first type of signal line and at least one second type of signal line, the at least one first type of signal line and the at least one second type of signal line are arranged at intervals in a first direction and extend in the second direction, in the first direction, the size of the first type of signal line is greater than the size of the second type of signal line, and in parallel to the plane where the substrate is located, the first direction intersects the second direction; at least part of the structure of the area where at least part of the first type of signal line corresponds to the pixel opening is provided as a hollow structure, the hollow structure divides the first type of signal line into a plurality of lines arranged at intervals in the first direction, and in the area corresponding to the same pixel opening, in the first direction, the size of at least part of the lines is consistent with the size of at least part of the second type of signal line.

5. The display substrate of claim 4, wherein, In the area corresponding to the same pixel opening: a plurality of first spacings are provided between the plurality of lines and the at least one second type of signal line, the sizes of the plurality of first spacings are consistent, and the first spacing is the distance between adjacent two of the plurality of lines and the at least one second type of signal line. 6.The display substrate of claim 5, wherein, The plurality of lines and the at least one second type signal line are arranged uniformly along the first direction in a region corresponding to the same pixel opening. 7.The display substrate of claim 5, wherein, In the region corresponding to the pixel opening, the size of the line and the second type signal line along the first direction is greater than or equal to 1 micron and less than or equal to 15 microns, and the size of the first interval along the first direction is greater than or equal to 1 micron and less than or equal to 15 microns. 8.The display substrate of claim 4, wherein, The substrate includes a display region, and the plurality of sub-pixels are located in the display region. A same first type signal line is provided with at least one connection node in the display region, and a plurality of lines in the same first type signal line are connected to each other at the connection node. 9.The display substrate of claim 8, wherein, The substrate further includes a frame region surrounding the display region and a plurality of first connection structures. In the second direction, the first connection structures are located on a side of the display region close to the frame region. In at least some of the plurality of first connection structures, each first connection structure corresponds to a same first type signal line, and a plurality of lines in the same first type signal line are connected to each other through the corresponding first connection structure on the side close to the frame region. 10.The display substrate of claim 8, wherein, The substrate further includes a plurality of first connection structures. In at least some of the plurality of first connection structures, each first connection structure corresponds to a same first type signal line. In the second direction, the first connection structures are located between adjacent two pixel openings. In at least some of the plurality of pixel openings, at least one first connection structure is provided on each side of each pixel opening, and a plurality of lines in the same first type signal line between the adjacent two pixel openings are connected to each other through the corresponding first connection structure. 11.The display substrate of claim 1, wherein, At least one of the sub-pixels includes a pixel driving circuit, and the pixel driving circuit is located in the driving circuit layer. The pixel driving circuit includes a plurality of transistors and at least one capacitor. The plurality of transistors include at least one first type transistor and at least one second type transistor. In a direction perpendicular to the plane in which the substrate is located, the capacitor includes a first electrode plate located on one side of the substrate and a second electrode plate located on a side of the first electrode plate away from the substrate. The first type transistor includes an active layer located on a side of the first electrode plate close to the substrate, a control electrode provided in the same layer as the first electrode plate, a first electrode and a second electrode located on a side of the control electrode away from the substrate. The second type transistor includes an active layer located on a side of the second electrode plate away from the substrate, a control electrode located on a side of the active layer away from the substrate, a first electrode and a second electrode located on a side of the control electrode away from the substrate. The first electrode and the second electrode of the first type transistor are provided in the same layer as the first electrode and the second electrode of the second type transistor, and the at least one signal line is located on a side of the first electrode and the second electrode away from the substrate. 12.The display substrate of claim 11, wherein, The at least one signal line comprises a plurality of first power lines and a plurality of first initial signal connection lines, the at least one signal line extends along the second direction and is arranged along a first direction; the plurality of sub-pixels at least comprises a plurality of first sub-pixels, a plurality of second sub-pixels and a plurality of third sub-pixels, the plurality of sub-pixels forms a plurality of pixel units, and each pixel unit at least comprises a first sub-pixel, a second sub-pixel and a third sub-pixel; In the same pixel unit: in the second direction, the pixel opening of the second sub-pixel and the pixel opening of the third sub-pixel are arranged in sequence with a spacing; in the first direction, the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel are arranged in sequence, the pixel opening of the second sub-pixel and the pixel opening of the third sub-pixel are located on the same side of the pixel opening of the first sub-pixel, the first initial signal connection line is located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel, and in the region corresponding to the pixel opening of the second sub-pixel and the pixel opening of the third sub-pixel, the two first power lines in the second sub-pixel and the third sub-pixel are symmetrical relative to the first initial signal connection line. 13.The display substrate of claim 12, wherein, The at least one signal line further comprises a plurality of first second initial signal connection lines and a plurality of second power lines; The first second initial signal line is located at the pixel driving circuit of the first sub-pixel, the pixel driving circuit of each sub-pixel is provided with a second power line, and in the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the first second initial signal line and the second power line in the first sub-pixel are symmetrical relative to a third center line, and the third center line is a center line of the pixel opening of the first sub-pixel extending along the second direction.

14. The display substrate of claim 13, wherein, Further comprising a plurality of anode connection electrodes, a plurality of data signal lines and a plurality of anodes, in the direction perpendicular to the display substrate plane, the plurality of anodes are located between the driving circuit layer and the pixel opening, the plurality of anode connection electrodes correspond to the plurality of anodes one by one, the sub-pixel further comprises at least one anode connection electrode and at least one anode, and in the same sub-pixel, the pixel driving circuit is electrically connected to the corresponding anode through the corresponding anode connection electrode; the at least one signal line further comprises the plurality of anode connection electrodes; In the same pixel unit: in the region corresponding to the pixel opening of the first sub-pixel, the data signal line and the anode connection electrode of the first sub-pixel are symmetrical relative to the third center line, and in the first direction, the data signal line is located on the side away from the second power line of the first second initial signal connection line, and the anode connection electrode of the first sub-pixel is located on the side away from the first second initial signal connection line of the second power line. 15.The display substrate of claim 14, wherein, In the same pixel unit: in the region corresponding to the anode of the second sub-pixel, the anode connecting electrodes in the second sub-pixel and the third sub-pixel are symmetrical relative to the first initial signal connecting line; in the first direction, in any one of the second sub-pixel and the third sub-pixel, the anode connecting electrode is located on the side of the first power supply line away from the first initial signal connecting line. 16.The display substrate of claim 14, wherein, The at least one signal line includes a plurality of first type signal lines and a plurality of second type signal lines, and in the first direction, the size of the first type signal line is greater than the size of the second type signal line; The plurality of first type signal lines include: a first second initial signal line and a second power supply line located in the pixel driving circuit of the first sub-pixel, and a first power supply line located in the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel; the plurality of second type signal lines include: a data signal line and an anode connecting electrode located in the pixel driving circuit of the first sub-pixel, and a first initial signal connecting line between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel; The region corresponding to the pixel opening of the first type signal line is provided as a hollow structure, and the hollow structure divides the first type signal line into a plurality of lines arranged at intervals along the first direction, and in the region corresponding to the same pixel opening, the size of the plurality of lines in the first direction is consistent with the size of the second type signal line. 17.The display substrate of claim 16, wherein, Further comprising a plurality of second power supply connecting lines, the second power supply connecting lines extend along the first direction, and the second power supply connecting lines are provided in the same layer as the first pole and the second pole; The plurality of second power supply lines and the plurality of second power supply connecting lines are connected to each other through second power supply vias to form a grid-like structure, the pixel opening of the first sub-pixel overlaps with the second power supply via, and in the region corresponding to the pixel opening of the first sub-pixel, the size of the line in the second power supply connecting line along the first direction at the position of the second power supply via is greater than the size of the line along the first direction at the position not provided with the second power supply via. 18.The display substrate of claim 16, wherein, In the same sub-pixel, a plurality of anode vias are provided, the plurality of anode vias include a first anode via and a second anode via, the anode connecting electrode is electrically connected to the corresponding pixel driving circuit through the first anode via, and is electrically connected to the corresponding anode through the second anode via, and the line adjacent to the anode via of the first type signal line is bent away from the anode via in the direction away from the anode via. 19.The display substrate of claim 18, wherein, In the same pixel unit: in the second power supply line corresponding to the anode of the first sub-pixel, at least one line in the second power supply line corresponding to the anode via position in the first sub-pixel is bent away from the corresponding anode via in the first direction, and is combined with the line of the second power supply line on the side away from the corresponding anode via; In the first power supply line corresponding to the anode of the second sub-pixel, at least one line in the first power supply line corresponding to the position of the anode via hole in the second sub-pixel is bent away from the corresponding anode via hole and merged with the line of the first power supply line away from the corresponding anode via hole.

20. A display device comprising: The display substrate as claimed in any one of claims 1 to 19.

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