Unmanned aerial vehicle mainboard and unmanned aerial vehicle base station

Abstract

The utility model relates to the technical field of unmanned aerial vehicles, and discloses an unmanned aerial vehicle mainboard and an unmanned aerial vehicle base station. The core board is connected with the carrier board to form a mainboard; the core board is used for providing a standard interface for the carrier board; and the carrier plate is used for being connected with the core plate through the standard interface and providing a power supply for the core plate. The unmanned aerial vehicle mainboard has the characteristics of high reliability and high protection level, and supports a POE industrial camera, RGV control, an intelligent gateway, isolation protection of external signals and anti-seismic and waterproof design of interfaces. And the use requirements of multiple interfaces, multiple functions and high reliability of the distribution unmanned aerial vehicle base station are met.

Description

Technical Field

[0001] This application relates to the field of unmanned aerial vehicle (UAV) technology, and more particularly to a UAV motherboard and a UAV base station. Background Technology

[0002] With the development of the urban low-altitude economy, delivery services such as express delivery and food delivery are gradually becoming unmanned. Building such a delivery network requires efficient and reliable drone base stations, and the dedicated industrial control motherboard is the core technology of the base station.

[0003] This motherboard needs to connect various intelligent communication devices, such as switching communication networks when a drone moves from far-field to near-field, enabling interconnection between different networks; accurately calculating the drone's position when hovering / landing, fixing the drone, and controlling the RGV to unload its cargo; providing a visual operating interface and touch interaction for users to obtain personal orders; and meeting the dust / waterproof and shockproof requirements for long-term outdoor exposure and RGV movement. This type of motherboard needs to integrate multiple communication functions, including redundant communication schemes, rich and reliable peripheral interfaces, and certain computing and control capabilities. Existing delivery cabinet motherboards are mostly based on ARM architecture, with limited functionality, and cannot meet the multiple usage requirements such as drone take-off and landing. Utility Model Content

[0004] The purpose of this application is to provide a drone motherboard and a drone base station, which aims to solve the technical problem of limited interfaces and functions of delivery drone base stations.

[0005] To achieve the above objectives, this application proposes a drone motherboard, which includes: a core board and a carrier board;

[0006] The core board is connected to the carrier board to form the motherboard;

[0007] The core board is used to provide a standard interface for the carrier board;

[0008] The carrier board is used to connect to the core board via the standard interface and to provide power to the core board.

[0009] In one embodiment, the core board includes: a main controller, a first connector, and a second connector;

[0010] The first end of the main controller is connected to the first end of the carrier board via the first connector; the second end of the main controller is connected to the second end of the carrier board via the second connector.

[0011] In one embodiment, the core board further includes: a first network interface card (NIC) and a second NIC;

[0012] The first end of the first network card is connected to the main controller via PCIe2, and the second end of the first network card is connected to the first connector via LAN1.

[0013] The second end of the first network card is connected to the main controller via PCIE3, and the second end of the first network card is connected to the first connector via LAN2.

[0014] In one embodiment, the core board further includes: a sound card;

[0015] The first end of the sound card is connected to the main controller via HDA, and the second end of the sound card is connected to the second connector via two LOUT channels and one MIC channel.

[0016] In one embodiment, the core board further includes: a bridge chip and an I / O chip;

[0017] The first end of the bridge chip is connected to the main controller via an ESPI interface, the second end of the bridge chip is connected to the second connector via a first LPC interface, and the third end of the bridge chip is connected to the first end of the I / O chip via a second LPC interface.

[0018] The second end of the I / O chip is connected to the second connector via six TTL COM ports and five GPI / O ports.

[0019] In one embodiment, the carrier board includes: a plurality of display signal interfaces, a plurality of USB interfaces, and a plurality of M.2 interfaces;

[0020] The multiple display signals include LVDS signal interfaces and HDMI signal interfaces;

[0021] The plurality of M.2 interfaces include:

[0022] The M.2 KEY B interface with one PCIe signal supports external network cards;

[0023] The M.2 KEY B interface with one USB 3.0 signal supports external 4G / 5G modules;

[0024] The M.2 KEY E interface with one PCIe / USB 2.0 signal supports WIFI / Bluetooth modules;

[0025] The M.2 KEY B interface with one SATA signal supports SATA SSDs;

[0026] The MINIPCIE interface with one USB 2.0 signal supports 4G modules and can be configured with the above-mentioned 4G / 5G module interfaces as dual 4G redundancy or 4G+5G redundancy.

[0027] Among them, the multiple USB interfaces of the southbridge directly output two USB 3.0 signals, which are led to the rear I / O panel through the TYPE A interface, and directly output two USB 2.0 signals, which are led to the rear I / O panel through the A-coded interface.

[0028] In one embodiment, the carrier board further includes: multiple buses, an external network interface card (NIC) chip, a 2.5G NIC chip, a switch, and a PSE controller; the multiple buses include: LAN1, LAN2, LAN3, and LAN4;

[0029] The external network card chip is connected to the rear I / O panel via LAN1;

[0030] The 2.5G network card chip is connected to the rear I / O panel via LAN2;

[0031] The switch outputs LAN3 / LAN4 to the rear I / O panel;

[0032] LAN3 and LAN4 support PoE and are connected to the PSE controller, which manages their power.

[0033] In one embodiment, the carrier board further includes: a digital isolator and a level shifter;

[0034] After conversion by the digital isolator and RS 485 level converter, four RS 485 signals are output and led out to the rear I / O panel through the SOCKET 60 interface.

[0035] In one embodiment, the carrier board further includes: an I / O expander and an optocoupler clutch;

[0036] The I / O expander generates sixteen GPIO signals, of which eight GPIO signals are protected by the optocoupler clutch, and the other eight GPIO signals drive external devices by driving onboard relays through a Darlington array.

[0037] In addition, to achieve the above objectives, this application also proposes a drone base station, which includes the drone motherboard described above.

[0038] This application proposes a drone motherboard, comprising: a core board and a carrier board; the core board is connected to the carrier board to form the motherboard; the core board provides a standard interface for the carrier board; the carrier board connects to the core board through the standard interface and provides power to the core board. The drone motherboard features high reliability and a high protection level, supports PoE industrial cameras, RGV control, and smart gateways, and features isolation protection for external signals and shockproof and waterproof interface design. It meets the multi-interface, multi-functional, and high-reliability requirements of delivery drone base stations. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the module of the first embodiment of the drone motherboard proposed in this application;

[0040] Figure 2 This is a circuit connection diagram of the second embodiment of the drone motherboard proposed in this application;

[0041] Figure 3 This is a circuit connection diagram of the third embodiment of the drone motherboard proposed in this application.

[0042] Explanation of icon numbers:

[0043] label name label name 100 core board J1 First connector 200 carrier board J2 Second connector Intel SOC Main controller Detailed Implementation

[0044] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0046] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0047] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0048] Reference Figure 1 , Figure 1 This is a schematic diagram of a module of the first embodiment of the drone motherboard proposed in this application. Based on Figure 1 The first embodiment of the unmanned aerial vehicle (UAV) motherboard of this application is presented.

[0049] The UAV motherboard includes: a core board 100 and a carrier board 200;

[0050] The core board 100 is connected to the carrier board 200 to form a motherboard.

[0051] It should be understood that the UAV motherboard consists of a core board 100 and a carrier board 200, which are interconnected to form the motherboard. This structural design is similar to the modular design concept in many electronic devices, which combines modules with different functions through specific connection methods to achieve the overall function.

[0052] The core board 100 is used to provide a standard interface for the carrier board 200.

[0053] It should be noted that the core board 100 provides standard interfaces for the carrier board 200. These standard interfaces act as a bridge in the entire UAV system. They define a unified specification, enabling the carrier board 200 to easily connect and exchange information with the core board 100. For example, these may be common communication interfaces (such as SPI interfaces, UART interfaces, etc.) or data transmission interfaces (such as USB interfaces), through which the carrier board 200 can obtain various control signals or data transmitted from the core board 100.

[0054] The carrier board 200 is used to connect to the core board 100 through the standard interface and to provide power to the core board 100.

[0055] It should be understood that the carrier board 200 connects to the core board 100 via a standard interface, achieving both physical and electrical connection. Furthermore, the carrier board 200 provides power to the core board 100. This means that the carrier board 200 undertakes some power management functions; it can process externally input power (possibly DC power from a battery), performing operations such as voltage regulation and filtering, before providing the core board 100 with appropriate voltage and current to ensure its normal operation. This design eliminates the need for the core board 100 to handle complex power supply issues independently, allowing it to focus more on its core functions, such as data processing and control signal generation.

[0056] In this embodiment, the UAV motherboard includes a core board 100 and a carrier board 200. The core board 100 connects to the carrier board 200 to form the motherboard. The core board 100 provides a standard interface for the carrier board 200. The carrier board 200 connects to the core board 100 via the standard interface and provides power to the core board 100. The UAV motherboard features high reliability and a high protection level, supports PoE industrial cameras, RGV control, and smart gateways, and provides isolation protection for external signals and shockproof and waterproof design for the interfaces. This meets the multi-interface, multi-functional, and high-reliability requirements of delivery UAV base stations.

[0057] Reference Figure 2 , Figure 2 This is a circuit connection diagram of a second embodiment of the drone motherboard proposed in this application. Based on the first embodiment of the drone motherboard described above, a second embodiment of the drone motherboard of this application is proposed.

[0058] The core board 100 includes: a main controller Intel SOC, a first connector J1, and a second connector J2.

[0059] It should be noted that the main controller, Intel SOC, is a key component of the core board 100. It acts as the "brain" of the core board 100, responsible for controlling and managing the operation of the entire system. It can process various input / output signals, execute corresponding instruction sets, and coordinate the interaction between the core board 100 and the carrier board 200. These two connectors are the interface components that connect the core board 100 and the carrier board 200. Their main function is to establish a physical connection and ensure stable signal transmission.

[0060] The first end of the main controller Intel SOC is connected to the first end of the carrier board 200 through the first connector J1; the second end of the main controller Intel SOC is connected to the second end of the carrier board 200 through the second connector J2.

[0061] It should be understood that the first end of the main controller Intel SOC is connected to the first end of the carrier board 200 via the first connector J1. This connection method enables the transmission of signals in a specific direction or function between the core board 100 and the carrier board 200. For example, it may be used to transmit power signals, control signals, or data signals. This connection structure facilitates the modular design of the system, making it easy to expand the functionality of the carrier board 200 or upgrade the core board 100.

[0062] It should be noted that the second end of the main controller Intel SOC is connected to the second end of the carrier board 200 via the second connector J2. This connection, together with the first end connection, forms a complete interaction channel between the core board 100 and the carrier board 200. Different connection ends may be responsible for different types of signal transmission, such as one end transmitting data acquisition-related signals and the other end transmitting control feedback signals, thereby ensuring the normal operation of the entire system.

[0063] The core board 100 also includes: a first network card and a second network card;

[0064] The first end of the first network card is connected to the main controller Intel SOC via PCIe2, and the second end of the first network card is connected to the first connector J1 via LAN1;

[0065] The second end of the first network card is connected to the main controller Intel SOC via PCIE3, and the second end of the first network card is connected to the first connector J1 via LAN2.

[0066] It should be understood that the first network card connects to the main controller, Intel SOC, via PCIe 2 (a high-speed serial computer expansion bus standard interface). This connection provides a high-speed channel for data transmission between the main controller, Intel SOC, and the first network card, enabling operations such as network control signals and data exchange. Simultaneously, the second end of the first network card connects to the main controller, Intel SOC, via PCIe 3. This is likely to accommodate different functionalities or data transmission requirements, to increase network bandwidth, or to facilitate interaction between different network function modules and the main controller, Intel SOC.

[0067] It should be noted that the second end of the first network card is connected to the first connector J1 via LAN1 (Local Area Network Interface 1). This indicates that the first network card can transmit network signals to the first connector J1 via LAN1, possibly to further extend the network signal to other devices or modules. The second end of the first network card is also connected to the first connector J1 via LAN2. Here, two different LAN lines are connected to the first connector J1, possibly to enable connections for different network frequency bands or network functions (such as data transmission and network management) with the first connector J1, or to provide network redundancy, ensuring that the other LAN line continues to function normally if one fails. Although the specific function and connection relationship of the second network card are not mentioned here, from the overall structure, it may play a supplementary or backup role to the first network card in the network architecture of the core board 100, or be used to implement different network functions than the first network card.

[0068] The core board 100 also includes a sound card.

[0069] It should be understood that the core board 100 includes a sound card component. As part of the core board 100, the sound card has specific connections with other components to achieve sound-related functions.

[0070] The first end of the sound card is connected to the main controller Intel SOC via HDA, and the second end of the sound card is connected to the second connector J2 via two LOUT channels and one MIC channel.

[0071] It's important to note that the sound card's first end connects to the main controller, Intel SOC, via HDA (High Definition Audio). This connection allows the Intel SOC to interact with the sound card, controlling functions such as audio input and output. For example, the Intel SOC can send commands to the sound card via the HDA protocol to control audio playback, volume adjustment, and other operations. The sound card's second end connects to the second connector J2 via two LOUT channels (potentially left and right channel outputs) and one MIC (microphone input). This connection provides a path for audio signals to be transmitted between the sound card and external devices (devices connected via the second connector J2). The two LOUT channels can output the processed audio signals to external devices, such as connecting to external speakers for playback; while the MIC connection can receive external audio input signals, such as connecting a microphone to capture sound and transmit it to the sound card for processing.

[0072] The core board 100 also includes: a bridge chip and an I / O chip;

[0073] The first end of the bridge chip is connected to the main controller Intel SOC via ESPI, the second end of the bridge chip is connected to the second connector J2 via the first LPC, and the third end of the bridge chip is connected to the first end of the I / O chip via the second LPC.

[0074] It should be understood that the first end of the bridge chip connects to the host controller, Intel SOC, via ESPI (Enhanced Serial Peripheral Interface). ESPI provides a high-speed, reliable communication method between the bridge chip and the host controller, Intel SOC, for transmitting control signals, data, and other information. The second end of the bridge chip connects to the second connector J2 via the first LPC (Low Pin Count). The LPC interface here serves to transmit data, enabling the bridge chip to interact with external devices (via the second connector J2). The third end of the bridge chip connects to the first end of the I / O chip via the second LPC. This connection method establishes a data transmission channel between the bridge chip and the I / O chip, enabling them to exchange data and work together.

[0075] The second end of the I / O chip is connected to the second connector J2 via six TTL COM ports and five GPI / O ports.

[0076] It should be noted that the second end of the I / O chip is connected to the second connector J2 via six TTL COM (Transistor Transistor Logic Communication) channels and five GPI / O (General Purpose Input / Output) channels. TTL COM is used for specific types of communication transmission, while GPI / O can be flexibly configured as input or output as needed. Through these connections, the I / O chip can perform various forms of data interaction with external devices (via the second connector J2).

[0077] In this embodiment, the memory uses surface-mount LPDDR4X, supporting a maximum capacity of 8GB; the storage is equipped with surface-mount eMMC, supporting a maximum capacity of 32GB, providing good shock and drop resistance. The onboard eMMC serves as the motherboard system, and the onboard SSD is used for data storage. The detailed structure of the core board 100 demonstrates that the drone motherboard features high reliability and a high level of protection, supporting PoE industrial cameras, RGV control, and smart gateways, as well as isolation and protection for external signals and shock and waterproof design for the interfaces. This meets the multi-interface, multi-functional, and high-reliability requirements of the delivery drone base station.

[0078] Reference Figure 3 , Figure 3 This is a circuit connection diagram of a third embodiment of the drone motherboard proposed in this application. Based on the first and second embodiments of the drone motherboard described above, a third embodiment of the drone motherboard of this application is proposed.

[0079] The carrier board 200 includes: multiple display signal interfaces, multiple USB interfaces, and multiple M.2 interfaces;

[0080] The multiple display signals include LVDS signal interfaces and HDMI signal interfaces;

[0081] The plurality of M.2 interfaces include:

[0082] The M.2 KEY B interface with one PCIe signal supports external network cards;

[0083] The M.2 KEY B interface with one USB 3.0 signal supports external 4G / 5G modules;

[0084] The M.2 KEY E interface with one PCIe / USB 2.0 signal supports WIFI / Bluetooth modules;

[0085] The M.2 KEY B interface with one SATA signal supports SATA SSDs;

[0086] The MINIPCIE interface with one USB 2.0 signal supports 4G modules and can be configured with the above-mentioned 4G / 5G module interfaces as dual 4G redundancy or 4G+5G redundancy.

[0087] Among them, the multiple USB interfaces of the southbridge directly output two USB 3.0 signals, which are led to the rear I / O panel through the TYPE A interface, and directly output two USB 2.0 signals, which are led to the rear I / O panel through the A-coded interface.

[0088] It should be understood that the display signals include LVDS and HDMI. LVDS is output from the eDP signal via the display conversion chip, with a wafer interface, supporting dual channels and a maximum resolution of 1920x1200@60Hz. The HDMI signal is designed with a colay with LVDS for testing purposes and supports a maximum resolution of 1920x1080@60Hz.

[0089] It should be noted that there are as many as four M.2 interfaces, plus one MINIPCIE interface. Specifically: the M.2 KEY B interface with one PCIe signal supports a 10GBE network card; the M.2 KEY B interface with one USB 3.0 signal supports 4G / 5G modules; the M.2 KEY E interface with one PCIe / USB 2.0 signal supports a WIFI / Bluetooth module, where the WIFI can select the 2.4G / 5.8G / 6.0G frequency band, supports dual-band concurrent operation, and the power is not less than 20dBm; the M.2 KEY B interface with one SATA signal supports 2241-size SATA SSDs; the MINIPCIE interface with one USB 2.0 signal supports 4G modules, and can be configured with the above-mentioned 4G / 5G module interfaces for dual 4G redundancy or 4G+5G redundancy.

[0090] It should be understood that the southbridge outputs two USB 3.0 signals directly to the rear I / O panel via the TYPE A interface, and two USB 2.0 signals directly to the rear I / O panel via the A-coded interface, supporting IP67 dustproof / waterproof rating.

[0091] The carrier board 200 also includes: multiple buses, an external network card chip, a 2.5G network card chip, a switch, and a PSE controller; the multiple buses include: LAN1, LAN2, LAN3, and LAN4;

[0092] The external network card chip is connected to the rear I / O panel via LAN1;

[0093] The 2.5G network card chip is connected to the rear I / O panel via LAN2;

[0094] The switch outputs LAN3 / LAN4 to the rear I / O panel;

[0095] LAN3 and LAN4 support PoE and are connected to the PSE controller, which manages their power.

[0096] It should be noted that one PCIe x1 signal is output to the rear I / O panel via the I210 network card chip (LAN1), with a maximum bandwidth of 1Gb / s; another PCIe x1 signal is output to the rear I / O panel via the 2.5G network card chip (LAN2), with a maximum bandwidth of 2.5Gb / s; and a third PCIe x1 signal is output to LAN X via the Gigabit network card chip. LAN X communicates with the 200 switch chip on the carrier board. The switch outputs LAN3 / LAN4 to the rear I / O panel (supporting PoE), with a maximum bandwidth of 1Gb / s and a maximum power of 15W per port. It supports wide temperature range. LAN3 / LAN4 are powered by the PSE controller to ensure the normal power requirements of the powered devices. All four LAN ports use X-coded interfaces, meet IP67 protection standards, and can withstand the harshest industrial environmental conditions, ensuring the reliability of Ethernet communication.

[0097] The carrier board 200 also includes: a digital isolator and a level converter;

[0098] After conversion by the digital isolator and RS 485 level converter, four RS 485 signals are output and led out to the rear I / O panel through the SOCKET 60 interface.

[0099] It should be understood that the southbridge outputs two CAN signals directly, and another PCIe x1 signal is converted into two CAN signals via the CAN bus controller for a backup design. The signals are digitally isolated and led out to the rear I / O panel through the PBT+ metal alloy SOCKET 60 interface, which can effectively avoid the influence of rain / dust / vibration and ensure the reliability of the motherboard operation.

[0100] It should be noted that the southbridge directly outputs the ESPI bus signal, which is then bridged to the LPC bus signal via the bridge chip. Through the IO chip expansion, it outputs 6 TTL COM signals and 5 GPIO signals. Among them, 4 TTL signals are output as 4 RS 485 signals after passing through a 4-channel digital isolator and RS 485 level conversion, which can prevent damage to devices caused by level mismatch. The signals are led out to the rear IO panel through the SOCKET 60 interface to maintain the high protection level requirement.

[0101] The carrier board 200 also includes: an I / O expander and an optocoupler clutch;

[0102] The I / O expander generates sixteen GPIO signals, of which eight GPIO signals are protected by the optocoupler clutch, and the other eight GPIO signals drive external devices by driving onboard relays through a Darlington array.

[0103] It should be understood that the Southbridge outputs two GPIO signals directly, which are isolated by optocouplers to enable fast interruption. In addition, the Southbridge uses SMBus bus signals to generate 16 GPIO signals through I / O expanders. Among them, 8 GPIO signals are protected by optocouplers, and 8 GPIO signals drive onboard relays through Darlington arrays to achieve higher current drive capability. At the same time, it isolates the influence of external high voltage on the internal components and finally drives devices such as RGV, lighting, and valves.

[0104] In this embodiment, the motherboard supports a wide operating temperature range of -40°C to 85°C, and the BIOS features a dual-backup design with one core board 100 and one carrier board 200, enhancing system reliability and security. A detailed description of the carrier board 200's structure reveals that the drone motherboard possesses high reliability and a high level of protection, supporting PoE industrial cameras, RGV control, and smart gateways, as well as isolation and protection for external signals and shockproof and waterproof design for interfaces. This meets the multi-interface, multi-functional, and high-reliability requirements of delivery drone base stations.

[0105] The above are only some embodiments of this application and do not limit the scope of implementation of this application. Any equivalent structural or procedural transformations made based on the content of this application specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the protection scope of this application.

Claims

1. A drone motherboard, characterized in that, The UAV motherboard includes: a core board and a carrier board; The core board is connected to the carrier board to form the motherboard; The core board is used to provide a standard interface for the carrier board; The carrier board is used to connect to the core board via the standard interface and to provide power to the core board.

2. The UAV motherboard as described in claim 1, characterized in that, The core board includes: a main controller, a first connector, and a second connector; The first end of the main controller is connected to the first end of the carrier board via the first connector; the second end of the main controller is connected to the second end of the carrier board via the second connector.

3. The UAV motherboard as described in claim 2, characterized in that, The core board also includes: a first network card and a second network card; The first end of the first network card is connected to the main controller via PCIe2, and the second end of the first network card is connected to the first connector via LAN1. The second end of the first network card is connected to the main controller via PCIE3, and the second end of the first network card is connected to the first connector via LAN2.

4. The UAV motherboard as described in claim 2, characterized in that, The core board also includes: a sound card; The first end of the sound card is connected to the main controller via HDA, and the second end of the sound card is connected to the second connector via two LOUT channels and one MIC channel.

5. The UAV motherboard as described in claim 2, characterized in that, The core board also includes: bridge chips and I / O chips; The first end of the bridge chip is connected to the main controller via an ESPI interface, the second end of the bridge chip is connected to the second connector via a first LPC interface, and the third end of the bridge chip is connected to the first end of the I / O chip via a second LPC interface. The second end of the I / O chip is connected to the second connector via six TTL COM ports and five GPI / O ports.

6. The UAV motherboard as described in claim 2, characterized in that, The carrier board includes: multiple display signal interfaces, multiple USB interfaces, and multiple M.2 interfaces; The multiple display signals include LVDS signal interfaces and HDMI signal interfaces; The plurality of M.2 interfaces include: The M.2 KEY B interface with one PCIe signal supports external network cards; The M.2 KEY B interface with one USB 3.0 signal supports external 4G / 5G modules; The M.2 KEY E interface with one PCIe / USB 2.0 signal supports WIFI / Bluetooth modules; The M.2 KEY B interface with one SATA signal supports SATASSDs; The MINIPCIE interface with one USB 2.0 signal supports 4G modules and can be configured with the above-mentioned 4G / 5G module interfaces as dual 4G redundancy or 4G+5G redundancy. Among them, the multiple USB interfaces of the southbridge directly output two USB 3.0 signals, which are led to the rear I / O panel through the TYPE A interface, and directly output two USB 2.0 signals, which are led to the rear I / O panel through the A-coded interface.

7. The UAV motherboard as described in claim 2, characterized in that, The carrier board also includes: multiple buses, an external network card chip, a 2.5G network card chip, a switch, and a PSE controller; the multiple buses include: LAN1, LAN2, LAN3, and LAN4; The external network card chip is connected to the rear I / O panel via LAN1; The 2.5G network card chip is connected to the rear I / O panel via LAN2; The switch outputs LAN3 / LAN4 to the rear I / O panel; LAN3 and LAN4 support PoE and are connected to the PSE controller, which manages their power.

8. The UAV motherboard as described in claim 2, characterized in that, The carrier board also includes: a digital isolator and a level converter; After conversion by the digital isolator and RS 485 level converter, four RS 485 signals are output and led out to the rear I / O panel through the SOCKET60 interface.

9. The UAV motherboard as described in claim 2, characterized in that, The carrier board also includes: an I / O expander and an optocoupler clutch; The I / O expander generates sixteen GPIO signals, of which eight GPIO signals are protected by the optocoupler clutch, and the other eight GPIO signals drive external devices by driving onboard relays through a Darlington array.

10. A drone base station, characterized in that, The drone base station includes a drone motherboard as described in any one of claims 1 to 9.

Images