Integrated circuit and semiconductor device

Abstract

The utility model relates to an integrated circuit and a semiconductor device. An integrated circuit includes: a semiconductor substrate; a lateral isolation region defining an active region in the semiconductor substrate; and a feature disposed in a trench extending vertically in depth in the semiconductor substrate through the lateral isolation region and the active region; wherein a bottom of the trench has a shape that varies in depth wherein a lower portion of the bottom of the trench faces a position of the trench through the lateral isolation region and an upper portion of the bottom of the trench faces a position of the trench through the active region, the change in depth is due to the lateral isolation region having an enlarged portion of the lateral isolation region at the location of the trench, the enlarged portion of the lateral isolation region defining a thinned portion of the active region. According to the embodiment of the invention, the performance and the efficiency of the memory are favorably improved by reducing the resistance of the access transistor.

Description

Technical Field

[0001] The embodiments and implementations relate to integrated circuits, and more specifically, to integrated circuits comprising embodiments including trenches extending vertically in depth in a substrate, such as integrated circuits incorporating vertical gate buried transistors (e.g., transistors for accessing non-volatile memory cells). Background Technology

[0002] Figure 1A , 1B Figure 1C illustrates an example of a memory plane incorporating memory cells CEL1 and CEL2 in non-volatile memory technology. Memory cells CEL1 and CEL2 have a floating gate state transistor TE connected in series with a vertical gate buried access transistor TA.

[0003] Figure 1A The arrangement of memory cells is illustrated using a plan view of the memory plane (in semiconductor manufacturing technology, this is usually designated as the front-end line (FEOL) stage).

[0004] Figure 1B It shows Figure 1A A cross-sectional view in plane BB, which passes through the gate region and vertical gate region of the state transistor in width.

[0005] Figure 1C It shows in Figure 1A A cross-sectional view of the plane CC, extending through the vertical gate region in length.

[0006] In short, the state transistor TE makes it possible to store a charge representing a binary data item in its floating gate FG, and the access transistor TA makes it possible, for example, to selectively access memory cells CEL1, CEL2 in write and read modes.

[0007] In addition, in order to access memory cells CEL1 and CEL2, the drain region D of the state transistor TE is typically connected to the bit line, while the source region of the access transistor TA is accessed by a region NISO embedded in the substrate at a depth, which may be referred to as the source plane.

[0008] Typically, the bottom of the vertical gate (TRG) of the access transistor (TA) is not in deep contact with the source plane (NISO), and the source region (Simp) (also known as a source implant) is implanted in the substrate between the bottom of the vertical gate (TRG) and the source plane. The implantation of the source region (Simp) is performed from the bottom of the trench etched to form the vertical gate (TRG). The source implant (Simp) is therefore designed to provide electrical continuity with the source plane (NISO).

[0009] The inventors have noted that the performance limitations and efficiency losses of this non-volatile memory technology may be related to low access current in the memory cell, caused by the high resistance of the access transistor TA. This is because if the trench including the vertical gate TRG has an effective depth p11 smaller than the nominal depth p10, electrical continuity between the source implant Simp and the source plane NISO may be poorly established, leading to the aforementioned increase in the resistance of the access transistor TA.

[0010] The inventors also established a correlation between the increase in resistance of the access transistor TA and the depth of the lateral isolation region STI (typically a shallow isolation trench). This is because the trench containing the vertical gate is etched, particularly in the lateral isolation region STI at the surface of a substrate typically made of silicon oxide, and then in a substrate typically made of monocrystalline silicon oxide. However, the etch rate of the trench is much faster in silicon oxide than in monocrystalline substrates.

[0011] Therefore, for equal etching times, if the depth of the lateral isolation region p21 is smaller, the depth of the trench p11 will be smaller, and if the depth of the lateral isolation region p20 is larger (or at the nominal value), the depth of the trench p10 will be larger (or at the nominal value).

[0012] Finally, the depth p21 of the lateral isolation zone STI, which is less than the nominal depth p20 set in the design, can be caused by the etch stop phenomenon of shallow trench STI, which is commonly referred to as STI etch stop in this technique.

[0013] This undesirable phenomenon is simply caused by the saturation of the etching (reaction) material or etching reaction products in an excessively narrow etching space w21. This phenomenon can manifest as so-called random variations in the manufacturing process, particularly regarding the location on the semiconductor wafer, and is difficult to control. Utility Model Content

[0014] The purpose of this disclosure is to provide an integrated circuit and a semiconductor device that at least partially solves the aforementioned problems existing in the prior art.

[0015] One aspect of this disclosure provides an integrated circuit, comprising: a semiconductor substrate; a lateral isolation region defining an active region in the semiconductor substrate; and a component disposed in a trench extending vertically in depth through the lateral isolation region and the active region in the semiconductor substrate; wherein the bottom of the trench has a shape varying in depth, wherein the lower portion of the bottom of the trench faces a location of the trench through the lateral isolation region, and the upper portion of the bottom of the trench faces a location of the trench through the active region, the variation in depth being attributed to the lateral isolation region having an enlarged portion at the location of the trench, the enlarged portion of the lateral isolation region defining a thinned portion of the active region.

[0016] According to one or more embodiments, the variation in depth has an amplitude greater than 50 nm.

[0017] According to one or more embodiments, a lateral isolation region is defined as an active region extending in length in a first direction, and a trench extends in length in a second direction perpendicular to the first direction, wherein variations in depth in the bottom of the trench have continuous alternation in the second direction.

[0018] According to one or more embodiments, the lower portion is located in a plane oriented by the vertical direction and the first direction and passing through the transverse isolation region, and the upper portion is located in a plane oriented by the vertical direction and the first direction and passing through the active region.

[0019] According to one or more embodiments, the integrated circuit further includes: a buried access transistor having a vertical gate, the vertical gate being a component disposed in a trench; and a state transistor including a stack of a floating gate and a control gate, the stack at least partially covering an active region near the trench.

[0020] According to one or more embodiments, the bottom of the trench has a substantially cycloid appearance.

[0021] Another aspect of this disclosure provides a semiconductor device, including: a semiconductor substrate; and a lateral isolation region defining an active region in the semiconductor substrate; wherein the lateral isolation region has an enlarged portion defining a thinned portion of the active region.

[0022] According to one or more embodiments, an enlarged portion of the lateral isolation region is disposed at the location where a trench is to be formed, the trench extending into the semiconductor substrate through the enlarged portion of the lateral isolation region and the thinned portion of the active region.

[0023] The embodiments of this disclosure advantageously improve memory performance and efficiency by reducing the resistance of the access transistors. Attached Figure Description

[0024] Other advantages and features of this invention will become apparent from a review of the detailed description of the non-limiting implementations and embodiments and from the accompanying drawings, in which:

[0025] Figure 1A , Figure 1B and Figure 1C The illustration shows an example of a memory plane incorporating memory cells in non-volatile memory technology;

[0026] Figure 2A , Figure 2B , Figure 2C and Figure 2D The results of the step of forming a lateral isolation region in a semiconductor substrate in a method for manufacturing an integrated circuit are shown.

[0027] Figure 3A , Figure 3B , Figure 3C and Figure 3D The image shows a memory plane during the initial step of etching trenches extending in depth in the substrate in the method for manufacturing an integrated circuit.

[0028] Figure 4A , Figure 4B , Figure 4C and Figure 4D The image shows a memory plane at the end of the step of etching trenches extending in depth in the substrate in the method for manufacturing an integrated circuit.

[0029] Figure 5A , Figure 5B , Figure 5C and Figure 5D The image shows a memory plane at the end of the formation of a gate structure in a trench extending in depth in a substrate of the method for manufacturing an integrated circuit; and

[0030] Figure 6A , Figure 6B , Figure 6C and Figure 6D The image shows a memory plane at the end of the process of forming memory cells, particularly forming state transistors, in the method for manufacturing an integrated circuit. Detailed Implementation

[0031] Figure 2A , 2B Figures 2C and 2D illustrate the results of the step of forming a lateral isolation region (STI) of a semiconductor substrate (SUB) in a method for manufacturing an integrated circuit, particularly the results of the step of forming a lateral isolation region (STI) in the memory plane of an integrated circuit intended to include cells.

[0032] For orthogonal reference coordinate system XYZ Figure 2A- 2D and the following description Figure 3A - 3D, 4A-4D, 5A-5D, and 6A-6D are defined together.

[0033] The first direction X and the second direction Y are located in the plane of the front FA (see below), and the third direction Z is vertical.

[0034] Figure 2A A plan view of the front FA of the substrate SUB is shown (see below).

[0035] Figure 2B It shows Figure 2A A cross-sectional view in plane BB. Plane BB, pointed to by the first direction X and the vertical direction Z, lies along the length of the active region ACT (see below).

[0036] Figure 2C It shows Figure 2A A cross-sectional view in plane CC. Plane CC is pointed by the second direction Y and the vertical direction Z, and is located through the transverse isolation region STI with an enlarged width or a portion of STIw+ (relative to the nominal width described below) and the active region ACT with a thinned width or a portion of ACTw- (relative to the nominal width described below).

[0037] Figure 2D It shows Figure 2A The cross-sectional view of plane DD in the diagram. Plane DD is pointed by the second direction Y and the vertical direction Z, and is located through the transverse isolation region STI with nominal width STIw and the active region ACT with nominal width ACTw (see below).

[0038] The front side (FA) of the substrate (SUB) is the front-end line (FEOL) stage of the fabrication process from the face of the device from which semiconductor components are manufactured.

[0039] Before or after forming the lateral isolation region STL, a depth-embedded region NISO is formed in the semiconductor substrate SUB. A depth-embedded region NISO with a dopant type opposite to that of the substrate SUB can provide the functionality of the memory cell source plane. Typically, few other steps are performed prior to forming the lateral isolation region STL.

[0040] Lateral isolation region STI is formed from the front FA in the superficial region of the semiconductor substrate SUB (i.e., a shallow region, such as approximately 250 nm or between 150 nm and 350 nm).

[0041] Lateral isolation regions (STIs) are obtained using shallow isolation trench technology. In other words, they are obtained by etching shallow trenches (basically 200 nm to 250 nm) that open in the surface region of the substrate (SUB) and filling the trenches with a dielectric material (typically silicon oxide).

[0042] The lateral isolation region STI defines the active region ACT of the substrate, and the lateral isolation region STI extends in length in the first direction X.

[0043] The step of forming the transverse isolation region STI is configured to form an enlarged portion STIw+ of the transverse isolation region STI, which defines the thinned portion ACTw- of the active region ACT.

[0044] The extended portion STIw+ of the lateral isolation region STI is located at the site of the subsequent etch GRTR of the trench extending vertically in depth within the substrate SUB (see also...). Figure 3A -3D).

[0045] Elsewhere, such as at locations where the GRTR is subsequently etched, the lateral isolation region STI of this portion of the semiconductor substrate has a nominal width STIw in order to define an active region ACT with a nominal width ACTw.

[0046] Therefore, the extended portion STIw+ of the lateral isolation region STI is greater than the nominal width STIw in the second direction Y (in width); and correspondingly, the thickened portion ACTw- of the active region ACT is smaller than the nominal width ACTw in the second direction Y (in width).

[0047] Figure 3A , Figure 3B , Figure 3C and Figure 3D The memory plane is shown during the initial step of etching the trenches extending into the depth of the substrate SUB by the GRTR.

[0048] Figure 3A A plan view of the front surface FA of the substrate SUB is shown.

[0049] Figure 3B It shows Figure 3A plane BB (and) Figure 2A The cross-sectional view is the same as the plane BB.

[0050] Figure 3C It shows Figure 3A The plane CC (and) Figure 2A The cross-sectional view is the same as the plane CC.

[0051] Figure 3D It shows Figure 3A plane DD (and Figure 2A The cross-sectional view is the same as the plane DD.

[0052] The etched trench TR (GRTR) is positioned to extend in length along the second direction Y and perpendicular to its length through the continuous width of the transverse isolation region STI and the active region ACT.

[0053] Therefore, the etching of the trench GRTR vertically passes through the enlarged portion STIw+ of the transverse isolation region STI and the thinned portion ACTw- of the active region ACT.

[0054] The technique for etching the GRTR trench TR is typically a reactive ion type dry etching, such as using reactive ion etching (RIE). Compared to the semiconductor material of the active region ACT, which is typically made of single-crystal silicon, this type of etching usually has fast dynamic characteristics in the dielectric material of the lateral isolation region STI (typically made of silicon oxide).

[0055] Therefore, when the etched GRTR reaches the bottom of the shallow isolation trench (STI), the portion facing the shallow isolation region (STI) is etched deeper than the portion facing the active region (ACT).

[0056] Therefore, during the etching process, the bottom of the trench TR has a shape that varies with depth, with a lower part at the trench location that passes through the transverse isolation region STI and an upper part at the trench location that passes through the active region ACT.

[0057] Figure 4A , Figure 4B , Figure 4C and Figure 4D The memory plane is shown at the end of the GRTR etching step, with the trench TR extending in depth in the substrate SUB.

[0058] Figure 4A A plan view of the front surface FA of the substrate SUB is shown.

[0059] Figure 4B It shows Figure 4A plane BB (and) Figure 2A and Figure 3A The cross-sectional view is the same as the plane BB.

[0060] Figure 4C It shows Figure 4A The plane CC (and) Figure 2A and Figure 3A The cross-sectional view in the plane CC is the same.

[0061] Figure 4D It shows Figure 4A plane DD (and Figure 2A and Figure 3AThe cross-sectional view is the same as the plane DD.

[0062] exist Figure 3A - Figure 3D Between the state of the etch GRTR shown and the end of the etching process, only the semiconductor material of the substrate (i.e., single-crystal silicon) is etched. Therefore, until the end of the etch GRTR, the shape of the trench bottom no longer changes significantly, only the depths p1 and p11 increase.

[0063] Therefore, the bottom of the trench TR thus obtained has a shape with a lower PTB at depth p1, facing the old lateral isolation region STI before etching; and an upper PTH at depth p11, which faces the old active region ACT before etching.

[0064] Furthermore, a source region, Simp, is implanted in the substrate SUB from the bottom of the trench TR between the bottom of the trench TR and the source plane NISO, also known as a source implantation Simp. The source implantation Simp is therefore designed to provide electrical continuity with the source plane NISO.

[0065] Figure 5A , Figure 5B , Figure 5C and Figure 5D The memory plane is shown at the end of a gate structure TRG formed in a trench TR extending in depth in a substrate SUB.

[0066] Figure 5A A plan view of the front surface FA of the substrate SUB is shown.

[0067] Figure 5B It shows Figure 5A plane BB (and) Figure 2A , Figure 3A , Figure 4A The cross-sectional view is the same as the plane BB in the view.

[0068] Figure 5C It shows Figure 5A The plane CC (and) Figure 2A , Figure 3A , Figure 4A The cross-sectional view is the same as the plane CC in the view.

[0069] Figure 5D It shows Figure 5A plane DD (and Figure 2A , Figure 3A , Figure 4A The cross-sectional view is the same as the plane DD in the view.

[0070] First, a dielectric gate layer is typically formed on the bottom and sides of a trench TR that is thus opened in a semiconductor substrate SUB by oxidation.

[0071] Secondly, a conductive gate region is formed in the volume of the trench, typically by depositing excess polysilicon overflowing onto the front FA, and a chemical mechanical polishing step up to the front FA.

[0072] The gate structure TRG arranged in the trench TR includes a dielectric gate envelope on the sides and bottom of the trench, and a conductive gate region in the volume defined by the envelope and the front FA.

[0073] Therefore, the source regions Simp, NISO, and vertical gate structure TRG of the buried access transistor TA for the memory cell of the memory plane are formed in the trench TR.

[0074] Figure 6A , Figure 6B , Figure 6C and Figure 6D The memory plane is shown at the end of the steps of forming memory cells CEL1 and CEL2, particularly the formation of state transistor TE.

[0075] Figure 6A A plan view of the front surface FA of the substrate SUB is shown.

[0076] Figure 6B It shows Figure 6A A cross-sectional view in plane BB. Plane BB and Figure 2A , Figure 3A , Figure 4A , Figure 5A The plane BB is the same, and it passes through the gate regions CG and FG of the state transistor TE in length and through the vertical gate region TRG in width.

[0077] Figure 6C It shows Figure 6A A cross-sectional view in plane CC. Plane CC: with Figure 2A , Figure 3A , Figure 4A , Figure 5A The plane CC is the same, and it extends through the vertical gate region in length.

[0078] Figure 6D It shows Figure 6A A cross-sectional view of plane DD. Plane DD and Figure 2A , Figure 3A , Figure 4A , Figure 5A The plane DD is the same and passes through the gate region of the state transistor in width.

[0079] The steps to complete the formation of memory cells CEL1 and CEL2 include the formation of state transistor TE, which includes a floating gate FG covered by a control gate CG.

[0080] The conductive region of the state transistor TE is implanted in the active region ACT. The drain region D is connected to the corresponding bit lines BL1, BL2, and the source region (not shown) of the state transistor TE is also the drain region of the access transistor TA, and a series connection is made between the state transistor TE and the access transistor TA.

[0081] Bit lines BL1 and BL2 are formed, for example, in a metal layer extending above the storage plane along a first direction X.

[0082] A control gate CG can be generated to extend in a second direction Y, thereby enabling the formation of control gate lines for selectively accessing memory cells, the control gate lines of which belong to the same group referred to as rows.

[0083] The access transistor TA is also manufactured to extend in the second direction Y and can form word lines for selectively accessing memory cells belonging to the same group called memory words.

[0084] The floating gate FG is formed to cover an active region ACT of nominal width ACTw on either side of the vertical gate TRG in the first direction X, specifically covering each memory cell CEL1, CEL2.

[0085] Specifically, the interface between each floating gate FG and the underlying active region ACT is designed to pass through the tunnel oxide layer via a "tunnel effect," typically through the Fowler-Nordheim effect, and / or through the implantation of hot carriers generated by impact ionization to achieve charge implantation.

[0086] The reliability and performance of memory cells CEL1 and CEL2 over multiple cycles are specifically determined by the width of the tunneling effect implantation interface (i.e., by the nominal width ACTw of the active region ACT). The larger the nominal width ACTw of the active region ACT, the greater the reliability of the memory cell.

[0087] Therefore, it is possible to provide an active region ACT that is amplified relative to the floating gate FG (i.e., the width ACTw (here referred to as the nominal width) is greater than the conventional nominal width of the active region).

[0088] This is because by expanding the active region ACT relative to the tunnel implantation region, the reliability of memory cells CEL1 and CEL2 can be improved simultaneously; it does not cause problems related to the resistance of the access transistor TA, because the active region ACT includes a thinned portion ACTw- at the etched location of the trench TR of the access transistor TA.

[0089] In fact, based on the design possibilities and the accompanying drawings, a trade-off between increasing the nominal width ACTw and reducing the width of the thinner portion of ACTw will be found.

[0090] Furthermore, from the above regarding Figure 2A - Figures 2D to 6A - Figure 6D From the viewpoint of the terminal device obtained by the method, the bottom of the trench TR containing the vertical gate TRG has a shape with a depth variation, having a lower PTB at depth p1 and an upper HTB at depth p11. The variation in depth p1–p11 has an amplitude, for example, greater than 50 nm.

[0091] The lower PTB is located at the location of the trench TR that passes through the transverse isolation zone STI, for example, at the intersection between the trench TR (extending in the second direction Y) and the transverse isolation zone STI (extending in the first direction X).

[0092] The upper PTH is located at the position of the trench TR that passes through the active region ACT, for example at the intersection between the trench TR (extending along the second direction Y) and the active region ACT (extending along the first direction X).

[0093] In other words, the structure can also be geometrically defined as follows: the lower PTB is located in the plane XZ_STI, which is pointed to by the vertical direction Z in the first direction X, and is located at a position that passes through the transverse isolation region STI (in length X); and the higher PTH is located in the plane XZ_ACT, which is guided by the vertical direction Z and the first direction X and passes through the active region ACT.

[0094] In a cross-sectional view along the plane CC in the second direction Y, the bottom of the groove has a substantially oblique cycloid appearance (i.e., a shortened cycloid). A cycloid is a curve obtained by tracing the motion described by points connected to a disk that rolls without slipping on a straight line. A cycloid where the point describing the curve lies on the circumference of the disk is called a subcycloid, and a shortened cycloid is described by points between the center of the circle and the center of the circumference (on the radius of the disk).

[0095] In summary, a description of a non-volatile memory including an active region of double width has been given, wherein the width ACTw is wider in the tunnel implantation region and narrower at the point of the trench TR of the access transistor TA.

[0096] This configuration significantly improves the trade-off between cycle performance and the etch stop problem of shallow isolation trench STI, while improving the depth uniformity of shallow isolation trench STI; without sacrificing design density (referred to in the art as pitch density); without relying on any modification to the method of manufacturing shallow isolation trench STI; and is compatible with the size reduction of potential technology development.

[0097] One aspect of this disclosure provides a method for manufacturing an integrated circuit, comprising: forming a lateral isolation region in a semiconductor substrate defining an active region; and etching a trench extending vertically in depth through the lateral isolation region and the active region in the semiconductor substrate; wherein forming the lateral isolation region includes forming the lateral isolation region to have an enlarged portion of the lateral isolation region at the location where the etching of the trench is to be performed, the enlarged portion of the lateral isolation region defining a thinned portion of the active region.

[0098] According to one or more embodiments, the lateral isolation region is defined as an active region extending in length in a first direction, and the trench extends in length in a second direction perpendicular to the first direction, wherein the width of the enlarged portion of the lateral isolation region and the thinned portion of the active region at the etched location of the trench in the second direction is greater than and less than the width outside the etched location of the trench, respectively.

[0099] According to one or more embodiments, forming the lateral isolation region includes: generating a volume of dielectric material in the semiconductor substrate; wherein the active region of the semiconductor substrate is generated from a single-crystal semiconductor material; and wherein the etching dynamics of the trench are faster in the dielectric material than in the single-crystal semiconductor material.

[0100] According to one or more embodiments, the method further includes: forming the gate of a buried access transistor having a vertical gate in a trench etched at a depth in the semiconductor substrate; and forming a stack of a floating gate and a control gate of a state transistor, the stack at least partially covering the active region near the trench.

[0101] The embodiments and implementations of the aspects defined below propose forming a lateral isolation region, which includes an enlarged portion below the trench and a thinned portion outside the trench.

[0102] In other words, it is proposed to form an active region with double the width, which includes a thinned portion below the trench and an enlarged portion outside the trench, assuming that the lateral isolation region defines the active region in the superficial region of the semiconductor substrate.

[0103] It should be noted that the solutions presented in the embodiments and implementations defined below advantageously do not provide for modifying the chemical reactions used in the etching of shallow isolation trenches (STI), which would be expensive and difficult to implement in existing methods, or for modifying the overall nominal width w20 of the lateral isolation region, which would affect the overall performance of the active region, or for increasing the trench etching time, which would also affect other formations of devices using the same steps of etching vertical gate buried transistors.

[0104] Therefore, according to one aspect, a method for manufacturing an integrated circuit is proposed, comprising: forming a lateral isolation region, such as a shallow isolation trench, which defines an active region in a semiconductor substrate; and etching a trench extending vertically through the lateral isolation region and the active region at a depth in the substrate. The formation of the lateral isolation region is configured to form an enlarged portion of the lateral isolation region at the etched location of the trench, the enlarged portion defining a thinned portion of the active region.

[0105] Due to this particular arrangement of the expanded portion of the lateral isolation region that defines the thinned portion of the active region at the etched location of the trench, the bottom of the trench will have a shape of varying depth, with the lower portion facing the etched lateral isolation region and the upper portion facing the etched active region.

[0106] The lower part reaches a sufficient depth to ensure electrical continuity between the source implant and the source plane.

[0107] Therefore, implementing the method according to this aspect in the context of manufacturing a memory with vertical gate buried access transistors in a trench can improve the performance and efficiency of the memory, especially by reducing the resistance of the access transistors.

[0108] According to one embodiment, the formation of the lateral isolation region defines an active region extending in length in a first direction, while the trench extends in length in a second direction perpendicular to the first direction, and the enlarged portion and the thinned portion are respectively larger and smaller in width in the second direction at the etched location of the trench than outside the etched location of the trench.

[0109] In one embodiment, the formation of the lateral isolation region includes creating a volume of dielectric material (e.g., silicon oxide) in the substrate, while the active region of the substrate is created by a single-crystal semiconductor material (e.g., silicon); the etching dynamics of the trench are faster in the dielectric material than in the single-crystal semiconductor material.

[0110] According to one embodiment, the gate of a vertical gate buried access transistor is formed in a trench etched at a depth in the substrate, and a stack of a floating gate and a control gate of a state transistor is formed, the stack at least partially covering the active region near the trench.

[0111] According to another aspect, an integrated circuit is also proposed, comprising: a lateral isolation region defining an active region in a semiconductor substrate; and a component disposed in a trench extending vertically through the lateral isolation region and the active region in the substrate. The bottom of the trench has a depth-varying shape, wherein the lower portion faces the location of the trench through the lateral isolation region and the upper portion faces the location of the trench through the active region.

[0112] For example, the change in depth has a magnitude greater than 50 nm.

[0113] According to one embodiment, the lateral isolation region is defined as an active region extending in length in a first direction, while the trench extends in length in a second direction perpendicular to the first direction, and the depth variation in the bottom of the trench has continuous alternation in the second direction.

[0114] In one embodiment, the lower portion is located in a plane oriented by the vertical direction and the first direction and passes through the transverse isolation zone, while the upper portion is located in a plane oriented by the vertical direction and the first direction and passes through the active zone.

[0115] According to one embodiment, the integrated circuit includes: a vertical gate buried access transistor, the vertical gate being disposed in the trench; and a state transistor including a stack of a floating gate and a control gate, the stack at least partially covering the active region near the trench.

[0116] According to one embodiment, the bottom of the trench has a substantially hypotrochoidal appearance in the second direction (i.e., having a shortened trochoid).

[0117] According to another aspect, a semiconductor device is also proposed, which includes a lateral isolation region defining an active region in a semiconductor substrate, wherein an enlarged portion of the lateral isolation region defines a thinned portion of the active region.

[0118] The semiconductor device according to this aspect corresponds, for example, to an integrated circuit manufactured in the process described above before etching the trench.

[0119] Therefore, according to one embodiment, a semiconductor device can be formed by etching trenches as defined above. In other words, specifically, at the location of the enlarged portion of the lateral isolation region, a thinned portion of the active region is defined in the substrate by trenches extending vertically in depth through the lateral isolation region and the active region.

Claims

1. An integrated circuit, characterized in that, include: Semiconductor substrate; A lateral isolation region defines an active region within the semiconductor substrate; as well as A component disposed in a trench that extends vertically in depth through the lateral isolation region and the active region in the semiconductor substrate; The bottom of the trench has a shape that varies in depth, wherein the lower portion of the bottom of the trench faces the location of the trench passing through the lateral isolation region, and the upper portion of the bottom of the trench faces the location of the trench passing through the active region, the variation in depth being attributed to the lateral isolation region having an enlarged portion at the location of the trench, the enlarged portion of the lateral isolation region defining a thinned portion of the active region.

2. The integrated circuit according to claim 1, characterized in that, The change in the depth has an amplitude greater than 50 nm.

3. The integrated circuit according to claim 1, characterized in that, The lateral isolation zone is defined as the active zone extending in length in a first direction, and the trench extends in length in a second direction perpendicular to the first direction, wherein the variation in depth in the bottom of the trench has continuous alternation in the second direction.

4. The integrated circuit according to claim 3, characterized in that, The lower part is located in a plane oriented by the vertical direction and the first direction and passing through the transverse isolation area, and the upper part is located in a plane oriented by the vertical direction and the first direction and passing through the active area.

5. The integrated circuit according to claim 1, characterized in that, Also includes: A buried access transistor having a vertical gate, the vertical gate being the component disposed in the trench; as well as A state transistor comprising a stack of a floating gate and a control gate, the stack at least partially covering the active region near the trench.

6. The integrated circuit according to claim 1, characterized in that, The bottom of the trench has a substantially cycloid appearance.

7. A semiconductor device, characterized in that, include: Semiconductor substrate; as well as A lateral isolation region defines an active region within the semiconductor substrate; The lateral isolation region has an enlarged portion that defines a thinned portion of the active region.

8. The semiconductor device according to claim 7, characterized in that, The enlarged portion of the lateral isolation region is positioned at the location where a trench will be formed, the trench extending into the semiconductor substrate through the enlarged portion of the lateral isolation region and the thinned portion of the active region.

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