Semiconductor device with current adaptive resistance

Abstract

The utility model provides a semiconductor device having a current adaptive resistance. The semiconductor device includes a first conductivity type semiconductor layer, a source region, and a resistance formation region. Wherein the source region is located in the first conductive type semiconductor layer. The source region includes a second conductive type well region and a first conductive type main source region. The first conductive type main source region is located in the second conductive type well region. The resistor forming region is located in the first conductive type main source region, and the resistor forming region is further adjacent to the second conductive type well region to form a current self-adaptive resistor, so that the short-circuit current flowing through the first conductive type main source region is limited. The current adaptive resistor in the semiconductor device can play a good role in limiting short-circuit current when the device is in a short-circuit working condition, and the stability, the short-circuit current tolerance time and the reliability of the device are improved.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology and relates to semiconductor devices with current-adaptive resistors. Background Technology

[0002] In terms of material properties, SiC has a much higher critical breakdown electric field than Si; for example, the critical breakdown electric field of 4H-SiC is 10 times that of silicon (Si). This means that, under the same drift region width, SiC devices can withstand higher breakdown voltages and greater current densities compared to Si power devices. Furthermore, SiC has a bandgap and thermal conductivity that are three times that of Si. These characteristics make SiC very suitable for high-frequency, high-voltage, and high-temperature environments. However, current SiC vertical double-diffused metal-oxide-semiconductor (VDMOS) chips are prone to failure under extreme short-circuit conditions due to their small area and high current density.

[0003] In related technologies, a ballast resistor can be added to the source region of the device to limit the short-circuit current under short-circuit conditions through the resistive heating effect. For example, a metal-embedded source resistor with a strong positive temperature coefficient can be set in the main source region. When a large short-circuit current passes through the source resistor, the resistance of the source resistor increases significantly after sensing the high temperature, thereby reducing the short-circuit peak current and improving the short-circuit withstand time.

[0004] While the design of the source resistor can limit short-circuit current to some extent, its effect is temperature-sensitive. Under short-circuit conditions, the increase in the source resistor value may exhibit a lag, meaning the source resistor cannot promptly adjust its resistance to detect changes in the current within the device, causing the instantaneous current to still exceed the safe range. Therefore, the method described above, which relies on the thermal effect of metal to increase the source resistance, lacks sufficient sensitivity for controlling short-circuit current and cannot precisely regulate the source resistance, thus failing to adequately improve the device's short-circuit current capability.

[0005] Therefore, how to provide a semiconductor device with a current-adaptive resistor to effectively improve the short-circuit current capability of the semiconductor device and enhance its service life and reliability has become an important technical problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Utility Model Content

[0007] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a semiconductor device with a current adaptive resistor to solve the problem that the short-circuit current capability and reliability of semiconductor devices in the prior art need to be improved.

[0008] To achieve the above and other related objectives, a semiconductor device with a current-adaptive resistor is provided, comprising:

[0009] First conductivity type semiconductor layer;

[0010] The source region is located in the first conductivity type semiconductor layer. The source region includes a second conductivity type well region and a first conductivity type main source region, wherein the first conductivity type main source region is located in the second conductivity type well region.

[0011] A resistance forming region is located in the first conductivity type main source region. The resistance forming region includes a first conductivity type main resistance region and a second conductivity type auxiliary resistance region. The second conductivity type auxiliary resistance region is located in the first conductivity type main source region. The first conductivity type main resistance region is located between the second conductivity type auxiliary resistance region and the second conductivity type well region.

[0012] A source metal is located above the first conductivity type semiconductor layer, and the source metal is connected to a portion of the first conductivity type main source region and the second conductivity type auxiliary resistor region; wherein...

[0013] The resistance forming region and the second conductivity type well region constitute a current adaptive resistor to limit the short-circuit current flowing through the first conductivity type main source region.

[0014] Optionally, the doping concentration of the main resistance region of the first conductivity type is less than the doping concentration of the main source region of the first conductivity type.

[0015] Optionally, the doping concentration range of the main resistance region of the first conductivity type is 8e15 cm⁻¹. -3 ~3e16 cm -3 The doping concentration range of the secondary resistive region of the second conductivity type is 8e16 cm⁻¹. -3 ~3e17 cm -3 The doping concentration range of the second conductivity type well region is 8e17 cm⁻¹. -3 ~3e18 cm -3 .

[0016] Optionally, the ratio between the thickness of the first conductive type main resistor region and the thickness of the second conductive type auxiliary resistor region is in the range of 1.5 to 2.5.

[0017] Optionally, the thickness range of the first conductivity type main resistor region is 0.1μm to 0.3μm; the thickness range of the second conductivity type auxiliary resistor region is 0.05μm to 0.15μm.

[0018] Optionally, the ratio between the width of the first conductivity type main source region and the width of the resistance forming region is in the range of 2.6 to 3.2.

[0019] Optionally, the width of the first conductivity type main source region ranges from 1.5 μm to 4.5 μm; the width of the resistance forming region ranges from 0.8 μm to 1.2 μm.

[0020] Optionally, the resistor forming region divides the first conductivity type main source region into a first source region and a second source region in the current flow path, and the current adaptive resistor is used to limit the short-circuit current flowing between the first source region and the second source region.

[0021] Optionally, the semiconductor device further includes a gate, the gate including a gate dielectric and a gate electrode, the gate dielectric being located between the first conductivity type semiconductor layer and the gate electrode; wherein the gate dielectric covers the second source region, and the gate electrode covers at least a portion of the second source region.

[0022] Optionally, the semiconductor device includes at least one of a planar gate device and a trench gate device.

[0023] As described above, the semiconductor device with a current-adaptive resistor of this application forms a resistance-forming region in the main source region of the first conductivity type, such that the resistance-forming region and the well region of the second conductivity type constitute a current-adaptive resistor to limit the short-circuit current flowing through the main source region of the first conductivity type. This current-adaptive resistor can effectively limit the short-circuit current under short-circuit conditions, not only improving the stability of the semiconductor device under short-circuit conditions and extending the short-circuit current withstand time, but also effectively improving the reliability and durability of the circuit while maintaining high device efficiency, thus helping to expand the application scenarios of the semiconductor device. Attached Figure Description

[0024] Figure 1 The diagram shown is a schematic representation of a semiconductor device with a current-adaptive resistor provided in an embodiment of this application.

[0025] Figure 2 Displayed as Figure 1 Enlarged schematic diagram of region A in the middle;

[0026] Figure 3 The diagram shows another structural schematic of a semiconductor device with a current-adaptive resistor provided in an embodiment of this application.

[0027] Explanation of reference numerals in the attached figures:

[0028] 10 - First conductivity type semiconductor layer, 11 - Substrate, 12 - Drift layer, 121 - JFET region;

[0029] 20 - Source region, 21 - Second conductivity type well region, 220 - Initial main source region, 22 - First conductivity type main source region, 221 - First source region, 222 - Second source region, 23 - Second conductivity type contact region;

[0030] 30 - Resistance forming region; 31 - Main resistance region of the first conductivity type; 32 - Auxiliary resistance region of the second conductivity type;

[0031] 40 - Source metal; 50 - Gate; 51 - Gate dielectric; 52 - Gate electrode; 60 - Interlayer dielectric layer; A - Region. Detailed Implementation

[0032] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application.

[0033] To address the technical problem of insufficient control sensitivity in metal-embedded source resistors mentioned in the background art, an attempt is made to replace thermally sensitive source resistors with electrically sensitive ones, which can improve the timeliness of adjustment to some extent. For example, an N- region can be embedded in the N+ main source region as a resistive region. However, to achieve a comparable resistance under short-circuit conditions, the doping concentration of the N- region needs to be very low, even approaching that of intrinsic semiconductors. This makes it impossible to flexibly adjust the resistance value for different short-circuit requirements by changing the device's doping. In other words, since the source resistance is adjusted based on the doping concentration (or resistivity) of the N- region, and the resistance variation that the N- region can provide when acting as a resistive region is limited, the adjustability of the source resistance is poor. Therefore, this approach also cannot effectively improve the short-circuit current capability of semiconductor devices.

[0034] Please see Figures 1 to 3 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] This application provides a semiconductor device with a current-adaptive resistor (hereinafter referred to as "semiconductor device"). Please refer to [link to relevant documentation]. Figure 1 , Figure 1 A schematic diagram of the semiconductor device is shown; more specifically, Figure 1 This is a schematic cross-sectional view of the cell structure in the height direction of the semiconductor device, which exhibits a symmetrical structure in the width direction. The semiconductor device includes a first conductivity type semiconductor layer 10, a source region 20, a resistance forming region 30, and a source metal 40.

[0036] Specifically, such as Figure 1 As shown, the source region 20 is located in the first conductivity type semiconductor layer 10. The source region 20 includes a second conductivity type well region 21 and a first conductivity type main source region 22. The first conductivity type main source region 22 is located in the second conductivity type well region 21. The resistor forming region 30 is located in the first conductivity type main source region 22. The resistor forming region 30 includes a first conductivity type main resistor region 31 and a second conductivity type auxiliary resistor region 32. The second conductivity type auxiliary resistor region 32 is located in the first conductivity type main source region 22, and the first conductivity type main resistor region 31 is located between the second conductivity type auxiliary resistor region 32 and the second conductivity type well region 21. Furthermore, the first conductivity type main resistor region 31 is also adjacent (vertically adjacent) to the second conductivity type well region 21. The resistor forming region 30 and the second conductivity type well region 21 constitute a current adaptive resistor to limit the short-circuit current flowing through the first conductivity type main source region 22. The source metal 40 is located above the first conductivity type semiconductor layer 10, and the source metal 40 is connected to a portion of the first conductivity type main source region 22 and the second conductivity type auxiliary resistor region 32.

[0037] In this embodiment, a resistor-forming region 30 is provided in the first conductivity type main source region 22. The resistor-forming region 30 is adjacent to the second conductivity type well region 21 to form a current-adaptive resistor. That is, the second conductivity type auxiliary resistor region 32, the first conductivity type main resistor region 31, and the second conductivity type well region 21 are sequentially adjacent to form a JFET structure. When the current-adaptive resistor senses a change in the current flowing through the first conductivity type main source region 22, it adaptively adjusts its own resistance value, thereby adjusting the size of the current path in the first conductivity type main source region 22 (which can be regarded as the area of ​​the region in the first conductivity type main source region 22 where current is allowed to pass). This allows the current-adaptive resistor to instantly increase its resistance value when a large short-circuit current flows through the first conductivity type main source region 22 under short-circuit conditions, thereby narrowing the current path and limiting the short-circuit peak current. This extends the short-circuit current withstand time of the device and improves the stability and reliability of the device. Since the current-adaptive resistor is electrically sensitive (e.g., adjusts its resistance value based on changes in current magnitude), its response speed and sensitivity are significantly improved compared to thermally sensitive resistors, making it suitable for practical applications. Short-circuit current includes the current flowing between the source and drain of a semiconductor device under short-circuit conditions. The current-adaptive resistor described herein is used to limit the magnitude of the short-circuit current flowing through the primary source region 22 of the first conductivity type.

[0038] It should be noted that there are two widely existing short-circuit conditions in the power device industry. The first is a short circuit before turn-on (i.e., a hard-switching fault), and the second is a short circuit after turn-on (i.e., a load short circuit). In these two conditions, the hard-switching fault has a larger short-circuit voltage and current density, resulting in greater electrothermal stress during the short circuit and placing more severe demands on the device. Therefore, if the device's short-circuit withstand capability is improved under hard-switching fault conditions, its short-circuit withstand capability under general short-circuit conditions will also be improved. The adaptive source resistor in the power device provided in this application addresses the hard-switching fault short-circuit condition. During a hard-switching fault, the gate voltage is turned on, the power device is short-circuited, and the entire bus voltage is applied to the power device, causing the current to rise rapidly. Since the JFET region in the source region saturates before the channel current, the peak short-circuit current is suppressed, extending the short-circuit current withstand time.

[0039] In this embodiment, a current-adaptive resistor is integrated in the source region 20. This current-adaptive resistor is a JFET structure composed of a second conductivity type auxiliary resistor region 32, a first conductivity type main resistor region 31, and a second conductivity type well region 21 connected in sequence. When a short-circuit current passes through the first conductivity type main resistor region 31, the voltage drop of the JFET structure increases, i.e., the voltage between the first conductivity type main resistor region 31 and the second conductivity type auxiliary resistor region 32 increases, and the voltage between the first conductivity type main resistor region 31 and the second conductivity type well region 21 increases. This causes the depletion regions between the first conductivity type main resistor region 31 and the second conductivity type auxiliary resistor region 32 and the second conductivity type well region 21 to expand. This manifests as a narrowing of the current path in the first conductivity type main resistor region 31, limiting the short-circuit peak current (i.e., the pinch-in effect). Furthermore, the resistance of this current-adaptive resistor is relatively small under normal device conduction conditions, and will not cause significant loss to the device's current-carrying capability. However, under short-circuit high current conditions, its resistance increases rapidly, achieving the effect of accurately and promptly limiting the short-circuit current. The narrowing effect of this current-adaptive resistor is directly related to its electrical environment (i.e., the electrical sensitivity mentioned above). When the semiconductor device is in a short-circuit state, the current-adaptive resistor can quickly and sensitively react to changes in current and adaptively feed back to changes in resistance. As the short-circuit current increases, the current path in the JFET structure (i.e., the main structure in the first conductivity type main resistance region 31 where the depletion region has not been formed, the region that allows current to pass through) will be affected by the voltage across its terminals and will rapidly become narrower, thereby effectively limiting the short-circuit current.

[0040] In an optional embodiment, the doping concentration of the first conductivity type main resistance region 31 is lower than the doping concentration of the first conductivity type main source region 22. The doping concentration of the first conductivity type main resistance region 31 is selected based on the required on-resistance and short-circuit limiting capability of the semiconductor device. For example, if the semiconductor device has strict requirements for short-circuit limiting capability, the doping concentration of the first conductivity type main resistance region 31 can be designed to be lower, thereby providing a larger resistance value under short-circuit conditions.

[0041] Furthermore, the doping concentration range of the first conductivity type main resistance region 31 is 8e15 cm⁻¹. -3 ~3e16 cm -3 (Including endpoint values), for example, the doping concentration of the first conductivity type main resistance region 31 can be 9e15 cm⁻¹. -3 1e16cm -3 or 2e16 cm -3 The doping concentration range of the second conductivity type auxiliary resistor region 32 is 8e16 cm⁻¹. -3 ~3e17 cm -3(Including endpoint values), for example, the doping concentration of the second conductivity type auxiliary resistor region 32 can be 9e16 cm⁻¹. -3 1e17 cm -3 Or 2e17cm -3 The doping concentration range of the second conductivity type well region 21 is 8e17 cm⁻¹. -3 ~3e18 cm -3 (Including endpoint values), for example, the doping concentration of the second conductivity type well region 21 can be 9e17 cm⁻¹. -3 1e18 cm -3 or 2e18 cm -3 .

[0042] In an optional embodiment, please refer to Figure 2 , Figure 2 It shows Figure 1 A magnified structural diagram of region A shows that the ratio between the thickness t1 of the first conductivity type main resistive region 31 and the thickness t2 of the second conductivity type auxiliary resistive region 32 ranges from 1.5 to 2.5 (inclusive). The ratio between the thickness t1 of the first conductivity type main resistive region 31 and the thickness t2 of the second conductivity type auxiliary resistive region 32 can be 1.8, 2.0, or 2.2. In this text, "width" refers to the dimension in the cell width direction (i.e., the arrangement direction of multiple cells), and "thickness" refers to the dimension perpendicular to the cell width direction. To avoid ambiguity, the thickness of various doped regions mentioned in this text can be considered to some extent as the doping depth of the corresponding structure.

[0043] Since current flows through the first conductivity type main resistance region 31 of the current adaptive resistor under both normal operating conditions and short-circuit conditions, in order to avoid the current adaptive resistor affecting the conduction capability of the device under normal conditions, the thickness t2 of the first conductivity type main resistance region 31 is set as high as possible within a limited area. At the same time, in order for the current adaptive resistor to play a good role in limiting the short-circuit current, the thickness t1 of the second conductivity type auxiliary resistance region 32 needs to be set accordingly to ensure the adjustable width of the depletion region between the second conductivity type auxiliary resistance region 32 and the first conductivity type main resistance region 31.

[0044] Further, the thickness t1 of the first conductivity type main resistance region 31 ranges from 0.1 μm to 0.3 μm (inclusive of endpoint values). For example, the thickness t1 of the first conductivity type main resistance region 31 can be 0.15 μm, 0.2 μm, or 0.25 μm. The thickness t2 of the second conductivity type auxiliary resistance region 32 ranges from 0.05 μm to 0.15 μm (inclusive of endpoint values). For example, the thickness t2 of the first conductivity type main resistance region 31 can be 0.1 μm. The thickness t1 of the first conductivity type main resistance region 31 and the thickness t2 of the second conductivity type auxiliary resistance region 32 are reasonably adjusted under the premise that they do not substantially affect the on-resistance of the device under normal conduction conditions and can effectively limit the short-circuit current under short-circuit conditions. Correspondingly, the thickness of the first conductivity type main source region 22 ranges from 0.15 μm to 0.45 μm (inclusive of endpoint values). For example, the thickness of the first conductivity type main source region 22 can be 0.25 μm, 0.3 μm, or 0.35 μm. Similarly, the thickness of the second conductivity type well region 21 needs to be reasonably designed to meet the controllability of the current-adaptive resistance-controlled current path. For example, the thickness range of the second conductivity type well region 21 is 0.8 μm to 1.5 μm to ensure that the thickness t3 of the portion of the second conductivity type well region 21 located below the first conductivity type main source region 22 can generate a sufficiently wide depletion region between it and the first conductivity type main resistance region 31. For example, the thickness of the second conductivity type well region 21 can be 1 μm.

[0045] In optional embodiments, such as Figure 2 As shown, the ratio between the width w1 of the first conductivity type main source region 22 and the width w2 of the resistance forming region 30 ranges from 2.8 to 3.2 (inclusive of the endpoint values). For example, the ratio between the width w1 of the first conductivity type main source region 22 and the width w2 of the resistance forming region 30 can be 2.8, 2.9, or 3.0.

[0046] Furthermore, the width w1 of the first conductivity type main source region 22 ranges from 1.5 μm to 4.5 μm (inclusive of endpoint values), and the width w2 of the resistance forming region 30 ranges from 0.8 μm to 1.2 μm (inclusive of endpoint values). Correspondingly, the widths of the first conductivity type main resistance region 31 and the second conductivity type auxiliary resistance region 32 both range from 0.8 μm to 1.2 μm (inclusive of endpoint values). For example, the width of the first conductivity type main source region 22 is 2.9 μm, and the width of the resistance forming region 30 is 1.0 μm.

[0047] In an optional embodiment, please refer to Figure 1 and Figure 3 ,in, Figure 3Another schematic diagram of the semiconductor device is shown. The semiconductor device further includes a gate 41, which includes a gate dielectric 51 and a gate electrode 52. The gate dielectric 51 is located between the first conductivity type semiconductor layer 10 and the gate electrode 52. For example, the gate dielectric 51 covers the second source region 222, and the gate electrode 52 covers at least a portion of the second source region 222. The gate dielectric 51 can be made of silicon dioxide, and the gate electrode 52 can be made of polycrystalline silicon. To reduce the resistance of the gate electrode 52, it can be made of heavily doped polycrystalline silicon. For example, the width of the gate dielectric 51 layer is 3 μm, and the thickness of the gate dielectric 51 layer is 45 nm.

[0048] In an optional embodiment, the gate 41 includes at least one of a planar gate and a trench gate. That is, the semiconductor device can be a planar gate device (such as...). Figure 1 (as shown) or trench gate devices (such as Figure 3 As shown), for example, the semiconductor device can be an insulated gate bipolar transistor (IGBT).

[0049] In optional embodiments, such as Figure 1 and Figure 3 As shown, the resistor forming region 30 divides the first conductivity type main source region 22 into a first source region 221 and a second source region 222 in the current flow path. The current adaptive resistor is used to limit the short-circuit current flowing between the first source region 221 and the second source region 222. The first source region 221 is electrically connected to the source metal 40, and the second source region 222 is electrically isolated from the source metal 40. The gate 41 covers at least a portion of the second source region 222. When the gate 41 voltage is greater than a threshold voltage, a channel is formed based on the region of the second conductivity type well region 21 located between the second source region 222 and the first conductivity type semiconductor layer 10 to enable the semiconductor device to conduct. The first conductivity type main source region 22 is divided into a first source region 221 and a second source region 222 by the resistor forming region 30, so that the current flowing from the source metal 40 to the drain metal (or the current flowing from the drain metal to the source metal 40) in the semiconductor device can only flow through the resistor forming region 30, which can further improve the short-circuit current capability of the device.

[0050] Wherein, when the resistance forming region 30 divides the first conductivity type main source region 22 into a first source region 221 and a second source region 222, the source metal 40 is connected to one of the first source region 221 and the second source region 222, while being electrically isolated from the other of the first source region 221 and the second source region 222.

[0051] In optional embodiments, such as Figure 1 and Figure 3 As shown, the source region 20 further includes a second conductivity type contact region 23, which is located in the second conductivity type well region 21 and adjacent to the first conductivity type main source region 22. When the first conductivity type main source region 22 is divided into a first source region 221 and a second source region 222, the second conductivity type contact region 23 is adjacent to the first source region 221, and the source metal 40 is also electrically connected to the second conductivity type contact region 23. The width of the second conductivity type contact region 23 may be equal to or different from the width of the resistor forming region 30; for example, the width of the second conductivity type contact region 23 may be 1 μm.

[0052] In optional embodiments, such as Figure 1 and Figure 3 As shown, the thickness of the first conductive semiconductor layer 10 ranges from 2 to 15 μm (inclusive). For example, the thickness of the first conductive semiconductor layer 10 can be 5 μm, 8 μm, or 10 μm. The thickness of the first conductive semiconductor layer 10 is designed based on the application scenario of the semiconductor device. For example, the thickness of the first conductive semiconductor layer 10 is directly related to the voltage withstand rating of the semiconductor device. When the semiconductor device is used in applications requiring high voltage withstand performance, the thickness of the first conductive semiconductor layer 10 is generally greater than 5 μm. The doping concentration of the first conductive semiconductor layer 10 ranges from 8e15 cm⁻¹. -3 ~1e16 cm -3 (Including endpoint values), for example, the doping concentration of the first conductivity type semiconductor layer 10 can be 9e15 cm⁻¹. -3 .

[0053] In optional embodiments, such as Figure 1 and Figure 3 As shown, the semiconductor device further includes a JFET region 121, which is located in the first conductivity type semiconductor layer 10 and lies between two adjacent second conductivity type well regions 21 in the width direction of the cell. For example, the doping concentration of the JFET region 121 can be 1e17 cm⁻¹. -3Optionally, the surface of the JFET region 121 may further have a surface region, the doping concentration of which may be 5e16 cm⁻¹. -3 .

[0054] In optional embodiments, such as Figure 1 and Figure 3 As shown, the first conductivity type semiconductor layer 10 includes a substrate 11 and a drift layer 12. The source region 20 is located in the drift layer 12. Both the substrate 11 and the drift layer 12 are of the first conductivity type. The doping concentration of the substrate 11 is greater than that of the drift layer 12. The material of the substrate 11 includes at least one of SiC and Si. The thickness of the substrate 11 can be 10 μm.

[0055] In an optional embodiment, the semiconductor device further includes a drain metal (not shown) located on the side of the substrate 11 away from the drift layer.

[0056] In an optional embodiment, the first conductivity type is N-type, and correspondingly, the second conductivity type is P-type. Alternatively, the first conductivity type is P-type, and correspondingly, the second conductivity type is N-type. This embodiment uses N-type as the first conductivity type and P-type as the second conductivity type for example. That is, the semiconductor device in this embodiment includes an N-type drift region, a P-type well region, an N-type main source region, an N-type doped region, a P-type doped region, and a P-type contact region, wherein the P-type well region, the N-type doped region, and the P-type doped region constitute the current adaptive resistor.

[0057] It should be noted that the structural parameters such as the width and thickness of each doped region need to be adjusted based on the cell size. For example, in a specific embodiment, the width of a single cell of the semiconductor device is 5.8 μm, the width of the second conductivity type well region 21 is 4.4 μm, the width of the first conductivity type main source region 22 is 2.9 μm, the width of the second conductivity type contact region 23 is 1 μm, the width of the region in the second conductivity type well region 21 used to form a channel is 0.4 μm, and the width of the JFET region 121 is 1.4 μm.

[0058] The semiconductor device with a current-adaptive resistor provided in this application embodiment forms a resistor-forming region in the main source region of a first conductivity type, such that the resistor-forming region and the well region of a second conductivity type constitute a current-adaptive resistor to limit the short-circuit current flowing through the main source region of the first conductivity type. This current-adaptive resistor can effectively limit the short-circuit current under short-circuit conditions. This not only improves the stability of the semiconductor device under short-circuit conditions and extends the short-circuit withstand time (SWCT), but also effectively enhances the reliability and durability of the circuit while maintaining high device efficiency (e.g., conduction capability), thus helping to expand the application scenarios of semiconductor devices (especially silicon carbide devices).

[0059] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A semiconductor device with a current-adaptive resistor, characterized in that, include: First conductivity type semiconductor layer; The source region is located in the first conductivity type semiconductor layer. The source region includes a second conductivity type well region and a first conductivity type main source region, wherein the first conductivity type main source region is located in the second conductivity type well region. A resistance forming region is located in the first conductivity type main source region. The resistance forming region includes a first conductivity type main resistance region and a second conductivity type auxiliary resistance region. The second conductivity type auxiliary resistance region is located in the first conductivity type main source region. The first conductivity type main resistance region is located between the second conductivity type auxiliary resistance region and the second conductivity type well region. A source metal is located above the first conductivity type semiconductor layer, and the source metal is connected to a portion of the first conductivity type main source region and the second conductivity type auxiliary resistor region; wherein... The resistance forming region and the second conductivity type well region constitute a current adaptive resistor to limit the short-circuit current flowing through the first conductivity type main source region.

2. The semiconductor device with current-adaptive resistance according to claim 1, characterized in that: The doping concentration of the main resistance region of the first conductivity type is less than the doping concentration of the main source region of the first conductivity type.

3. The semiconductor device with current-adaptive resistance according to claim 1, characterized in that: The ratio between the thickness of the first conductive type main resistor region and the thickness of the second conductive type auxiliary resistor region is in the range of 1.5 to 2.

5.

4. The semiconductor device with current-adaptive resistor according to claim 1, characterized in that: The thickness range of the first conductivity type main resistor region is 0.1μm~0.3μm; the thickness range of the second conductivity type auxiliary resistor region is 0.05μm~0.15μm.

5. The semiconductor device with current-adaptive resistor according to claim 1, characterized in that: The ratio between the width of the first conductivity type main source region and the width of the resistance forming region ranges from 2.6 to 3.

2.

6. The semiconductor device with current-adaptive resistor according to claim 1, characterized in that: The width of the main source region of the first conductivity type ranges from 1.5 μm to 4.5 μm; the width of the resistance forming region ranges from 0.8 μm to 1.2 μm.

7. The semiconductor device with current-adaptive resistance according to claim 1, characterized in that: The resistor forming region divides the first conductivity type main source region into a first source region and a second source region in the current flow path, and the current adaptive resistor is used to limit the short-circuit current flowing between the first source region and the second source region.

8. The semiconductor device with current-adaptive resistor according to claim 7, characterized in that: The semiconductor device further includes a gate, which includes a gate dielectric and a gate electrode, wherein the gate dielectric is located between the first conductivity type semiconductor layer and the gate electrode; wherein the gate dielectric covers the second source region, and the gate electrode covers at least a portion of the second source region.

9. The semiconductor device with current-adaptive resistor according to claim 1, characterized in that: The semiconductor device includes at least one of a planar gate device and a trench gate device.

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