Data processing device and system thereof

Abstract

The utility model provides a device for converting a single-ended input signal into a differential output signal. The device comprises a conversion circuit, a buffer circuit and a routing circuit. The conversion circuit is configured to convert a single-ended input signal into a plurality of differential output signals. The buffer circuit is configured to amplify the plurality of differential output signals. The routing circuit is configured to route the single-ended input signal to the output of the conversion circuit and has a shorter signal propagation delay than the conversion circuit.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of system and data processing device for data processing and single-ended input signal is converted into differential output signal. BACKGROUND

[0002] Single-to-differential converter converts single-ended input signal into differential output signal. In single-ended signaling scheme, data is encoded by changes in voltage level relative to a reference point (e.g., ground). Single-ended signaling is more prone to noise compared to differential signaling. Differential signaling scheme encodes data by voltage difference between two complementary output signals and has better common-mode rejection, making single-to-differential converter important in data communication systems. SUMMARY

[0003] The utility model provides a kind of data processing device, comprising: conversion circuit, it is configured to convert single-ended input signal into multiple differential output signals;Buffer circuit, it is configured to amplify the multiple differential output signals;And, first routing circuit, (i) it is configured to the single-ended input signal is routed to the output of the conversion circuit and (ii) compared with the conversion circuit, it has shorter signal propagation delay.

[0004] The utility model provides a kind of system of data processing, comprising: first device, comprising: conversion circuit, it is configured to convert single-ended input signal into multiple differential output signals;Buffer circuit, it is configured to amplify the multiple differential output signals and generate multiple complementary output signals;And, first routing circuit, (i) it is configured to one of the multiple differential output signals is routed to the first output of the buffer circuit and (ii) compared with the buffer circuit, it has shorter signal propagation delay;And, second device, it is configured to generate the single-ended input signal or receive the multiple complementary output signals.

[0005] To make the above features and advantages of the utility model more obvious and easy to understand, the following examples are described in detail below, and the drawings are as follows. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is the block diagram according to the exemplary embodiment of the disclosed system.

[0007] Figure 2 is the circuit diagram according to the first exemplary embodiment of the disclosed device.

[0008] Figure 3is a flowchart of a first exemplary embodiment of a method for converting a single-ended input signal into complementary output signals according to the present disclosure.

[0009] Figure 4 is a circuit diagram of a second exemplary embodiment of a device according to the present disclosure.

[0010] Figure 5 is a circuit diagram of a third exemplary embodiment of a device according to the present disclosure.

[0011] Figure 6 is a flowchart of a second exemplary embodiment of a method for converting a single-ended input signal into complementary output signals according to the present disclosure.

[0012] Figure 7 is a circuit diagram of a fourth exemplary embodiment of a device according to the present disclosure.

[0013] Figure 8 is a flowchart of a third exemplary embodiment of a method for converting a single-ended input signal into complementary output signals according to the present disclosure.

[0014] Figure 9 is a circuit diagram of a fifth exemplary embodiment of a device according to the present disclosure.

[0015] Figure 10 is a flowchart of a fourth exemplary embodiment of a method for converting a single-ended input signal into complementary output signals according to the present disclosure. DETAILED DESCRIPTION

[0016] The following disclosure provides different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of first feature on top of or on a second feature in the following description can include embodiments in which the first feature is formed directly contacting the second feature, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not directly contact each other. Additionally, the present disclosure can make repeated reference to a reference number and / or letter in various instances. Such repeated usage is for the purpose of simplicity and clarity and is not itself indicative of a relationship between the various embodiments and / or configurations discussed.

[0017] The sampling circuit samples or captures the value of the data signal (e.g., the high (or low) state of a bit) at a specific point in time (e.g., during the rising edge of the frequency signal). That is, the data signal is sampled when the rising (or falling) edge of the frequency signal aligns with the high (or low) state of a bit in the data signal. This alignment is ensured using a delay-locked loop (PLL) that requires synchronization between the data and frequency signals. For example, the sampling circuit samples the bit when the rising (or falling) edge of the frequency signal aligns with the portion of the data signal's bit located between the rising (or falling) edge and the falling (or rising) edge. This alignment is ensured using a delay-locked loop. However, a particular data processing device receives and processes data from the data signal generating device. A single-ended to differential converter converts or transforms a single-ended input signal into a complementary output signal (e.g., OUT, OUT'). The load cycle of the complementary output signal in conventional methods deviates significantly from the ideal by 50%. In addition, in the conventional method, the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT') is undesirably long.

[0018] The disclosed methods provide systems, apparatus, and methods for generating complementary output signals that eliminate or mitigate the drawbacks of conventional methods. In some embodiments, the systems, apparatus, and methods include: a signal receiver (e.g., Figure 1 The signal receiver shown); the data processing transmitter; and the data processing device (e.g., Figure 1 The data processing apparatus shown is used to receive data from a data signal generating apparatus and transmit data to a data signal receiving apparatus, and includes a first routing circuit 140, a second routing circuit 150, and a third routing circuit 160. The SDC 130 converts or transforms a single-ended input signal (IN) into a complementary output signal (OUT, OUT'). At least one of the first routing circuit 140, the second routing circuit 150, and the third routing circuit 160 causes the complementary output signal (OUT, OUT') to have substantially 50% load cycles (e.g., between about 49% and about 51% load cycles) and to cause a relatively short delay (e.g., between about -1 picosecond and about 1 picosecond) between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT'). For example, the SDC 130 includes a conversion circuit (e.g., Figure 2The conversion circuit 210 shown converts or transforms a single-ended input signal (IN) into a differential output signal (DS, DS'). A first routing circuit 140 is connected across the two ends of the conversion circuit 210 and, in a manner described below, facilitates the conversion of the single-ended input signal (IN) into a differential output signal (DS') substantially simultaneously with the conversion of the single-ended input signal (IN) into a differential output signal (DS).

[0019] Figure 1 This is a block diagram based on an exemplary embodiment of the system disclosed herein. (Example:) Figure 1 As shown, the system includes an input signal generating device 110, an output signal receiving device 120, and a device 100 connected between the input signal generating device 110 and the output signal receiving device 120. The input signal generating device 110 generates a single-ended input signal (IN). In this exemplary embodiment, the device 100 includes a single-ended to differential converter (SDC) 130, a first routing circuit 140, a second routing circuit 150, and a third routing circuit 160. The SDC 130 performs the following operations: (i) converting or transforming the single-ended input signal (IN) into differential output signals that are substantially out of phase with each other by 180 degrees (e.g., logic 0 and logic 1), for example... Figure 2 The differential output signals (DS, DS') are shown; and (ii) the differential output signals (DS, DS') are converted or transformed into complementary output signals (OUT, OUT'), which are amplified versions of the differential output signals (DS, DS'). The output signal receiving device 120 receives the complementary output signals (OUT, OUT').

[0020] The first routing circuit 140 facilitates the conversion of the single-ended input signal (IN) to a differential output signal (DS') substantially simultaneously with the conversion of the single-ended input signal (IN) to a differential output signal (DS). Each of the second routing circuit 150 and the third routing circuit 160 facilitates the faster conversion of a corresponding differential output signal (DS, DS') to a corresponding complementary output signal (OUT, OUT'). More specifically, Figure 2 This is a circuit diagram according to a first exemplary embodiment of the device 100 disclosed herein.

[0021] like Figure 2As shown in FIG. 1, the SDC 130 includes a conversion circuit 210 and a buffer circuit 220. The conversion circuit 210 converts or translates a single-ended input signal (IN) into differential output signals (DS, DS'). In this exemplary embodiment, the conversion circuit 210 includes a first inverter 230 and a second inverter 240, and a pass gate 250. The first inverter 230 isolates the device 100 from a device (e.g., the input signal generating device 110 (see Figure 1 )) external to the device 100, receives the single-ended input signal (IN), and generates an inverted version of the single-ended input signal (IN).

[0022] The pass gate 250 is connected between the first inverter 230 and the buffer circuit 220. When enabled by a control signal at a control terminal of the pass gate 250, the inverted version of the single-ended input signal (IN) flows from an input of the pass gate to an output of the pass gate 250. The inverted version of the single-ended input signal (IN) at the output of the pass gate 250 serves as the differential output signal (DS). Conversely, when disabled by the control signal at the control terminal of the pass gate 250, the pass gate 250 does not allow the inverted version of the single-ended input signal (IN) to flow therethrough. The second inverter 240 is connected between the first inverter 230 and the buffer circuit 220, receives the inverted version of the single-ended input signal (IN), and generates the differential output signal (DS').

[0023] Various configurations of the conversion circuit 210 are contemplated in yet other embodiments, as long as the various configurations achieve the above-described intended purpose of the conversion circuit 210.

[0024] The buffer circuit 220 isolates the device 100 from a device (e.g., the output signal receiving device 120 (see Figure 1 )) external to the device 100, amplifies the differential output signals (DS, DS'), and generates complementary output signals (OUT, OUT'). In this exemplary embodiment, the buffer circuit 220 includes a first pair of inverters 260, 260', a second pair of inverters 270, 270', and a third pair of inverters 280, 290. The first pair of inverters 260, 260' is connected in series to the output of the pass gate 250 of the conversion circuit 210, amplifies the differential output signal (DS), and generates the complementary output signal (OUT).

[0025] The second pair of inverters 270, 270' is connected in series to the output of the second inverter 240 of the conversion circuit 210, amplifies the differential output signal (DS'), and generates the complementary output signal (OUT'). The third pair of inverters 280, 290 is connected in a cross-coupled manner between a first node (Nl) between the first pair of inverters 260, 260' and a second node (N2) between the second pair of inverters 270, 270' and adjusts the inverted version of the differential output signal (DS) to be closer to a logic 0 (or 1) and the inverted version of the differential output signal (DS') to be closer to a logic 1 (or 0).

[0026] Various configurations of the buffer circuit 220 are contemplated in yet other embodiments, as long as the various configurations achieve the above-mentioned contemplated purposes of the buffer circuit 220.

[0027] The signal propagation delay of an inverter is longer than that of a pass gate. As such, the single-ended input signal (IN) travels more slowly through the first inverter 230 and the second inverter 240 of the conversion circuit 210 than the single-ended input signal (IN) travels through the first inverter 230 and the pass gate 250 of the conversion circuit 210. That is, the differential output signal (DS) reaches the output of the pass gate 250 of the conversion circuit 210 earlier than the differential output signal (DS') reaches the output of the second inverter 240 of the conversion circuit 210. This distorts the load cycle of the complementary output signals (OUT, OUT'), i.e., causes the load cycle of the complementary output signals (OUT, OUT') to deviate from the ideal 50% load cycle, and undesirably lengthens the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0028] The first routing circuit 140 ensures that the arrival of the differential output signal (DS) at the output of the pass gate 250 of the conversion circuit 210 is substantially synchronized with the arrival of the differential output signal (DS') at the output of the second inverter 240 of the conversion circuit 210. For example, the first routing circuit 140 is connected between the input of the first inverter 230 of the conversion circuit 210 and the output of the second inverter 240 of the conversion circuit 210 and has a shorter signal propagation delay than the first inverter 230 and the second inverter 240 of the conversion circuit 210. This shorter signal propagation delay of the first routing circuit 140 compensates for the longer signal propagation delays of the first inverter 230 and the second inverter 240 of the conversion circuit 210. That is, the signal propagation delays of the first inverter 230 and the second inverter 240 of the conversion circuit 210 and the first routing circuit 140 are substantially equal to the average of the shorter signal propagation delay of the first routing circuit 140 and the longer signal propagation delays of the first inverter 230 and the second inverter 240 of the conversion circuit 210. This causes the arrival of the differential output signal (DS) at the output of the pass gate 250 of the conversion circuit 210 to be substantially synchronized with the arrival of the differential output signal (DS') at the output of the second inverter 240 of the conversion circuit 210. This helps to minimize, if not eliminate, distortion of the load swing of the complementary output signals (OUT, OUT') and the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0029] In this exemplary embodiment, the first routing circuit 140 includes a buffer. For example, the buffer includes a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the input of the first inverter 230 of the conversion circuit 210, a source terminal connected to the output of the second inverter 240 of the conversion circuit 210, and a drain terminal connected to ground.

[0030] Various configurations of the first routing circuit 140 are contemplated in yet other embodiments, so long as the various configurations achieve the above-described contemplated purposes of the first routing circuit 140. For example, in some embodiments, the first routing circuit 140 includes a resistor in place of the buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the input of the first inverter 230 of the conversion circuit 210 and a second resistor terminal of the resistor is connected to the output of the second inverter 240 of the conversion circuit 210. In other embodiments, the first routing circuit 140 includes a pass gate in place of the buffer. In other such embodiments, the pass gate has an input connected to the input of the first inverter 230 of the conversion circuit 210, an output connected to the output of the second inverter 240 of the conversion circuit 210, and a pair of control terminals each receiving a control signal for enabling and disabling passage of the single-ended input signal (IN) through the pass gate.

[0031] The second routing circuit 150 expedites arrival of the complementary output signal (OUT') to the outputs of the second pair of inverters 270, 270' of the buffer circuit 220. For example, the second routing circuit 150 is connected between the first node (Nl) and the outputs of the second pair of inverters 270, 270' of the buffer circuit 220. The inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220 and the second routing circuit 150 have a shorter signal propagation delay than the second pair of inverters 270, 270' of the buffer circuit 220. This shorter signal propagation delay of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220 and the second routing circuit 150 compensates for the longer signal propagation delay of the second pair of inverters 270, 270' of the buffer circuit 220. That is, the signal propagation delays of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220, the second pair of inverters 270, 270' of the buffer circuit 220, and the second routing circuit 150 are substantially equal to the average of the shorter signal propagation delay of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220 and the second routing circuit 150 and the longer signal propagation delay of the second pair of inverters 270, 270' of the buffer circuit 220. This expedites arrival of the complementary output signal (OUT') to the outputs of the second pair of inverters 270, 270'. This helps to minimize, if not eliminate, distortion of the load swing of the complementary output signals (OUT, OUT') and delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0032] In this example embodiment, the second routing circuit 150 includes a buffer. For example, the buffer includes a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the first node (Nl), a source terminal connected to the output of the second pair of inverters 270, 270' of the buffer circuit 220, and a drain terminal connected to ground.

[0033] Various configurations of the second routing circuit 150 are contemplated in yet other embodiments, so long as the various configurations achieve the above-described contemplated purposes of the second routing circuit 150. For example, in some embodiments, the second routing circuit 150 includes a resistor in place of the buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the first node (Nl) and a second resistor terminal of the resistor is connected to the output of the second pair of inverters 270, 270' of the buffer circuit 220. In other embodiments, the second routing circuit 150 includes a pass gate in place of the buffer. In other such embodiments, the pass gate has an input connected to the first node (Nl), an output connected to the output of the second pair of inverters 270, 270' of the buffer circuit 220, and a pair of control terminals each receiving a control signal for passing an inverted version of the differential output signal (DS) in the pass gate by being enabled and disabled.

[0034] Similarly, the third routing circuit 160 accelerates the arrival of the complementary output signal (OUT) at the output of the first pair of inverters 260, 260' of the buffer circuit 220. For example, the third routing circuit 160 is connected between the second node (N2) and the output of the first pair of inverters 260, 260' of the buffer circuit 220. The inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 have a shorter signal propagation delay than the first pair of inverters 260, 260' of the buffer circuit 220. This shorter signal propagation delay of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 compensates for the longer signal propagation delay of the first pair of inverters 260, 260' of the buffer circuit 210. That is, the signal propagation delays of the first pair of inverters 260, 260' of the buffer circuit 220, the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 are substantially equal to the average of the shorter signal propagation delay of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 and the longer signal propagation delay of the first pair of inverters 260, 260' of the buffer circuit 220. This accelerates the arrival of the complementary output signal (OUT) at the output of the first pair of inverters 260, 260'. This helps to minimize, if not eliminate, the distortion of the load swing of the complementary output signals (OUT, OUT') and the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0035] In this exemplary embodiment, the third routing circuit 160 comprises a buffer. For example, the buffer comprises a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the second node (N2), a source terminal connected to the output of the first pair of inverters 260, 260' of the buffer circuit 220 and a drain terminal connected to ground.

[0036] In other embodiments, various configurations of the third routing circuit 160 are contemplated, provided that these configurations achieve the aforementioned intended purpose of the third routing circuit 160. For example, in some embodiments, the third routing circuit 160 includes a resistor instead of a buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the second node (N2) and a second resistor terminal of the resistor is connected to the output of the first pair of inverters 260, 260' of the buffer circuit 220. In other embodiments, the third routing circuit 160 includes a transmission gate instead of a buffer. In other such embodiments, the transmission gate has: an input connected to the second node (N2); an output connected to the output of the first pair of inverters 260, 260' of the buffer circuit 220; and a pair of control terminals, each receiving a control signal for enabling and de-enabling the inverted version of the differential output signal (DS') in the transmission gate.

[0037] In some embodiments, the third routing circuit 160 has substantially the same signal propagation delay as the second routing circuit 150. In another embodiment, the third routing circuit 160 has a shorter or longer signal propagation delay compared to the second routing circuit 150.

[0038] Figure 3 This is a flowchart of a first exemplary embodiment of a method 300 for converting or transforming a single-ended input signal into a complementary output signal according to the present disclosure. For ease of understanding, further reference will now be made. Figure 1 and Figure 2 Let's illustrate instance method 300. It should be understood that method 300 applies to all methods except... Figure 1 and Figure 2 Structures other than those shown. Furthermore, it should be understood that in alternative embodiments of method 300, additional operations may be provided before, during, and after method 300, and some of the operations described below may be replaced or eliminated.

[0039] In operation 310, the conversion circuit 210 converts or transforms the single-ended input signal (IN) into a differential output signal (DS, DS'). At this time, compared to the case where the single-ended input signal (IN) passes through the first inverter 230 and the transmission gate 250 of the conversion circuit 210, the single-ended input signal (IN) passes through the first inverter 230 and the second inverter 240 of the conversion circuit 210 more slowly. That is, compared to the case where the differential output signal (DS') reaches the output of the second inverter 240 of the conversion circuit 210, the differential output signal (DS) reaches the output of the transmission gate 250 of the conversion circuit 210 earlier.

[0040] In operation 320, the buffer circuit 220 amplifies the differential output signals (DS, DS') and generates the complementary output signals (OUT, OUT'), respectively. At this time, the differential output signal (DS) passes through the first pair of inverters 260, 260' of the buffer circuit 220, and the differential output signal (DS') passes through the second pair of inverters 270, 270' of the buffer circuit 220.

[0041] In operation 330, the first routing circuit 140 routes the single-ended input signal (IN) from the input of the first inverter 230 of the conversion circuit 210 to the output of the second inverter 240 of the conversion circuit 210. At this time, the single-ended input signal (IN) passes through the first routing circuit 140 faster than the single-ended input signal (IN) passes through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This faster signal propagation of the single-ended input signal (IN) through the first routing circuit 140 compensates for the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. That is, the signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210 and the first routing circuit 140 is substantially equal to the average of the faster signal propagation of the single-ended input signal (IN) through the first routing circuit 140 and the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This causes the differential output signal (DS) reaching the output of the pass gate 250 of the conversion circuit 210 and the differential output signal (DS') reaching the output of the second inverter 240 of the conversion circuit 210 to be substantially synchronized.

[0042] In operation 340, the second routing circuit 150 routes the inverted version of the differential output signal (DS) from the first node (N1) to the outputs of the second pair of inverters 270, 270' of the buffer circuit 220. At this time, the differential output signal (DS) passes through the inverter 260 of the first pair of inverters 260, 260' and the second routing circuit 150 faster than the differential output signal (DS') passes through the second pair of inverters 270, 270' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS) through the inverter 260 of the first pair of inverters 260, 260' and the second routing circuit 150 compensates for the slower signal propagation of the differential output signal (DS') through the second pair of inverters 270, 270' of the buffer circuit 220. This causes the complementary output signal (OUT') to reach the outputs of the second pair of inverters 270, 270' faster.

[0043] In operation 350, the third routing circuit 160 routes the inverted version of the differential output signal (DS') from the second node (N2) to the output of the first pair of inverters 260, 260' of the buffer circuit 220. At this point, the differential output signal (DS') travels faster through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 than the differential output signal (DS) does through the first pair of inverters 260, 260' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS') through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 compensates for the slower signal propagation of the differential output signal (DS) through the first pair of inverters 260, 260' of the buffer circuit 220. This causes the complementary output signal (OUT) to reach the output of the first pair of inverters 260, 260' of the buffer circuit 220 faster.

[0044] Although the device 100 is illustrated with three routing circuits 140, 150, 160, it should be understood that the number of routing circuits of the device 100 can be increased or decreased as desired after reading the present disclosure. For example, Figure 4 is a circuit diagram of a second exemplary embodiment of a device 400 according to the present disclosure.

[0045] As Figure 4 shown in FIG. 4B, the exemplary device 400 differs from the exemplary device 100 shown in Figure 1 by including the first routing circuit 140 and omitting the second routing circuit 150 and the third routing circuit 160. A pair of inverters 410, 420 connected in a cross-coupled manner is positioned between the output of the first pair of inverters 260, 260' of the buffer circuit 220 and the second pair of inverters 270, 270' of the buffer circuit 220. In some embodiments, the exemplary device 400 includes at least one of the second routing circuit 150 and the third routing circuit 160 and omits the first routing circuit 140. In other embodiments, the exemplary device 400 includes the first routing circuit 140 and includes one of the second routing circuit 150 and the third routing circuit 160 and omits the other of the second routing circuit 150 and the third routing circuit 160.

[0046] Since the operation of the device 400 is similar to the operation set forth above for the device 100, the same detailed description is omitted for the sake of brevity.

[0047] Figure 5 is a circuit diagram of a third exemplary embodiment of a device 500 according to the present disclosure. As Figure 5 shown in FIG. 5B, the exemplary device 500 differs from the exemplary device 100 shown in Figure 1The illustrated example apparatus 100 differs in that the second routing circuit 550 causes the inverted version of the differential output signal (DS') to speed up reaching the second node (N2). For example, the second routing circuit 550 is connected between the output of the pass gate 250 of the conversion circuit 210 and the second node (N2) and has a shorter signal propagation delay than the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This shorter signal propagation delay of the second routing circuit 550 compensates for the longer signal propagation delay of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. That is, the signal propagation delays of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the second routing circuit 550 are substantially equal to the average of the shorter signal propagation delay of the second routing circuit 550 and the longer signal propagation delay of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This causes the inverted version of the differential output signal (DS') to speed up reaching the second node (N2). This helps to minimize, if not eliminate, distortion of the load swing of the complementary output signals (OUT, OUT') and the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0048] In this example embodiment, the second routing circuit 550 includes a buffer. For example, the buffer includes a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the output of the pass gate 250 of the conversion circuit 210, a source terminal connected to the second node (N2), and a drain terminal connected to ground.

[0049] Various configurations of the second routing circuit 550 are contemplated in yet other embodiments, so long as the various configurations achieve the above-described contemplated purpose of the second routing circuit 550. For example, in some embodiments, the second routing circuit 550 includes a resistor instead of a buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the output of the pass gate 250 of the conversion circuit 210 and a second resistor terminal of the resistor is connected to the second node (N2). In other embodiments, the second routing circuit 550 includes a pass gate instead of a buffer. In other such embodiments, the pass gate has an input connected to the output of the pass gate 250 of the conversion circuit 210, an output connected to the second node (N2), and a pair of control terminals each receiving a control signal for enabling and disabling passage of the differential output signal (DS) in the pass gate.

[0050] Also as shown in Figure 5 the example apparatus 500 and Figure 1The illustrated example apparatus 100 differs in that the third routing circuit 560 causes an inverted version of the differential output signal (DS) to speed to the first node (Nl). For example, the third routing circuit 560 is connected between an output of the second inverter 240 of the conversion circuit 210 and the first node (Nl) and has a shorter signal propagation delay than the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This shorter signal propagation delay of the third routing circuit 560 compensates for the longer signal propagation delay of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. That is, the signal propagation delays of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220 and the third routing circuit 560 are substantially equal to an average of the shorter signal propagation delay of the third routing circuit 560 and the longer signal propagation delay of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This causes the inverted version of the differential output signal (DS) to speed to the first node (Nl). This helps to minimize, if not eliminate, distortion of the load swing of the complementary output signals (OUT, OUT') and delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0051] In this example embodiment, the third routing circuit 560 includes a buffer. For example, the buffer includes a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the output of the second inverter 240 of the conversion circuit 210, a source terminal connected to the first node (Nl), and a drain terminal connected to ground.

[0052] Various configurations of the third routing circuit 560 are contemplated in yet other embodiments, so long as the various configurations achieve the above-described contemplated purpose of the third routing circuit 560. For example, in some embodiments, the third routing circuit 560 includes a resistor in place of the buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the output of the second inverter 240 of the conversion circuit 210 and a second resistor terminal of the resistor is connected to the first node (Nl). In other embodiments, the third routing circuit 560 includes a pass gate in place of the buffer. In other such embodiments, the pass gate has an input connected to the output of the second inverter 240 of the conversion circuit 210, an output connected to the first node (Nl), and a pair of control terminals each receiving a control signal for enabling and disabling passage of the differential output signal (DS') through the pass gate.

[0053] In some embodiments, the third routing circuit 560 has substantially the same signal propagation delay as the second routing circuit 550. In another embodiment, the third routing circuit 560 has a shorter or longer signal propagation delay than the second routing circuit 550.

[0054] As also shown in FIG. 5, the example apparatus 500 differs from the example apparatus 100 shown in FIG. 1 in that the apparatus 500 includes a pair of inverters 510, 520 connected between the outputs of the first pair of inverters 260, 260' of the buffer circuit 220 and the outputs of the second pair of inverters 270, 270' of the buffer circuit 220 in a cross-coupled manner and omits the third pair of inverters 280, 290. Figure 5 Figure 1 As also shown in FIG. 5, the example apparatus 500 differs from the example apparatus 100 shown in FIG. 1 in that the apparatus 500 includes a pair of inverters 510, 520 connected between the outputs of the first pair of inverters 260, 260' of the buffer circuit 220 and the outputs of the second pair of inverters 270, 270' of the buffer circuit 220 in a cross-coupled manner and omits the third pair of inverters 280, 290.

[0055] Figure 6 is a flowchart of a second example embodiment of a method 600 of converting a single-ended input signal into complementary output signals according to the present disclosure. For ease of understanding, the example method 600 will be further explained with reference to the example apparatus 500 shown in FIG. 5 and the example apparatus 100 shown in FIG. 1. It should be understood that the method 600 is applicable to structures other than the structures shown in FIGS. 1 and 5. Moreover, it should be understood that in alternative embodiments of the method 600, additional operations can be provided before, during, and after the method 600, and some operations described below can be replaced or eliminated. Figure 1 Figure 5 Figure 1 Figure 5

[0056] In operation 610, the conversion circuit 210 converts or transforms the single-ended input signal (IN) into the differential output signals (DS, DS'). At this time, the single-ended input signal (IN) passes through the first inverter 230 and the pass gate 250 of the conversion circuit 210 more slowly than if the single-ended input signal (IN) passed through the first inverter 230 and the pass gate 250 of the conversion circuit 210. That is, the differential output signal (DS) reaches the output of the pass gate 250 of the conversion circuit 210 earlier than the differential output signal (DS') reaches the output of the second inverter 240 of the conversion circuit 210.

[0057] In operation 620, the buffer circuit 220 amplifies the differential output signals (DS, DS') and generates the complementary output signals (OUT, OUT'). At this time, the differential output signal (DS) passes through the first pair of inverters 260, 260' of the buffer circuit 220, while the differential output signal (DS') passes through the second pair of inverters 270, 270' of the buffer circuit 220.

[0058] ​​​​​In operation 630, the first routing circuit 140 routes the single-ended input signal (IN) from the input of the first inverter 230 of the conversion circuit 210 to the output of the second inverter 240 of the conversion circuit 210. At this time, the single-ended input signal (IN) travels faster through the first routing circuit 140 than if the single-ended input signal (IN) were to travel through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This faster signal propagation of the single-ended input signal (IN) through the first routing circuit 140 compensates for the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. That is, the signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210 and the first routing circuit 140 is substantially equal to the average of the faster signal propagation of the single-ended input signal (IN) through the first routing circuit 140 and the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This causes the differential output signal (DS) to reach the output of the pass gate 250 of the conversion circuit 210 to be substantially synchronized with the differential output signal (DS') to reach the output of the second inverter 240 of the conversion circuit 210.

[0059] In operation 640, the second routing circuit 550 routes the differential output signal (DS) from the output of the pass gate 250 of the conversion circuit 210 to the second node (N2). At this time, the differential output signal (DS) travels faster through the second routing circuit 550 than if the differential output signal (DS') were to travel through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS) through the second routing circuit 550 compensates for the slower signal propagation of the differential output signal (DS') through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This causes the complementary output signal (OUT') to reach the output of the second pair of inverters 270, 270' of the buffer circuit 220 faster.

[0060] In operation 650, the third routing circuit 560 routes the differential output signal (DS') from the output of the second inverter 240 of the conversion circuit 210 to the first node (Nl). At this time, the differential output signal (DS') travels through the third routing circuit 560 faster than the differential output signal (DS) travels through the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS') through the third routing circuit 560 compensates for the slower signal propagation of the differential output signal (DS) through the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This causes the complementary output signal (OUT) to reach the output of the first pair of inverters 260, 260' of the buffer circuit 220 faster.

[0061] Figure 7 is a circuit diagram according to a fourth exemplary embodiment of the disclosed apparatus 700. As shown in Figure 7 the exemplary apparatus 700 differs from the exemplary apparatus 100 shown in Figure 1 by the second routing circuit 750 causing the inverted version of the differential output signal (DS') to reach the second node (N2) faster. For example, the second routing circuit 750 is connected between the output of the pass gate 250 of the conversion circuit 210 and the second node (N2) and has a shorter signal propagation delay than the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This shorter signal propagation delay of the second routing circuit 750 compensates for the longer signal propagation delay of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. That is, the signal propagation delays of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the second routing circuit 750 are substantially equal to the average of the shorter signal propagation delay of the second routing circuit 750 and the longer signal propagation delay of the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This causes the inverted version of the second differential output signal (DS') to reach the second node (N2) faster. This helps to minimize, if not eliminate, distortion of the load swing of the complementary output signal (OUT, OUT') and the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0062] In this exemplary embodiment, the second routing circuit 750 includes a buffer. For example, the buffer includes a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the output of the pass gate of the conversion circuit 210, a source terminal connected to the second node (N2), and a drain terminal connected to ground.

[0063] Various configurations of the second routing circuit 750 are contemplated in yet other embodiments, so long as the various configurations achieve the above-described contemplated purposes of the second routing circuit 750. For example, in some embodiments, the second routing circuit 750 includes a resistor in place of the buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the output of the pass gate 250 of the conversion circuit 210 and a second resistor terminal of the resistor is connected to the second node (N2). In other embodiments, the second routing circuit 750 includes a pass gate in place of the buffer. In other such embodiments, the pass gate has an input connected to the output of the pass gate 250 of the conversion circuit 210, an output connected to the second node (N2), and a pair of control terminals each receiving a control signal for enabling and disabling flow of the differential output signal (DS) through the pass gate.

[0064] Also as shown in FIG. 7, the example apparatus 700 differs from the example apparatus 100 shown in FIG. 1 in that the apparatus 700 omits the third pair of inverters 280, 290. Figure 7 Figure 1 As shown in FIG. 7, the example apparatus 700 differs from the example apparatus 100 shown in FIG. 1 in that the apparatus 700 omits the third pair of inverters 280, 290.

[0065] In some embodiments, the third routing circuit 160 has substantially the same signal propagation delay as the second routing circuit 750. In another embodiment, the third routing circuit 160 has a shorter or longer signal propagation delay than the second routing circuit 750.

[0066] Figure 8 is a flowchart of a third example embodiment of a method 800 of converting a single-ended input signal into complementary output signals according to the present disclosure. For ease of understanding, reference will now be made to the example apparatus 700 shown in FIG. 7 and the example method 800 shown in FIG. 8. It should be understood that the method 800 is applicable to structures other than the structure shown in FIG. 7. Moreover, it should be understood that in alternative embodiments of the method 800, additional operations can be provided before, during, and after the method 800, and that some operations described below can be replaced or eliminated. Figure 1 Figure 7 is a flowchart of a third example embodiment of a method 800 of converting a single-ended input signal into complementary output signals according to the present disclosure. For ease of understanding, reference will now be made to the example apparatus 700 shown in FIG. 7 and the example method 800 shown in FIG. 8. It should be understood that the method 800 is applicable to structures other than the structure shown in FIG. 7. Moreover, it should be understood that in alternative embodiments of the method 800, additional operations can be provided before, during, and after the method 800, and that some operations described below can be replaced or eliminated. Figure 1 Figure 7 is a flowchart of a third example embodiment of a method 800 of converting a single-ended input signal into complementary output signals according to the present disclosure. For ease of understanding, reference will now be made to the example apparatus 700 shown in FIG. 7 and the example method 800 shown in FIG. 8. It should be understood that the method 800 is applicable to structures other than the structure shown in FIG. 7. Moreover, it should be understood that in alternative embodiments of the method 800, additional operations can be provided before, during, and after the method 800, and that some operations described below can be replaced or eliminated.

[0067] In operation 810, the conversion circuit 210 converts or transforms the single-ended input signal (IN) into the differential output signals (DS, DS’). At this time, the single-ended input signal (IN) passes through the first inverter 230 and the second inverter 240 of the conversion circuit 210 more slowly than the single-ended input signal (IN) passes through the first inverter 230 and the pass gate 250 of the conversion circuit 210. That is, the differential output signal (DS) reaches the output of the pass gate 250 of the conversion circuit 210 earlier than the differential output signal (DS’) reaches the output of the second inverter 240 of the conversion circuit 210.​​​

[0068] In operation 820, the buffer circuit 220 amplifies the differential output signals (DS, DS') and generates the complementary output signals (OUT, OUT'). At this time, the differential output signal (DS) passes through the first pair of inverters 260, 260' of the buffer circuit 220, while the differential output signal (DS') passes through the second pair of inverters 270, 270' of the buffer circuit 220.

[0069] In operation 830, the first routing circuit 140 routes the single-ended input signal (IN) from the input of the first inverter 230 of the conversion circuit 210 to the output of the second inverter 240 of the conversion circuit 210. At this time, the single-ended input signal (IN) passes through the first routing circuit 140 faster than the single-ended input signal (IN) passes through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This faster signal propagation of the single-ended input signal (IN) through the first routing circuit 140 compensates for the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. That is, the signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210 and the first routing circuit 140 is substantially equal to the average of the faster signal propagation of the single-ended input signal (IN) through the first routing circuit 140 and the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This causes the differential output signal (DS) reaching the output of the pass gate 250 of the conversion circuit 210 and the differential output signal (DS') reaching the output of the second inverter 240 of the conversion circuit 210 to be substantially synchronized.

[0070] In operation 840, the second routing circuit 750 routes the differential output signal (DS) from the output of the pass gate 250 of the conversion circuit 210 to the second node (N2). At this time, the differential output signal (DS) passes through the second routing circuit 750 faster than the differential output signal (DS') passes through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS) through the second routing circuit 750 compensates for the slower signal propagation of the differential output signal (DS') through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220. This causes the complementary output signal (OUT') to reach the outputs of the second pair of inverters 270, 270' of the buffer circuit 220 faster.

[0071] In operation 850, the third routing circuit 160 routes the inverted version of the differential output signal (DS) from the second node (N2) to the output of the first pair of inverters 260, 260' of the buffer circuit 220. At this point, the differential output signal (DS') travels faster through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 than the differential output signal (DS) does through the first pair of inverters 260, 260' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS') through the inverter 270 of the second pair of inverters 270, 270' of the buffer circuit 220 and the third routing circuit 160 compensates for the slower signal propagation of the differential output signal (DS) through the first pair of inverters 260, 260' of the buffer circuit 220. This causes the complementary output signal (OUT) to reach the output of the first pair of inverters 260, 260' of the buffer circuit 220 faster.

[0072] Figure 9 is a circuit diagram of a fifth exemplary embodiment of the disclosed apparatus 900. As shown in Figure 9 the exemplary apparatus 900 differs from the exemplary apparatus 100 shown in Figure 1 by the third routing circuit 960 causing the inverted version of the differential output signal (DS) to reach the first node (Nl) faster. For example, the third routing circuit 960 is connected between the output of the second inverter 240 of the conversion circuit 210 and the first node (Nl) and has a shorter signal propagation delay than the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This shorter signal propagation delay of the third routing circuit 960 compensates for the longer signal propagation delay of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 210. That is, the signal propagation delays of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 210 and the third routing circuit 960 are substantially equal to the average of the shorter signal propagation delay of the third routing circuit 960 and the longer signal propagation delay of the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This causes the inverted version of the differential output signal (DS) to reach the first node (Nl) faster. This helps to minimize, if not eliminate, the distortion of the load swing of the complementary output signal (OUT, OUT') and the delay between the rising (or falling) edge of the complementary output signal (OUT) and the falling (or rising) edge of the complementary output signal (OUT').

[0073] In this example embodiment, the third routing circuit 960 includes a buffer. For example, the buffer includes a transistor (e.g., a field effect transistor) in a source follower configuration and has a gate terminal connected to the output of the second inverter 240 of the conversion circuit 210, a source terminal connected to the first node (Nl), and a drain terminal connected to ground.

[0074] Various configurations of the third routing circuit 960 are contemplated in yet other embodiments so long as the various configurations achieve the above-mentioned contemplated purpose of the third routing circuit 960. For example, in some embodiments, the third routing circuit 960 includes a resistor in place of the buffer. In some such embodiments, a first resistor terminal of the resistor is connected to the output of the second inverter 240 of the conversion circuit 210 and a second resistor terminal of the resistor is connected to the first node (Nl). In other embodiments, the third routing circuit 960 includes a pass gate in place of the buffer. In other such embodiments, the pass gate has an input connected to the output of the second inverter 240 of the conversion circuit 210, an output connected to the first node (Nl), and a pair of control terminals each receiving a control signal for enabling and disabling passage of the differential output signal (DS') through the pass gate.

[0075] As also shown in Figure 9 , the example apparatus 900 differs from the example apparatus 100 shown in Figure 1 in that the apparatus 900 omits the third pair of inverters 280, 290.

[0076] In some embodiments, the third routing circuit 960 has substantially the same signal propagation delay as the second routing circuit 150. In another embodiment, the third routing circuit 960 has a shorter or longer signal propagation delay than the second routing circuit 150.

[0077] Figure 10 is a flowchart of a fourth example embodiment of a method 1000 of converting a single-ended input signal into complementary output signals according to the present disclosure. For ease of understanding, reference will now be made to the example apparatus 900 shown in Figure 1 and Figure 9 to illustrate the example method 1000. It should be understood that the method 1000 is applicable to structures other than the structure shown in Figure 1 and Figure 9 . Moreover, it should be understood that, in alternative embodiments of the method 1000, additional operations can be provided before, during, and after the method 1000, and some of the operations described below can be replaced or eliminated.

[0078] In operation 1010, the conversion circuit 210 converts or translates the single-ended input signal (IN) into the differential output signals (DS, DS’). At this time, the single-ended input signal (IN) travels through the first inverter 230 and the pass gate 250 of the conversion circuit 210 more slowly than if the single-ended input signal (IN) were to travel through the first inverter 230 and the pass gate 250. That is, the differential output signal (DS) reaches the output of the pass gate 250 of the conversion circuit 210 earlier than the differential output signal (DS’) reaches the output of the second inverter 240 of the conversion circuit 210.

[0079] In operation 1020, the buffer circuit 220 amplifies the differential output signals (DS, DS’) and generates the complementary output signals (OUT, OUT’). At this time, the differential output signal (DS) travels through the first pair of inverters 260, 260’ of the buffer circuit 220, while the differential output signal (DS’) travels through the second pair of inverters 270, 270’ of the buffer circuit 220.

[0080] In operation 1030, the first routing circuit 140 routes the single-ended input signal (IN) from the input of the first inverter 230 of the conversion circuit 210 to the output of the second inverter 240 of the conversion circuit 210. At this time, the single-ended input signal (IN) travels through the first routing circuit 140 more quickly than if the single-ended input signal (IN) were to travel through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This more rapid signal propagation of the single-ended input signal (IN) through the first routing circuit 140 compensates for the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. That is, the signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210 and the first routing circuit 140 is substantially equal to the average of the more rapid signal propagation of the single-ended input signal (IN) through the first routing circuit 140 and the slower signal propagation of the single-ended input signal (IN) through the first inverter 230 and the second inverter 240 of the conversion circuit 210. This causes the differential output signal (DS) to reach the output of the pass gate 250 of the conversion circuit 210 and the differential output signal (DS’) to reach the output of the second inverter 240 of the conversion circuit 210 to be substantially synchronized.

[0081] In operation 1040, the second routing circuit 150 routes the inverted version of the differential output signal (DS) from the first node (N1) to the output of the second pair of inverters 270, 270' of the buffer circuit 220. At this time, the differential output signal (DS) travels faster through the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220 and the second routing circuit 150 than the differential output signal (DS') travels through the second pair of inverters 270, 270' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS) through the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220 and the second routing circuit 150 compensates for the slower signal propagation of the differential output signal (DS') through the second pair of inverters 270, 270' of the buffer circuit 220. This speeds up the arrival of the complementary output signal (OUT') at the output of the second pair of inverters 270, 270' of the buffer circuit 220.

[0082] In operation 1050, the third routing circuit 960 routes the differential output signal (DS') from the output of the second inverter 240 of the conversion circuit 210 to the first node (N1). At this time, the differential output signal (DS') travels faster through the third routing circuit 960 than the differential output signal (DS) travels through the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This faster signal propagation of the differential output signal (DS') through the third routing circuit 960 compensates for the slower signal propagation of the differential output signal (DS) through the inverter 260 of the first pair of inverters 260, 260' of the buffer circuit 220. This speeds up the arrival of the complementary output signal (OUT) at the output of the first pair of inverters 260, 260' of the buffer circuit 220.

[0083] In an embodiment, an apparatus includes a conversion circuit, a buffer circuit, and a routing circuit. The conversion circuit is configured to convert a single-ended input signal into a plurality of differential output signals. The buffer circuit is configured to amplify the plurality of differential output signals. The first routing circuit is configured to route the single-ended input signal to an output of the conversion circuit and has a shorter signal propagation delay than the conversion circuit.

[0084] According to some embodiments, the first routing circuit includes a buffer. According to some embodiments, the buffer includes a transistor in a source follower configuration. According to some embodiments, the conversion circuit includes: a first inverter; a pass gate between the first inverter and the buffer circuit; and a second inverter between the first inverter and the buffer circuit, wherein the first routing circuit is between an input of the first inverter and an output of the second inverter. According to some embodiments, the data processing device further includes a second routing circuit configured to route one of the plurality of differential output signals to a first output of the buffer circuit and to have a shorter signal propagation delay than the buffer circuit. According to some embodiments, the data processing device further includes a third routing circuit configured to route another of the plurality of differential output signals to a second output of the buffer circuit and to have a shorter signal propagation delay than the buffer circuit.

[0085] In another embodiment, a method includes: converting, by a conversion circuit, a single-ended input signal into a plurality of differential output signals; amplifying the plurality of differential output signals; and routing, by a routing circuit, the single-ended input signal to an output of the conversion circuit, the routing circuit causing a shorter signal propagation delay than the conversion circuit.

[0086] According to some embodiments, the routing causes the single-ended input signal to pass through a buffer. According to some embodiments, the buffer includes a transistor in a source follower configuration. According to some embodiments, the converting causes the single-ended input signal to pass through an inverter and a pass gate. According to some embodiments, the converting causes the single-ended input signal to pass through a pair of inverters.

[0087] In another embodiment, a system includes a first device and a second device. The first device includes: a conversion circuit configured to convert a single-ended input signal into a plurality of differential output signals; a buffer circuit configured to amplify the plurality of differential output signals and generate a plurality of complementary output signals; and a routing circuit configured to route one of the plurality of differential output signals to an output of the buffer circuit and to have a shorter signal propagation delay than the buffer circuit. The second device is configured to generate the single-ended input signal or to receive the plurality of complementary output signals.

[0088] According to some embodiments, the first routing circuit includes a buffer. According to some embodiments, the buffer includes a transistor in a source follower configuration. According to some embodiments, the system further includes a second routing circuit configured to (i) route another one of the plurality of differential output signals to a second output of the buffer circuit and (ii) have a shorter signal propagation delay than the buffer circuit. According to some embodiments, the buffer circuit includes a first pair of inverters connected in series between a first output of the conversion circuit and the first output of the buffer circuit and a second pair of inverters connected in series between a second output of the conversion circuit and the second output of the buffer circuit; and the first routing circuit is connected between a first node between the first pair of inverters and the second output of the buffer circuit. According to some embodiments, the second routing circuit is connected between a second node between the second pair of inverters and the first output of the buffer circuit. According to some embodiments, the system further includes a cross-coupled inverter connected between the first node and the second node. According to some embodiments, the system further includes a third routing circuit configured to route the single-ended input signal to an output of the conversion circuit and having a shorter signal propagation delay than the conversion circuit. According to some embodiments, the conversion circuit includes a first inverter, a pass gate between the first inverter and the buffer circuit, and a second inverter between the first inverter and the buffer circuit, wherein the third routing circuit is between an input of the first inverter and an output of the second inverter.

[0089] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit it; even though the present application has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the above-described embodiments, or make equivalent replacements to some or all of the technical features; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data processing apparatus, characterized by, comprises: a conversion circuit configured to convert a single-ended input signal into a plurality of differential output signals; a buffer circuit configured to amplify the plurality of differential output signals; and a first routing circuit i. configured to route the single-ended input signal to an output of the conversion circuit and ii. having a shorter signal propagation delay than the conversion circuit. The first routing circuit comprises a buffer.

2. The data processing apparatus according to claim 1, characterized in that, The buffer comprises a transistor in a source follower configuration.

3. The data processing apparatus according to claim 2, characterized in that, The conversion circuit comprises:

4. The data processing apparatus according to claim 1, characterized by a first inverter; a pass gate between the first inverter and the buffer circuit; and a second inverter between the first inverter and the buffer circuit, wherein the first routing circuit is between an input of the first inverter and an output of the second inverter. Further comprising a second routing circuit i. configured to route one of the plurality of differential output signals to a first output of the buffer circuit and ii. having a shorter signal propagation delay than the buffer circuit.

5. The data processing apparatus according to claim 1, characterized by Further comprising a third routing circuit configured to route another of the plurality of differential output signals to a second output of the buffer circuit and having a shorter signal propagation delay than the buffer circuit.

6. The data processing apparatus according to claim 5, characterized in that, comprises:

7. A system for data processing, characterized by a first device comprising: a conversion circuit configured to convert a single-ended input signal into a plurality of differential output signals; a buffer circuit configured to amplify the plurality of differential output signals and generate a plurality of complementary output signals; and a first routing circuit i. configured to route one of the plurality of differential output signals to a first output of the buffer circuit and ii. having a shorter signal propagation delay than the buffer circuit; and a second device configured to generate the single-ended input signal or receive the plurality of complementary output signals. The first routing circuit comprises a buffer, 8. The system for data processing of claim 7, wherein, The buffer comprises a transistor in a source follower configuration. Further comprising a second routing circuit i. configured to route another of the plurality of differential output signals to a second output of the buffer circuit and ii. having a shorter signal propagation delay than the buffer circuit.

9. The system for data processing of claim 7, wherein, 10. The system for data processing of claim 9, wherein: the buffer circuit comprises a first pair of inverters connected in series between a first output of the conversion circuit and the first output of the buffer circuit and a second pair of inverters connected in series between a second output of the conversion circuit and the second output of the buffer circuit; and the first routing circuit is connected between a first node between the first pair of inverters and the second output of the buffer circuit. ​

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