Multi-channel video processing board card

Abstract

The utility model relates to a multi-channel video processing board card, belongs to the technical field of video processing, and solves the problems of low video processing efficiency and high cost in the prior art. The board card comprises a first high-speed data bus interface, a bridging chip and a plurality of video processing modules; one end of the first high-speed data bus interface serves as an external interface of the board card and is connected with host equipment; the other end of the first high-speed data bus interface is connected with one end of the bridging chip, and a video stream is transmitted between host equipment and the bridging chip; and the other end of the bridging chip is connected with a plurality of video processing modules respectively, and video streams are transmitted between the bridging chip and each video processing module. And high-efficiency video processing is realized.

Description

TECHNICAL FIELD

[0001] The utility model relates to video processing technical field especially relates to a multi -channel video processing board card. BACKGROUND

[0002] With the rapid development of audio-visual electronic industry, the popularization and application of 4K / 8K ultra-high definition video technology in video conference need higher image quality, lower data volume transmission, and put forward higher requirements to video processing related products such as video codec.

[0003] Traditional video coding mode is divided into two categories of soft coding and hard coding, soft coding is mainly used for operation in host device, and there are slow coding speed, low efficiency, few concurrent channels, large resource occupation and other defects;Hard coding is mainly based on high-performance GPU graphics processor, FPGA special chip and other hardware devices or board cards with video coding and decoding capability, and the computing resources of the host device are released, and the board card overall power consumption is increased by the FPGA chip, the cost is increased, and the video data forwarding times are also increased, which leads to large coding delay and low performance. And when the traditional video coding device is used for multi-channel video coding, not only multiple video coding devices are needed, but also multiple interfaces connected with the video coding device are needed in the host device, which causes resource waste and large size.

[0004] Therefore, a new multi-channel video coding technology is needed. UTILITY MODEL CONTENT

[0005] In view of the above analysis, the utility model aims at providing a multi-channel video processing board card to solve the problems of low video processing efficiency and high cost in the prior art.

[0006] The utility model mainly aims at realizing the following technical schemes:

[0007] The board card includes a first high-speed data bus interface, a bridge chip and multiple video processing modules;

[0008] One end of the first high-speed data bus interface is used as an external interface of the board card and is connected with the host device;The other end of the first high-speed data bus interface is connected with one end of the bridge chip, and the video stream is transmitted between the host device and the bridge chip;

[0009] The other end of the bridge chip is connected with multiple video processing modules respectively, and the video stream is transmitted between the bridge chip and each video processing module.

[0010] Based on the further improvement of the above scheme, the first high-speed data bus interface is a PCIe data bus interface;

[0011] The bridge chip is a PCIe bridge chip.

[0012] Based on the further improvement of the above scheme, the video processing module comprises a second high-speed data bus interface, a DDR memory, an eMMC memory and a video processor.

[0013] One end of the second high-speed data bus interface is connected to the other end of the bridge chip.

[0014] The other end of the second high-speed data bus interface, the DDR memory and the eMMC memory are respectively connected to the video processor.

[0015] Based on the further improvement of the above scheme, the second high-speed data bus interface is any of the following interfaces:

[0016] PCIe data bus interface;

[0017] USB interface;

[0018] RGMII interface.

[0019] Based on the further improvement of the above scheme, the video processor is at least one of the following:

[0020] Video encoder;

[0021] Video decoder;

[0022] Video preprocessor;

[0023] Video postprocessor.

[0024] Based on the further improvement of the above scheme, the model of the video processor is any of the following:

[0025] RK3588;

[0026] RK3588S;

[0027] RK3576.

[0028] Based on the further improvement of the above scheme, the PCIe bridge chip is any of the following models:

[0029] SM8724;

[0030] PEX8724;

[0031] ASM2824;

[0032] VL805;

[0033] ASM3242;

[0034] μPD720201;

[0035] I350;

[0036] WX1860AL4;

[0037] N500。

[0038] Based on the further improvement of the above scheme, the video processing module further comprises a power management chip;

[0039] The power management chip is connected with the video processor, the DDR memory and the eMMC memory respectively.

[0040] Based on the further improvement of the above scheme, the eMMC memories of the plurality of video processing modules are arranged on one side of the board card;

[0041] The bridge chip, the second high-speed data bus interface, the DDR memory, the video processor and the power management chip of the plurality of video processing modules are arranged on the other side of the board card.

[0042] Based on the further improvement of the above scheme, the board card comprises an even number of video processing modules, and the even number of video processing modules are symmetrically arranged on the board card.

[0043] Compared with the prior art, the utility model at least can realize following beneficial effect one:

[0044] 1、 through high speed data bus, video stream of host device is transmitted to multiple video processing modules, realizes to video stream high concurrent number and high performance density processing, has improved video processing efficiency;

[0045] 2、 through setting up the video processor, realize different processing to video stream, improve the richness of video processing;

[0046] 3、 through one high speed data bus interface simultaneously connects multiple video processing modules, reduced the interface that needs multiple connection of host device in prior art, namely can realize multiple video processing, greatly reduced cost.

[0047] In the utility model, the above each technical scheme can be combined with each other to realize more preferred combination scheme.The other features and advantages of the utility model will be described in the following content, and part of the advantages can become apparent from the specification, or be understood by implementing the utility model.The purpose and other advantages of the utility model can be realized and obtained by the content specially pointed out in the text and the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0048] The drawings are only for showing the purpose of specific embodiment, and are not considered as the limitation of the utility model, and the same reference signs indicate the same parts in the whole drawings.

[0049] Figure 1 A schematic diagram of the structure of a multi-channel video processing board provided by this utility model;

[0050] Figure 2 A schematic diagram of the structure of the video processing module provided by this utility model;

[0051] Figure 3 A front view of a multi-channel video processing board provided by this utility model;

[0052] Figure 4 This is a schematic diagram of the reverse side structure of a multi-channel video processing board provided by this utility model.

[0053] Figure label:

[0054] 1-Board; 2-First high-speed data bus interface; 3-Bridge chip; 4, 5, 6, 7-Multiple video processing modules. Detailed Implementation

[0055] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0056] A specific embodiment of this utility model discloses a multi-channel video processing board, such as... Figure 1 As shown, the board includes a first high-speed data bus interface, a bridge chip, and multiple video processing modules;

[0057] One end of the first high-speed data bus interface serves as the external interface of the board, connecting to the host device; the other end of the first high-speed data bus interface is connected to one end of the bridge chip, transmitting the video stream between the host device and the bridge chip.

[0058] The other end of the bridging chip is connected to multiple video processing modules, transmitting the video stream between the bridging chip and each video processing module.

[0059] Specifically, such as Figure 1 As shown, the multi-channel video processing board provided by this utility model transmits the video stream to be processed on the host device to the bridge chip 3 through the first high-speed data bus interface 2, and then transmits it to one or more designated video processing modules for video processing through the bridge chip. The processed video is then transmitted back to the bridge chip and then transmitted to the host device through the first high-speed data bus, thus completing the processing of the video stream in the host device.

[0060] Specifically, Figure 14, 5, 6, 7 are a plurality of video processing modules in the board card, the board card connects a bridge chip arranged on the board card and a corresponding slot of the host device through a first high-speed data bus interface, the bridge chip is connected with the plurality of video processing modules respectively, and data processing of a video stream is performed.

[0061] Preferably, the first high-speed data bus interface is a PCIe data bus interface.

[0062] The bridge chip is a PCIe bridge chip.

[0063] Specifically, the PCIe data bus interface connects a PCIe bridge chip arranged on the board card and a corresponding PCIe slot of the host device, and the PCIe bridge chip is connected with the plurality of video processing modules respectively, so as to realize processing of a video stream in the host device.

[0064] It is worth noting that the PCIe data bus interface and the size and other parameters fully comply with the standard PCIe specification, and can be compatible with and adapted to common host devices with PCIe 8x and above slots.

[0065] Preferably, the PCIe bridge chip is any one of the following models:

[0066] SM8724;

[0067] PEX8724;

[0068] ASM2824;

[0069] VL805;

[0070] ASM3242;

[0071] μPD720201;

[0072] I350;

[0073] WX1860AL4;

[0074] N500.

[0075] Specifically, SM8724, PEX8724 and ASM2824 are three chips that are functionally compatible and support in-situ replacement, and are all PCIe3.0 switching chips; SM8724 is a PCIe3.0 switch, has 24 channels, and has a maximum of 6 ports, and can realize data exchange between the ports; PEX8724 is a high-performance, low-power 6-port PCIe 3.0 switching chip, has 24 channels, and is functionally compatible with SM8724; ASM2824 is a low-latency, low-cost, low-power 24-channel, and a maximum of 12 downstream port packet switch.

[0076] Specifically, VL805, ASM3242 and μPD720201 are three functionally compatible chips that can be functionally replaced and are all PCIe signal to USB3.0 signal conversion chips; VL805 is a powerful USB 3.0 host controller that can realize PCIe platform bus control, supports USB super-speed, high-speed, full-speed and low-speed devices, has an x1 PCIe 2.0 bus interface, backward compatible with PCIe 1.0, and complies with the Universal Serial Bus 3.0 specification and Intel's Extensible Host Controller Interface (xHCI) to ensure seamless connection of USB devices; ASM3242 is a high-performance PCIe 3.0 to USB 3.2 conversion chip; and μPD720201 has the same function as VL805 and ASM3242.

[0077] Specifically, I350, WX1860AL4 and N500 are three chips with the same function, which are all PCIe signal to network signal conversion network controller chips.

[0078] Preferably, the video processing module comprises a second high-speed data bus interface, a DDR memory, an eMMC memory and a video processor.

[0079] One end of the second high-speed data bus interface is connected to the other end of the bridge chip.

[0080] The other end of the second high-speed data bus interface, the DDR memory and the eMMC memory are respectively connected to the video processor.

[0081] Specifically, as shown in Figure 2 Fig. 4, the second high-speed data bus interface 41 is taken as an example, which is connected to the bridge chip 3 as the entrance of the video processing module and is used for video stream transmission, and the video processor 42 is connected to the bridge chip 3 through the second high-speed data bus interface 41 for video stream transmission. The LPDDR4X memory 1 43 and the LPDDR4X memory 2 44 are used as the DDR memory of the video processing module, and the eMMC memory 45 stores programs.

[0082] Specifically, when the video stream to be processed is transmitted to the video processor 42 through the second high-speed data bus interface 41, the video processor 42 processes the video stream by loading the programs in the eMMC memory 45, and the temporary files generated in the processing process are stored in the DDR memory, such as the LPDDR4X memory 1 43 or the LPDDR4X memory 2 44. After the video processor 42 completes the processing of the video stream, the video stream is transmitted to the bridge chip 3 through the second high-speed data bus interface 41, and the bridge chip 3 transmits the processed video stream to the host device.

[0083] Preferably, the second high-speed data bus interface is any one of the following interfaces:

[0084] a PCIe data bus interface;

[0085] a USB interface;

[0086] a RGMII interface.

[0087] Specifically, as shown in the figure, Figure 2 the second high-speed data bus interface is a PCIe data bus interface, a USB interface, and a RGMII interface according to different video processors. It is worth noting that a matching bridge PCIe bridge chip is selected at the same time to realize the transmission of the video stream of the host device to the video processor for data processing.

[0088] Preferably, the video processor is at least one of the following:

[0089] a video encoder;

[0090] a video decoder;

[0091] a video pre-processor;

[0092] a video post-processor.

[0093] Specifically, the video encoder is used for encoding the video stream, the video decoder is used for decoding the video stream, the video pre-processor is used for video noise reduction, video scaling, and color correction of the video stream, and the video post-processor is used for video super-resolution, frame interpolation, and ROI of the video stream.

[0094] Preferably, the model of the video processor is any one of the following:

[0095] RK3588;

[0096] RK3588S;

[0097] RK3576.

[0098] Specifically, RK3588, RK3588S, and RK3576 are general SoC chips, and their functions are roughly the same, all of which have video encoding and decoding and artificial intelligence computing capabilities.

[0099] Specifically, RK3588 is a SoC chip launched by Rockchip, which adopts 8nm LP process; it is equipped with an eight-core 64-bit CPU with a clock speed of up to 2.4GHz; it supports 8K video encoding and decoding, and is embedded with a high-performance NPU and GPU, which can provide 6Tops computing power and support mainstream deep learning frameworks. It is widely used in ARM PC, edge computing, smart home and other fields. This chip not only integrates a variety of high-performance processing units, but also shows extraordinary strength in power consumption control, graphics processing, video encoding and decoding, and artificial intelligence computing capabilities.

[0100] Specifically, RK3588S has basically the same function as RK3588, but it has cut the PCIe interface, and other performance remains unchanged, and it is more power-efficient.

[0101] Specifically, RK3576 is an 8nm process high-performance SoC chip launched by Rockchip, which is built-in 4-core Cortex-A72 and 4-core Cortex-A53 processors and independent NEON coprocessor, with a clock speed of 2.2GHz; 6TOPS computing power NPU; can support 8K30@FPS and 4K120@FPS video decoding, suitable for industrial, AIoT, edge computing, smart mobile terminal and other digital multimedia scenarios.

[0102] Preferably, the video processing module further comprises a power management chip;

[0103] The power management chip is connected with the video processor, the DDR memory and the eMMC memory respectively.

[0104] Specifically, as shown in Figure 2 The power management chip 46 is connected with the eMMC memory 45, the LPDDR4X memory 1 43, the LPDDR4X memory 2 44 and the video processor 42, and is used to provide stable power supply.

[0105] Preferably, the eMMC memories of the plurality of video processing modules are arranged on one side of the board card;

[0106] The bridge chip, the second high-speed data bus interface, the DDR memory, the video processor and the power management chip of the plurality of video processing modules are arranged on the other side of the board card.

[0107] Specifically, as shown in Figure 3 and 4 The side of the board card 1 is called the back side, and the other side is called the front side. The first high-speed data bus interface 2 is arranged on the front side and the back side of the board card 1 respectively. The first high-speed data bus interface 2 serves as an external interface of the board card and is connected with a host device. At the same time, the eMMC memories of the plurality of video processing modules are arranged on the back side of the board card 1.

[0108] Specifically, in Figure 3 and Figure 4 , 42, 43, 44, 45, 46 are video processors, LPDDR4X memories 1, LPDDR4X memories 2 and eMMC memories and power management chips of the video processing module 4 respectively; 52, 53, 54, 55, 56 are video processors, LPDDR4X memories 1, LPDDR4X memories 2 and eMMC memories and power management chips of the video processing module 5 respectively; 62, 63, 64, 65, 66 are video processors, LPDDR4X memories 1, LPDDR4X memories 2 and eMMC memories and power management chips of the video processing module 6 respectively; 72, 73, 74, 75, 76 are video processors, LPDDR4X memories 1, LPDDR4X memories 2 and eMMC memories and power management chips of the video processing module 7 respectively.

[0109] The second high-speed data bus interface, the DDR memory, the video processor and the power management chip of the plurality of video processing modules are arranged on the front surface of the board card, and the bridge chip is arranged on the front surface of the board card.

[0110] Preferably, the board card comprises an even number of video processing modules, and the even number of video processing modules are symmetrically arranged on the board card.

[0111] Specifically, an even number of video processing modules are arranged on one board card and symmetrically distributed on the board card, which can further reduce the volume of the board card and reduce the cost.

[0112] Compared with the prior art, the multi-channel video processing board card provided in the embodiment of the utility model realizes high concurrent number and high performance density processing of the video stream by transmitting the video stream of the host device to the plurality of video processing modules through the high-speed data bus, improves the efficiency of video processing, and realizes different processing of the video stream through the video processor arranged, and improves the richness of video processing.

[0113] The above is only a preferred specific embodiment of the utility model, but the protection scope of the utility model is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the utility model, which should be covered in the protection scope of the utility model.

Claims

1. A multi-path video processing board card, characterized in that, The board card comprises a first high-speed data bus interface, a bridge chip and a plurality of video processing modules; One end of the first high-speed data bus interface serves as an external interface of the board card and is connected to a host device; The other end of the first high-speed data bus interface is connected to one end of the bridge chip, and video streams are transmitted between the host device and the bridge chip; The other end of the bridge chip is connected to the plurality of video processing modules respectively, and video streams are transmitted between the bridge chip and each video processing module.

2. The board card according to claim 1, characterized in that, The first high-speed data bus interface is a PCIe data bus interface; The bridge chip is a PCIe bridge chip.

3. The board card of claim 2, wherein, The video processing module comprises a second high-speed data bus interface, a DDR memory, an eMMC memory and a video processor; One end of the second high-speed data bus interface is connected to the other end of the bridge chip; The other end of the second high-speed data bus interface, the DDR memory and the eMMC memory are connected to the video processor respectively.

4. The board card of claim 3, wherein, The second high-speed data bus interface is any of the following interfaces: PCIe data bus interface; USB interface; RGMII interface.

5. The board card of claim 3, wherein, The video processor is at least one of the following: Video encoder; Video decoder; Video pre-processor; Video post-processor.

6. The board card of claim 5, wherein, The model of the video processor is any of the following: RK3588; RK3588S; RK3576.

7. The board card of claim 2, wherein, The PCIe bridge chip is any of the following models: SM8724; PEX8724; ASM2824; VL805; ASM3242; μPD720201; I350； WX1860AL4; N500。 8. The board card of claim 3, wherein, The video processing module further comprises a power management chip; The power management chip is connected to the video processor, the DDR memory and the eMMC memory respectively.

9. The board card of claim 8, wherein, The eMMC memories of the plurality of video processing modules are arranged on one side of the board card; The bridge chip, and the second high-speed data bus interfaces, the DDR memories, the video processors and the power management chips of the plurality of video processing modules are arranged on the other side of the board card.

10. The board card according to any one of claims 1 to 9, characterized in that, The board card comprises an even number of video processing modules, and the even number of video processing modules are symmetrically arranged on the board card.

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