Electronic device and system including the same

Abstract

An electronic device including a semiconductor-based power transistor and a system including the electronic device are provided. An example electronic device includes a transistor. The transistor includes: a p-doped semiconductor first layer; a piezoelectric semiconductor second layer covering the first layer; a piezoelectric semiconductor third layer covering the second layer; a piezoelectric semiconductor fourth layer covering the third layer; and a piezoelectric semiconductor fifth layer overlying the fourth layer, the transistor configured to generate a first two-dimensional electron gas between the fourth and fifth layers; and a gate pattern crossing through at least a portion of the fourth layer and the fifth layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French Patent Application No. FR2402000 entitled “Dispositifélectronique”, filed February 29, 2024, and U.S. Patent Application No. 19 / 056,258 entitled “ELECTRONIC DEVICE”, filed February 18, 2025, which are incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic devices, and more particularly to electronic devices including semiconductor-based power transistors. Background Technology

[0004] In the field of power electronics, a major challenge involves the development of power transistors based on “large bandgap” semiconductors, such as GaN.

[0005] Different architectures have been specifically developed for these GaN-based transistors. Architectures based on the use of two-dimensional electron gases (2DEG) typically allow operation with high source-drain bias voltages. A positive threshold voltage advantageously simplifies the transistor's control circuitry and ensures the safety of the switching system in the event of a failure. Utility Model Content

[0006] One embodiment provides an electronic device including a transistor comprising: a p-doped semiconductor first layer; a piezoelectric semiconductor second layer covering the first layer; a piezoelectric semiconductor third layer covering the second layer; a piezoelectric semiconductor fourth layer covering the third layer; a piezoelectric semiconductor fifth layer covering the fourth layer, the transistor being configured to generate a first two-dimensional electron gas between the fourth and fifth layers; and a gate pattern intersecting at least a portion of the fourth layer and the fifth layer.

[0007] According to an embodiment, the transistor is configured to generate a second two-dimensional electron gas between the second and third layers, and the first layer is configured to suppress the second electron gas.

[0008] According to an embodiment, the gate pattern intersects with at least a portion of the second layer, the third layer, the fourth layer, and the fifth layer.

[0009] According to an embodiment, the second and fourth layers are made of the same material.

[0010] According to an embodiment, the second and fourth layers are made of GaN.

[0011] According to an embodiment, the third and fifth layers are made of the same material.

[0012] According to embodiments, the third layer and the fifth layer are made of AlGaN, AsGa, AlN or InGaN.

[0013] According to embodiments, the first layer is made of GaN doped with magnesium, carbon or iron.

[0014] According to embodiments, the first layer is configured to be biased.

[0015] According to embodiments, the gate pattern separates at least the fifth layer into a first portion and a second portion.

[0016] According to embodiments, the gate pattern separates the third layer, the fourth layer and the fifth layer into a first portion and a second portion.

[0017] According to embodiments, the device comprises a first electrode in contact with the first portion of the fifth layer and a second electrode in contact with the second portion of the fifth layer.

[0018] According to embodiments, the first layer is configured to be biased with the same voltage as the first electrode or the second electrode.

[0019] Another embodiment provides a system comprising the electronic device of the present disclosure, the system further comprising: an on-board charger in an electric vehicle, a charging station, a photovoltaic system, a household appliance, a telecommunication system, a data center, a server, a light emitting diode lighting system or equipment requiring power conversion. BRIEF DESCRIPTION OF DRAWINGS

[0020] The foregoing features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0021] Figure 1 Fig. illustrates an example of an electronic device comprising a semiconductor-based power transistor;

[0022] Figure 2 Fig. illustrates an embodiment of an electronic device comprising a semiconductor-based power transistor;

[0023] Figure 3 Fig. illustrates Figure 2 the behavior of an electronic device; and

[0024] Figure 4 Fig. illustrates another embodiment of an electronic device comprising a semiconductor-based power transistor. DETAILED DESCRIPTION

[0025] In the various drawings, like features have been designated by like reference numerals. In particular, structural and / or functional features common among the various embodiments can have the same designation, and can have the same structure, dimensions and material properties.

[0026] For the sake of clarity, only the operations and elements of the embodiments helpful for understanding the present application have been illustrated and described.

[0027] Unless indicated otherwise, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements can be connected or they can be coupled through one or more other elements.

[0028] In the following disclosure, unless indicated otherwise, when referring to an absolute position qualifier such as the terms "front", "back", "top", "bottom", "left", "right", etc. or to a relative position qualifier such as the terms "above", "below", "higher", "lower", etc. or to an orientation qualifier such as "horizontal", "vertical", etc., reference is made to the orientation shown in the drawings.

[0029] Unless otherwise indicated, the expressions "about", "approximately", "substantially" and "roughly" mean within 10% and preferably within 5%.

[0030] Figure 1 An example of an electronic device comprising a semiconductor-based power transistor is illustrated.

[0031] More precisely, Figure 1 A part of a device comprising a power transistor 10 is schematically illustrated. The transistor 10 is a high electron mobility transistor (HEMT) type transistor. Such a transistor is a field effect transistor with high electron mobility, sometimes also referred to as a heterostructure field effect transistor.

[0032] The transistor 10 comprises a stack 12 of layers 14, 16, 18, 20, 22. The stack 12 is for example located in or on a semiconductor substrate 13. The substrate 13 is for example made of silicon, sapphire or SiC. In Figure 1 In an example, the stack 12 is located on an upper surface of the substrate 13.

[0033] The layer 14 is a buffer layer. The layer 14 can correspond to several buffer layers. The buffer layer 14 is for example made of AIN, GaN or AlGaN.

[0034] The layer 16 is made of a piezoelectric material, for example of GaN. The layer 16 is for example intrinsic or unintentionally doped. In other words, the layer 16 is undoped or doped with a doping concentration lower than 1014cm"3. The layer 16 is located on the layer 14 and for example in contact with the layer 14. The layer 16 is for example floating. In other words, the layer 16 is for example not biased. Alternatively, the layer 16 is biased by a reference voltage, for example ground.

[0035] The layer 18 forming the back barrier is made of a piezoelectric material, such as AlGaN. The proportion of aluminum is, for example, higher than 4%. Layer 18 is situated on layer 16 and, for example, in contact with layer 16. Layer 18 is, for example, floating.

[0036] The layer 20 forming the channel is made of a piezoelectric material, such as GaN. The layer 20 is located on the layer 18 and, for example, in contact with the layer 18.

[0037] The barrier layer 22 is made of a piezoelectric material, such as AlGaN. The proportion of aluminum is, for example, greater than 4%. Layer 22 is located on layer 20 and, for example, in contact with layer 20. Layer 22 does not completely cover layer 20, for example. In other words, a portion of layer 20 (e.g., a portion of the upper surface of layer 20) is not covered by layer 22.

[0038] Transistor 10 includes a gate pattern 24. Gate pattern 24 is located in cavity 26. The cavity extends from the upper surface of layer 22 through a portion of layers 22 and 20. In other words, cavity 26 extends through the interface between layers 20 and 22. Cavity 26 extends through layers 18, 20, and 22 and through a portion of layer 16. In other words, Figure 1 The bottom of cavity 26 is located in layer 16.

[0039] Layers intersecting with the cavity (e.g., Figure 1 Layers 18, 20, and 22 are divided into two parts by cavity 26. Layer 18 is divided into parts 18a and 18b, which are not in contact with each other. Layer 20 is divided into parts 20a and 20b, which are not in contact with each other. Layer 22 is divided into parts 22a and 22b, which are not in contact with each other. Parts 18a, 20a, and 22a form a secondary stack 12a, and parts 18b, 20b, and 22b form a secondary stack 12b. The secondary stacks 12a and 12b are separated by cavity 26.

[0040] Layer 16 is a continuous layer. In other words, layer 16 is made of a single portion. The portions of layer 16 facing portions 18a, 20a, 22a (e.g., in contact with portion 18a) and the portions of layer 16 facing portions 18b, 20b, 22b (e.g., in contact with portion 18b) are in contact with each other. Therefore, the portions of layer 16 are not separated by layers of different materials.

[0041] The gate pattern 24 comprises a dielectric layer 28 and a conductive layer 30. The layer 28 conformally covers the cavity 28 and a portion of the upper surface of the layer 22 surrounding the cavity 26. In other words, the layer 28 covers the lateral surfaces of the layers 16, 18, 20, 22 forming the walls of the cavity, the surface of the layer 16 forming the bottom of the cavity 26 and a portion of the upper surface of the layer 22 surrounding the cavity 26. The layer 30 conformally covers the layer 28. Preferably, the layer 30 completely and only covers the layer 28. The layer 30 is thus separated from the stack 12 by the layer 28.

[0042] The transistor 10 comprises a drain electrode 32 and a source electrode 34. The drain electrode 32 is in contact with both layers 20 and 22 on one side of the cavity 26 and the source electrode 34 is in contact with both layers 20 and 22 on the other side of the cavity 26. More precisely, the drain electrode 32 is in contact with portions 20a and 22a of the layers 20 and 22 and the source electrode 34 is in contact with portions 20b and 22b of the layers 20 and 22. In the example of Fig. 1, the drain electrode 32 covers a portion of the upper surface of the portion 22a, a portion of the upper surface of the portion 20a not covered by the portion 22a and a lateral surface of the portion 22a. Similarly, the source electrode 34 covers a portion of the upper surface of the portion 22b, a portion of the upper surface of the portion 20b not covered by the portion 22b and a lateral surface of the portion 22b. Figure 1

[0043] The architecture of a HEMT transistor, such as the transistor 10, comprises a superposition of two semiconductor layers with different bandgaps, which form a quantum well at their interface. This quantum well is induced by the present spontaneous and piezoelectric bias charges. Electrons are confined in this quantum well to form a two-dimensional electron gas (2DEG). In the stack 12 of Fig. 1, the two-dimensional electron gas 36 is formed in the layer 20 just below the layer 22. The two-dimensional electron gas 36 is generally confined at the interface between the layers 20 and 22. The layers 20 and 22 form a heterojunction. Figure 1

[0044] The gate pattern 24 crosses this interface between the layers 20 and 22 to interrupt the two-dimensional electron gas 36. The control gate voltage Vgs is such that the passage of electrons of the two-dimensional electron gas 36 can be enabled or blocked on either side of the gate pattern 24.

[0045] Generally, if the gate of a transistor is set to a voltage greater than the threshold voltage, there is an accumulation of electrons just below the gate dielectric, thus connecting the two-dimensional electron gas on either side, which makes it possible to connect the source and the drain to put the transistor into the on state. Thus, when the gate pattern 24 is in a state enabling the passage of electrons, the two-dimensional electron gas 36 extends between the portions 20a and 22a, along the walls and the bottom of the cavity 26 and between the portions 20b and 22b.

[0046] ​​If the gate of the transistor is set at a voltage less than the threshold voltage, the source and the drain are no longer connected and the transistor enters the off state.

[0047] A second two-dimensional electron gas 38 is formed in the layer 16 just below the layer 18. The two-dimensional electron gas 38 is generally confined to the interface between the layers 16 and 18. The two-dimensional electron gas 38 generates an unwanted constant leakage current flowing between the drain and the source of the transistor 10.

[0048] Figure 2 Embodiments of an electronic device comprising a semiconductor-based power transistor 11 are illustrated. More precisely, Figure 2 A part of a device comprising a power transistor 11 is schematically illustrated. The transistor 11 is a high electron mobility transistor (HEMT) type transistor. Such a transistor is a field effect transistor with high electron mobility, sometimes also called heterostructure field effect transistor.

[0049] The device is for example intended to be used in the automotive industry. The electrification of the automotive vehicles creates an extended high level of electronic content in the vehicles. The device comprises for example high electron mobility transistors (HEMTs) to be included in the vehicles. The automation of the driving also creates an extended high level of electronic content in the vehicles.

[0050] The device can for example be used in the industrial field. More particularly, the device is for example intended to be used in the development of green energy or in the electrification of infrastructures, for example for charging stations or for the incorporation of solar energy. The device can also be used in the field of the Internet of Things and smart homes. The device is for example intended to be implemented in the power and energy circuits of the equipment, including for example 650V or 1200V HEMTs, 1200V super-fast and silicon carbide diodes, transient voltage suppression diodes, and electromagnetic discharge protection devices. The device can also be used for the implementation of clouds, 5G networks, data centers and servers. The device comprises for example wide bandgap materials.

[0051] The device is for example intended to be used in personal electronic products, for example intended to increase the radio frequency content, devices for 5G connection or more generally devices for connection. The device is for example part of a smart phone or of a network of the Internet of Things. The device is for example connected by 5G, WIFI or ultra-wide band. The device comprises for example high speed interfaces, for example with high level filtering and electromagnetic discharge protection means.

[0052] The device is for example intended to be used in communication equipment, or in computers and peripherals. For example, the device can be used in 5G infrastructure and dedicated data centers. The device comprises for example silicon carbide diodes, power Schottky transistors, electromagnetic discharge protection devices and transient voltage suppression diodes. The device can also be used in satellites, satellites comprising for example integrated passive devices for radio frequency applications.

[0053] The disclosed device comprises a HEMT type transistor. HEMT type transistors are typically used for high frequency and high power applications, such as satellite communications, radar systems, battery chargers, computers, servers, cars, lightning protection systems and photovoltaic systems, microwave amplifiers and all equipment requiring power conversion (for example DC / DC or AC / DC or AC / AC or DC / AC power conversion). HEMT type transistors can also be used for some dedicated personal electronic devices, such as high-end audio amplifiers or radio frequency (RF) transmitters. HEMT type transistors are increasingly used for car electrification, in particular for electric and hybrid vehicles.

[0054] Like the device 10 of Fig. 1, Figure 1 The transistor 11 comprises a stack 12 of layers 14, 16, 18, 20, 22, like the device 10 of Fig. 1. In the embodiment of Fig. 1, Figure 2 The stack 12 further comprises a layer 15, in the embodiment of Fig. 1. Preferably, the layers 14, 15, 16, 18, 20, 22 of the stack 12 are arranged in this order from the substrate. The stack 12 is for example located in or on a semiconductor substrate 13. The substrate is for example made of silicon, sapphire or SiC.

[0055] The layer 14 is a buffer layer. The layer 14 can correspond to several buffer layers. The buffer layer 14 is for example made of AlGaN, AlN or GaN. The layer 14 is for example the lowest layer of the stack 12. In other words, the layer 14 is for example the layer closest to the substrate 13.

[0056] The layer 15 is a semiconductor layer. The layer 15 is p-doped. For example, the layer 15 is made of GaN. For example, the layer 15 is doped with magnesium, carbon or iron. The layer 15 is for example the second lowest layer of the stack 12. The layer 15 is for example separated (preferably completely) from the substrate by the layer 14. The doping concentration is for example higher than 1017cm-3, for example substantially equal to 1018cm-3.

[0057] Preferably, the layer 15 is floating. In other words, the layer 15 is preferably not biased. Alternatively, the layer 15 is biased by a reference voltage (for example ground).

[0058] The layer 16 is made of a piezoelectric material, preferably of a piezoelectric semiconductor material. The layer 16 constitutes a buried channel or sandwich. The layer 16 is preferably made of a material configured to be formed on the layer 15 (e.g. by epitaxial growth). The layer 16 is for example made of GaN. The layer 16 is preferably intrinsic or unintentionally doped. In other words, the layer 16 is un-doped or doped with a doping concentration lower than 1014cm-3. For example, the layer 16 is made of the same material as the layer 15.

[0059] The layer 16 is for example the third lowest layer of the stack 12. The layer 16 is for example located on the layer 15 and preferably in contact with the layer 15. The layer 16 is for example separated (preferably completely) from the layer 14 by the layer 15.

[0060] The layer 16 is preferably floating. In other words, the layer 16 is preferably not biased. Alternatively, the layer 16 is biased by a reference voltage (e.g. ground).

[0061] The layer 18 is made of a piezoelectric material, preferably of a piezoelectric semiconductor material. The layer 18 constitutes a back barrier. The layer 18 is preferably made of a material configured to be formed on the layer 16 (e.g. by epitaxial growth). The layer 18 is made of a different material than the material of the layer 16. The layer 18 is for example made of AlGaN, InGaN, AsGa or AlN. Preferably, the layer 18 is made of AlGaN with a proportion of aluminum higher than 4%.

[0062] The layer 18 is for example the fourth lowest layer of the stack 12. The layer 18 is for example located on the layer 16 and preferably in contact with the layer 16. The layer 18 is for example separated (preferably completely) from the layer 15 by the layer 16. The layer 18 is preferably not in contact with the layer 15.

[0063] The layer 18 is preferably floating. In other words, the layer 18 is preferably not biased. Alternatively, the layer 18 is biased by a reference voltage (e.g. ground).

[0064] The layer 20 is made of a piezoelectric material, preferably of a piezoelectric semiconductor material. The layer 20 constitutes a channel. The layer 20 is preferably made of a material configured to be formed on the layer 18 (e.g. by epitaxial growth). The layer 20 is made of a different material than the material of the layer 18. For example, the material of the layer 20 is the same material as the material of the layer 16. The layer 20 is for example made of GaN.

[0065] The layer 20 is for example the fifth lowest layer of the stack 12. The layer 20 is for example located on the layer 18 and preferably in contact with the layer 18. The layer 20 is for example separated (preferably completely) from the layer 16 by the layer 18. The layer 18 is preferably not in contact with the layers 15 and 16.

[0066] The layer 22 is made of a piezoelectric material, preferably of a piezoelectric semiconductor material. The layer 22 constitutes a potential barrier. The layer 22 is preferably made of a material configured to be formed on the layer 20 (e.g. by epitaxial growth). The layer 22 is made of a material different from the material of the layer 20. The layer 22 is for example made of the same material as the layer 18. The layer 22 is for example made of AlGaN, InGaN, AsGa or AlN. Preferably, the layer 22 is made of AlGaN, with a proportion of aluminum higher than 4%.

[0067] The layer 22 is for example the uppermost layer of the stack 12, in other words the layer that is the furthest from the substrate and the furthest from a buffer layer not shown. The layer 22 is for example located on the layer 20 and preferably in contact with the layer 20. The layer 22 is for example separated (preferably completely) from the layer 18 by the layer 20. The layer 22 is preferably not in contact with the layers 14, 15, 16, 18. The layer 22 does not for example completely cover the layer 20. In other words, a portion of the layer 20 (for example a portion of the upper surface of the layer 20) is not covered by the layer 22.

[0068] According to an embodiment, the layers 16, 18, 20 and 22 are all made of different piezoelectric materials. According to another embodiment, the layers 16 and 20 are made of the same material and the layers 18 and 22 are made of the same material.

[0069] Preferably, each of the layers 14, 15, 16, 18, 20, 22 is a homogenous layer. Preferably, each of the layers 14, 15, 16, 18, 20, 22 is made of a single material.

[0070] The layer 16 has for example a doping concentration lower than 1014cm-3. The layer 18 has a thickness between 20 nm and 150 nm. The layer 20 has for example a doping concentration lower than 1014cm-3. The layer 20 has for example a thickness between 50 nm and 200 nm. The layer 22 has a thickness between 20 nm and 100 nm.

[0071] The semiconductor material of the transistor 10 is for example chosen to have a wide energy band gap for power handling (in particular, high voltage) and temperature handling reasons.

[0072] The transistor 11 comprises a gate pattern 24. The gate pattern 24 is located in a cavity 26. The cavity extends from the upper surface of the layer 22. The cavity 26 extends at least through the layer 22 and a portion of the layer 20. In other words, the cavity 26 extends through the interface between the layers 20 and 22. In Figure 2 In an embodiment, the cavity 26 extends through the layers 18, 20, 22 and through a portion of the layer 16. In other words, the cavity 26 extends through the interface between the layers 16 and 18. Figure 2 The bottom of the cavity 26 of the transistor 11 is located in the layer 16. Preferably, the bottom of the cavity 26 is located between the interface of the layers 20 and 22 and the layer 16.

[0073] Layers (e.g., layers 18, 20, 22) that cross the cavity are divided into two parts by the cavity 26. Layer 18 is divided into parts 18a and 18b, which do not contact each other. Layer 20 is divided into parts 20a and 20b, which do not contact each other. Layer 22 is divided into parts 22a and 22b, which do not contact each other. Parts 18a, 20a, 22a form secondary stack 12a, and parts 18b, 20b, and 22b form secondary stack 12b. Secondary stacks 12a and 12b are separated by the cavity 26. Figure 2

[0074] The gate pattern 24 includes a dielectric layer 28 and a conductive layer 30. Layer 28 conformally covers the cavity 28 and a portion of the upper surface of layer 22 that surrounds the cavity 26. In other words, layer 28 covers the lateral surfaces of layers 16, 18, 20, 22 that form the walls of the cavity, the surface of layer 16 that forms the bottom of the cavity 26, and a portion of the upper surface of layer 22 that surrounds the cavity 26. Layer 30 conformally covers layer 28. Preferably, layer 30 completely and only covers layer 28. Layer 30 is thus separated from stack 12 by layer 28.

[0075] The transistor 11 includes a drain electrode 32 and a source electrode 34. Drain electrode 32 contacts both layers 20 and 22 on one side of the cavity 26, and source electrode 34 contacts both layers 20 and 22 on the other side of the cavity 26. More precisely, drain electrode 32 contacts parts 20a and 22a of layers 20 and 22, and source electrode 34 contacts parts 20b and 22b of layers 20 and 22. In the example of stack 12, Figure 2 In the example of stack 12, drain electrode 32 covers a portion of the upper surface of part 22a, a portion of the upper surface of part 20a that is not covered by part 22a, and a lateral surface of part 22a. Similarly, source electrode 34 covers a portion of the upper surface of part 22b, a portion of the upper surface of part 20b that is not covered by part 22b, and a lateral surface of part 22b.

[0076] The architecture of a HEMT transistor, such as transistor 11, includes a superposition of two semiconductor layers with different bandgaps, which form a quantum well at their interface. This quantum well is induced by the present spontaneous and piezoelectric bias charges. Electrons are confined in this quantum well to form a two-dimensional electron gas (2DEG). In the example of stack 12, Figure 2 In stack 12, a two-dimensional electron gas 36 is formed in layer 20 just below layer 22. Two-dimensional electron gas 36 is generally confined at the interface between layers 20 and 22. Layers 20 and 22 form a heterojunction.

[0077] ​The gate pattern 24 crosses this interface between the layers 20 and 22 to interrupt the two-dimensional electron gas 36. The gate voltage Vgs is controlled so that the passage of electrons of the two-dimensional electron gas 36 can be enabled or interrupted on either side of the gate pattern 24.

[0078] Generally, if the gate of the transistor is set to a voltage greater than the threshold voltage, there is an accumulation of electrons just under the gate dielectric, thus connecting the two-dimensional electron gas on either side of it, which makes it possible to connect the source and the drain to put the transistor into the on state. Thus, when the gate pattern 24 is in a state enabling the passage of electrons, the two-dimensional electron gas 36 extends between the portions 20a and 22a, along the walls and the bottom of the cavity 26 and between the portions 20b and 22b.

[0079] If the gate of the transistor is set to a voltage less than the threshold voltage, the source and the drain are no longer connected and the transistor enters the off state.

[0080] It would be advantageous for the threshold voltage to be positive. Indeed, if the value of the threshold voltage is relatively low (<1 V), the device can require a negative Vgs voltage to control the off state. The application of a voltage Vgs < 0 involves the use of more complex control circuits and an increase in the resistance of the transistor to the on state.

[0081] The layers 16 and 18 allow an increase in the threshold voltage towards higher values.

[0082] However, a two-dimensional electron gas 38 is formed in the layer 16 just under the layer 18. The two-dimensional electron gas 38 is generally confined to the interface between the layers 16 and 18. The two-dimensional electron gas 38 generates a constant leakage current flowing between the drain and the source of the transistor 10. This current is more important in the case where the gate pattern does not cross the interface between the layers 16 and 18.

[0083] The layer 15 is made of a p-doped semiconductor material. Thus, the layer 15 is configured to deplete the electrons in the adjacent region. In the embodiment of Figure 2 In the embodiment of the application, the thickness of the layer 16, in other words the distance between the two-dimensional electron gas 38 and the layer 15, is configured to ensure that the two-dimensional electron gas 38 is at least partially inhibited by the effect of the p-type doping of the layer 15. In other words, the layer 15 stops the current generated by the two-dimensional electron gas 38. In other words, the layer 15 is configured to deplete the two-dimensional electron gas 38.

[0084] The choice of the thickness of the layer 16 depends on the leakage current generated by the two-dimensional electron gas 38 that needs to be inhibited. In the case of a layer 18 made of AlGaN, the leakage current depends on the proportion of aluminium in the layer 18. Preferably, the thickness of the layer 16, which allows compensation of the leakage current, decreases as the proportion of aluminium increases. The thickness of the layer 16 also depends on the thickness of the layer 18.

[0085] According to a preferred embodiment, layer 15 is made of magnesium-doped GaN. Preferably, the thickness of layer 15 is greater than 10 nm, more preferably greater than 50 nm, for example, substantially equal to 100 nm. In a preferred embodiment, layer 15 is floating and does not receive a bias voltage. According to a preferred embodiment, layer 16 is made of intrinsic GaN. Preferably, layer 16 is floating. Preferably, the thickness of layer 16 is less than 150 nm, more preferably less than 100 nm. According to a preferred embodiment, layer 18 is made of AlGaN. Preferably, the proportion of aluminum in layer 18 is greater than 4%, for example, substantially equal to 4%. Preferably, layer 18 is floating. Preferably, the thickness of layer 18 is greater than 20 nm, for example, substantially equal to 75 nm. According to a preferred embodiment, layer 20 is made of intrinsic GaN. Preferably, the thickness of layer 20 is greater than 50 nm, for example, substantially equal to 80 nm. According to a preferred embodiment, layer 22 is made of AlGaN. Preferably, the proportion of aluminum in layer 22 is greater than 4%, for example, substantially equal to 25%. Preferably, the thickness of layer 22 is included between 20 nm and 100 nm, for example, substantially equal to 24 nm.

[0086] According to another embodiment, the device includes a contact element configured to bias layer 15. For example, the device includes an insulating conductive via (not shown) comprising a conductive core and an insulating sheath. The via, for example, intersects layers 16, 18, and 20 to reach the upper surface of layer 15.

[0087] Figure 3 Illustration Figure 2 The behavior of electronic devices. More precisely, Figure 3 Figure A shows the different thickness values ​​of layer 16 using curves C1, C2, C3, C4, and C5. Figure 2 The conduction band energy in different regions of transistor 11. Additionally, Figure 3 In Figures A and B, curves C6, C7, C8, C9, and C10 are used to illustrate different thickness values ​​for layer 16. Figure 2 The concentration of electrons in different regions of transistor 11. Figure 3 The diagram B corresponds to a larger size. Figure 3 The diagram shows area 41 of section A.

[0088] exist Figure 3 The diagram illustrates different examples where layer 15 has a thickness of 100 nm, layer 18 has a thickness of 75 nm, layer 20 has a thickness of 80 nm, and layer 22 has a thickness of 24 nm.

[0089] Curves C1 and C6 (C6 is identical to C7) correspond to the case where layer 16 has a thickness of 50 nm. Curves C2 and C7 correspond to the case where layer 16 has a thickness of 100 nm. Curves C3 and C8 correspond to the case where layer 16 has a thickness of 150 nm. Curves C4 and C9 correspond to the case where layer 16 has a thickness of 200 nm. Curves C5 and C10 correspond to the case where layer 16 has a thickness of 250 nm.

[0090] Figure 4 The curve of Figure 6 includes different portions corresponding to different zones of transistor 11. Portion Z22 corresponds to layer 22, portion Z20 corresponds to layer 20, portion Z18 corresponds to layer 18, portion Z16 corresponds to layer 16, and portion Z15 corresponds to layer 15.

[0091] Transistor is considered to be turned on. All curves C6 to C10 include a peak at the junction between portions Z22 and Z20, corresponding to two-dimensional electron gas 36 between the electrodes of the transistor.

[0092] In diagram B, it can be seen that curves C8, C9 and C10 include a peak at the junction between portions Z16 and Z18, corresponding to two-dimensional electron gas 38 between the electrodes of the transistor. Thus, for the thicknesses corresponding to curves C8, C9 and C10, two-dimensional electron gas 38 is not suppressed. It can also be seen that curves C6 and C7 do not include a peak at the junction between portions Z16 and Z18. Thus, for the corresponding thickness of layer 16, two-dimensional electron gas 38 is suppressed.

[0093] The thicknesses that allow the suppression of two-dimensional electron gas 38 depend on the composition of the transistor, in particular on the doping values of the different zones and on the thicknesses of the different zones. They can be determined empirically.

[0094] Figure 2 Another embodiment of an electronic device including a semiconductor-based power transistor 40 is illustrated.

[0095] Power transistor 40 includes the elements of transistor 10. Those elements will not be described in detail a second time. In other words, transistor 40 includes:

[0096] - buffer layer 14;

[0097] - p-doped layer 15,

[0098] - piezoelectric layer 16,

[0099] - piezoelectric layer 18,

[0100] - piezoelectric layer 20,

[0101] - piezoelectric layer 22,

[0102] - cavity 26,

[0103] - gate pattern 24, comprising a dielectric layer 28 and a conductive layer 30, and

[0104] - drain electrode 32.

[0105] Transistor 40 differs from transistor 11 of Figure 2 in that one of the electrodes (e.g. Figure 4 source electrode 34) is replaced by electrode 42, which is in contact with layer 15. For example, a part of the upper surface of layer 14 is not covered by layers 16, 18, 20, 22. One of the electrodes (e.g. electrode 42) covers:

[0106] - a part of the upper surface of layer 22 (e.g. part 22b),

[0107] - lateral surfaces of layers 16, 18, 20, 22, e.g. parts 18b, 20b, 22b and the lateral surface of layer 16, and

[0108] - a part of the upper surface of layer 15, which is not covered by layers 16, 18, 20, 22.

[0109] In embodiments of ​ layer 15 is biased with the same voltage as one of the electrodes (e.g. the source electrode). For example, layer 15 is biased to ground. For example, both layer 15 and source electrode 42 are biased to ground.

[0110] According to embodiments, the lateral surfaces of layers 16, 18, 20, 22 are separated from electrode 42 by a dielectric layer (not shown). The electrode is then only in contact with the upper surfaces of layers 15 and 22.

[0111] An advantage of the described embodiments is that the threshold voltage of the transistor is higher, preferably positive. The transistor is thus easier to realize and more reliable.

[0112] A further advantage of the described embodiments is that the energy consumption of the transistor is lower, because the drain current has been neutralized.

[0113] A further advantage of the described embodiments is that, because the drain current generated by two-dimensional electron gas 38 is stopped by layer 15, the bottom of cavity 26 can be higher than layer 15 without increasing the drain current.

[0114] Furthermore, the present disclosure also provides a method of using the device described in the present disclosure for an on-board charger in an electric vehicle, a charging station, a photovoltaic system, a household appliance, a telecommunication system, a data center and server, a light emitting diode lighting system or equipment requiring power conversion.

[0115] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments can be combined, and that other variations will occur to those skilled in the art.

[0116] Finally, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art, based on the above provided functional description.

Claims

1. An electronic device, comprising: The electronic device includes a transistor including: a p-doped semiconductor first layer; a piezoelectric semiconductor second layer overlying the p-doped semiconductor first layer; a piezoelectric semiconductor third layer overlying the piezoelectric semiconductor second layer; a piezoelectric semiconductor fourth layer overlying the piezoelectric semiconductor third layer; a piezoelectric semiconductor fifth layer overlying the piezoelectric semiconductor fourth layer, the transistor configured to generate a first two-dimensional electron gas between the piezoelectric semiconductor fourth layer and the piezoelectric semiconductor fifth layer; and a gate pattern intersecting at least a portion of the piezoelectric semiconductor fourth layer and the piezoelectric semiconductor fifth layer.

2. The electronic device of claim 1, wherein the transistor is configured to generate a second two-dimensional electron gas between the piezoelectric semiconductor second layer and the piezoelectric semiconductor third layer, the p-doped semiconductor first layer configured to suppress the second two-dimensional electron gas.

3. The electronic device of claim 1, wherein the gate pattern intersects at least a portion of the piezoelectric semiconductor second layer, the piezoelectric semiconductor third layer, the piezoelectric semiconductor fourth layer, and the piezoelectric semiconductor fifth layer.

4. The electronic device of claim 1, wherein the piezoelectric semiconductor second layer and the piezoelectric semiconductor fourth layer are made of the same material.

5. The electronic device of claim 1, wherein the piezoelectric semiconductor second layer and the piezoelectric semiconductor fourth layer are made of GaN.

6. The electronic device of claim 1, wherein the piezoelectric semiconductor third layer and the piezoelectric semiconductor fifth layer are made of the same material.

7. The electronic device of claim 1, wherein the piezoelectric semiconductor third layer and the piezoelectric semiconductor fifth layer are made of AlGaN, AsGa, AlN, or InGaN.

8. The electronic device of claim 1, wherein the p-doped semiconductor first layer is made of GaN doped with magnesium, carbon, or iron.

9. The electronic device of claim 1, wherein the p-doped semiconductor first layer is configured to be un-biased.

10. The electronic device of claim 1, wherein the gate pattern separates at least the piezoelectric semiconductor fifth layer into a first portion and a second portion.

11. The electronic device of claim 10, wherein the gate pattern separates the piezoelectric semiconductor third layer, the piezoelectric semiconductor fourth layer, and the piezoelectric semiconductor fifth layer into the first portion and the second portion.

12. The electronic device of claim 1, wherein the electronic device includes a first electrode in contact with the first portion of the piezoelectric semiconductor fifth layer and a second electrode in contact with the second portion of the piezoelectric semiconductor fifth layer.

13. The electronic device of claim 1, wherein the p-doped semiconductor first layer is configured to be biased with the same voltage as the first electrode or the second electrode.

14. A system comprising the electronic device of claim 1, wherein, The system further includes an on-board charger in an electric vehicle, a charging station, a photovoltaic system, a home appliance, a telecommunication system, a data center, a server, a light emitting diode lighting system, or equipment requiring power conversion.

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