Fan-out wafer level packaging chip structure with electromagnetic shielding function
By combining a multi-layer metal stacked shielding ring with a metal shielding layer, the problems of complex preparation and poor shielding effect of existing electromagnetic shielding materials are solved, realizing efficient electromagnetic shielding of fan-out wafer-level packaging, with a compact structure and easy industrial application.
Patent Information
- Application Number
- CN202423158689.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-20
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2034-12-20
AI Technical Summary
Existing electromagnetic shielding materials are complex to prepare, increasing production costs, and their shielding effect is poor at certain frequencies, affecting the performance of semiconductor devices. Furthermore, their application in fan-out wafer-level packaging is not yet mature.
The structure employs a multi-layered metal stacked shielding ring and a metal shielding layer bonded to the back of the chip. The shielding layer consists of materials such as ferromagnetic metals and their alloys, cobalt-nickel alloys, and copper, with a thickness of 10-60 micrometers. The shielding layer is embedded in the packaging material through the adhesive layer, and the electromagnetic shielding function is achieved by combining the shielding ring and the shielding layer.
It achieves good shielding effect under different electromagnetic environments, has a simple structure, does not increase the packaging volume, is easy to industrialize, improves the performance and stability of the packaging structure, and solves the problems of complex process and poor shielding effect of electromagnetic shielding materials in the prior art.
Smart Images
Figure CN223957963U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to a fan-out wafer level package chip structure, in particular to a fan-out wafer level package chip structure with electromagnetic shielding function, and belongs to the technical field of semiconductor packaging. BACKGROUND
[0002] In the technical field of semiconductor packaging, with the increasing integration of semiconductor devices, their sensitivity to electromagnetic interference is also increasing. Therefore, the application of electromagnetic shielding technology in semiconductor packaging becomes more and more important.
[0003] Electromagnetic shielding is a technology that limits electromagnetic fields to a certain area by setting a shielding layer to prevent electromagnetic interference. In the field of microelectronic device manufacturing, fan-out wafer level packaging is an advanced packaging technology that can achieve smaller packaging size and higher packaging density.
[0004] In the existing technology, electromagnetic shielding materials are usually added around the semiconductor chip to achieve the effect of electromagnetic shielding. Then, the shielding material and the chip are packaged together to achieve the effect of electromagnetic shielding.
[0005] However, the existing electromagnetic shielding technology still has some problems in practical application.
[0006] Firstly, the existing electromagnetic shielding materials often need to be prepared through complex process, which not only increases the production cost, but also reduces the production efficiency.
[0007] Secondly, the shielding effect of the existing electromagnetic shielding materials at certain specific frequencies is not good, which may cause the semiconductor device to be affected by electromagnetic interference during operation, affecting its performance.
[0008] In addition, the application of existing electromagnetic shielding technology in fan-out wafer level packaging is not mature enough, and further research and exploration are needed. SUMMARY
[0009] In order to solve the problems of the prior art, the purpose of the present application is to provide a fan-out wafer level package chip structure with electromagnetic shielding function.
[0010] In order to achieve the above-mentioned purpose, the application adopts the following technical solution:
[0011] A fan-out wafer level package chip structure with electromagnetic shielding function, comprising a shielding ring surrounding the chip and a shielding layer packaged on the back of the chip.
[0012] The cross section of the shielding ring is rectangular.
[0013] Further, the end corners of the rectangle are rounded.
[0014] The shielding ring comprises a first ring layer, a second ring layer and a third ring layer stacked in sequence.
[0015] The material of the first ring layer comprises ferromagnetic metal and its alloy, iron-nickel alloy, cobalt-nickel alloy, iron-based or cobalt-based amorphous alloy, iron-based or cobalt-based nanocrystalline alloy, or gold, silver, copper, aluminum.
[0016] The material of the second ring layer comprises cobalt-nickel alloy.
[0017] The material of the third ring layer comprises copper.
[0018] Further, the shielding ring comprises a plurality of groups of the first ring layer, the second ring layer and the third ring layer.
[0019] The thickness of the shielding ring is 10-60 microns.
[0020] The material of the shielding layer comprises nickel-iron alloy.
[0021] The present application has the advantages of:
[0022] The fan-out wafer level package chip structure with electromagnetic shielding function of the present application adopts the shielding ring composed of multiple metal layers and the metal shielding layer adhered to the back of the chip, to realize the electromagnetic shielding function. The stacked metal layers and the metal shielding layer can be selected from different materials, so as to achieve the purpose of shielding effect in different electromagnetic environments, and the shielding effect is good.
[0023] The fan-out wafer level package chip structure with electromagnetic shielding function of the present application has a simple structure, and by using the method of embedding the shielding material into the packaging material, the packaging volume is not increased, which is beneficial to the integration and miniaturization of packaging. Compared with the method of using a large shielding frame to achieve shielding effect, the shielding assembly of the present application is small and simple in process, and is easy to realize industrialization. After the shielding layers are connected to each other through the adhesive layer and embedded in the packaging material, the performance and stability of the packaging structure are further improved, effectively solving the problem that the current electromagnetic shielding assembly cannot be well combined with wafer level packaging, especially solving the problem that the current packaging structure with electromagnetic shielding function has poor shielding effect in complex electromagnetic field environment, and having strong practicability and wide applicability. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figure 1 Structure diagram for adhering a semiconductor chip to a carrier wafer.
[0025] Figure 2 Structure diagram for adhering a first ring layer to a carrier wafer.
[0026] Figure 3This is a schematic diagram of the structure for bonding the second ring layer.
[0027] Figure 4 This is a schematic diagram of the structure of the adhesive third ring layer.
[0028] Figure 5 This is a schematic diagram of a structure for bonding multiple sets of ring layers.
[0029] Figure 6 This is a schematic diagram of the adhesive shielding layer.
[0030] Figure 7 This is a schematic diagram of the packaged chip, shielding ring, and shielding layer.
[0031] Figure 8 This is a schematic diagram of the structure for peeling a chip from a carrier wafer.
[0032] Figure 9 This is a schematic diagram of the structure for fabricating a redistribution layer and metal bumps on the active surface of a chip.
[0033] The meanings of the markings in the attached diagram are as follows: 1. Chip, 2. Carrier wafer, 3. First ring layer, 4. Second ring layer, 5. Third ring layer, 6. Shielding layer;
[0034] a. Adhesive layer. Detailed Implementation
[0035] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0036] A fan-out wafer-level packaged chip structure with electromagnetic shielding function is fabricated as follows:
[0037] S1, such as Figure 1 As shown, the semiconductor chip 1 is attached to the carrier wafer 2;
[0038] S2, such as Figure 2 As shown, in the ring semiconductor chip, the first ring layer 3 is attached to the carrier wafer.
[0039] The material of the first ring layer can be ferromagnetic metals and their alloys, iron-nickel alloys, cobalt-nickel alloys, iron-based or cobalt-based amorphous alloys, iron-based or cobalt-based nanocrystalline alloys, or gold, silver, copper, aluminum, etc.
[0040] Preferably, the first ring layer is a rounded rectangle that can surround the chip, and the material is preferably an iron-nickel alloy.
[0041] S3, such as Figure 3 As shown, a second ring layer is placed on the first ring layer, and the shielding ring 1 and the shielding ring 2 are bonded together by an adhesive layer; preferably, the material of the second ring layer 4 is a cobalt-nickel alloy.
[0042] S4, such as Figure 4A third ring layer is placed on the second ring layer, as shown. Preferably, the third ring layer is made of copper.
[0043] S5, as shown in Figure 5 S2-S4 are repeated to place several groups of first ring layers, second ring layers and third ring layers 5 until the total thickness is equivalent to the thickness of the chip, forming a shielding ring. The thickness of the shielding ring is preferably 10-60 microns.
[0044] S6, as shown in Figure 6 A shielding layer 6 is adhered above the chip. Preferably, the shielding layer 6 is made of nickel-iron alloy.
[0045] S7, as shown in Figure 7 The chip, the shielding ring and the shielding layer are packaged with a packaging material.
[0046] S8, as shown in Figure 8 The chip is peeled off from the carrier wafer.
[0047] S9, as shown in Figure 9 A redistribution layer and a metal bump are made on the active surface of the chip.
[0048] The basic principles, main features and advantages of the present application are shown and described above. Those skilled in the art should understand that the above examples do not limit the present application in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation fall within the protection scope of the present application.
Claims
1. A fan-out wafer level package chip structure having an electromagnetic shielding function, characterized by, The shielding ring comprises a shielding ring for ring chip package and a shielding layer for package on the back of the chip; The cross section of the shielding ring is rectangular. The shielding ring comprises a first ring layer, a second ring layer and a third ring layer which are stacked in sequence.
2. The packaged chip structure of claim 1, wherein, The end corners of the rectangle are rounded.
3. The packaged chip structure of claim 1, wherein, The shielding ring comprises a plurality of groups of the first ring layer, the second ring layer and the third ring layer.
4. The packaged chip structure of claim 1, wherein, The thickness of the shielding ring is 10-60 microns.
5. The packaged chip structure of claim 1, wherein, The material of the shielding layer is nickel-iron alloy.