Chip packaging body
By using a shielded ground wire to form a metal cage structure and flip-chip technology in chip packaging, combined with highly conductive materials and low-cost molding compounds, the problems of miniaturization, low cost and high-frequency performance that existing packaging technologies cannot meet are solved, achieving electromagnetic shielding and efficient heat dissipation.
Patent Information
- Application Number
- CN202520377822.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-05
- Publication Date
- 2026-02-27
- Estimated Expiration
- 2035-03-05
AI Technical Summary
Existing chip packaging technologies cannot meet the requirements for miniaturization, low cost, high-frequency performance, and electromagnetic shielding. In particular, metal-ceramic tube packaging is expensive and cavity resonance affects chip functionality. RDL wafer-level packaging is expensive and cannot provide shielding, while plastic packaging has poor thermal conductivity and is susceptible to electromagnetic interference.
A shielded ground wire is bonded around the chip to form a grid-like metal shielding wall, which together with the back metal layer of the chip and the metal layer of the packaging substrate forms a metal cage structure. Combined with flip-chip technology and interconnect structure, highly conductive materials and low-cost molding compound materials are used, and a heat sink is embedded to achieve efficient heat dissipation.
It achieves effective electromagnetic shielding, prevents electromagnetic signal leakage, meets miniaturization requirements, reduces packaging costs, improves signal integrity and heat dissipation efficiency, and adapts to the electrical performance requirements of high-frequency and high-power chips.
Smart Images
Figure CN223957964U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of chip manufacturing, in particular to a chip package. BACKGROUND
[0002] The existing chip package usually adopts metal ceramic tube shell package, wafer level package of RDL or plastic package, wherein the metal ceramic tube shell package cannot meet the demand of miniaturization, has high cost and is easy to produce cavity resonance to affect the function of the chip; the wafer level package of RDL has high packaging cost and cannot shield the chip itself, so the chip is easy to interfere with or be interfered by other chips; the plastic package has obvious influence on the performance of high-frequency chips, poor heat conduction and poor isolation effect, and thus is easy to be interfered by electromagnetic interference. SUMMARY
[0003] The purpose of the embodiment of the present application is to provide a chip package to improve the electromagnetic shielding performance of the chip package.
[0004] The chip package provided by the present application comprises a chip, a packaging substrate and a plurality of shielding ground wires; the chip comprises a signal pad and a back metal layer opposite to the signal pad, and the signal pad faces the packaging substrate to complete flip-chip; one end of each of the shielding ground wires is connected to different positions of the back metal layer of the chip, and the other end is connected to different positions of the metal layer of the packaging substrate, so that the shielding ground wires are bonded around the chip to form a grid-shaped metal shielding wall, and the metal shielding wall, the back metal layer of the chip and the metal layer of the packaging substrate form a metal cage structure.
[0005] In the above scheme, the shielding ground wires are bonded around the chip to form a grid-shaped metal shielding wall, and the metal shielding wall, the back metal layer of the chip and the metal layer of the packaging substrate jointly form a closed metal cage structure, so that the internal circuit structure of the chip is surrounded by the metal cage, thereby achieving the shielding effect, which can effectively shield external electromagnetic interference and prevent the leakage of electromagnetic signals inside the chip, and improve the isolation effect.
[0006] As an optional way, the plurality of shielding ground wires are arranged in parallel or staggered.
[0007] In the above scheme, the parallel arrangement of the shielding ground wires can form a uniform electromagnetic shielding layer to ensure the consistency of the electromagnetic shielding effect around the chip, more effectively block external electromagnetic interference and improve the anti-interference ability of the chip, and the staggered arrangement of the shielding ground wires can increase the intersection points between the shielding ground wires to improve the shielding density and further enhance the electromagnetic shielding effect.
[0008] As an optional way, an interconnection structure is further included, and the signal pad and the packaging substrate are bonded through the interconnection structure.
[0009] In the above scheme, instead of wafer level packaging with RDL, flip technology is realized by using interconnection structure, which can significantly reduce the packaging size, and the flip technology directly faces the signal pads of the chip to the packaging substrate, reducing the additional space required by wire bonding in traditional packaging, meeting the market demand for small chip packaging.
[0010] As an optional way, the interconnection structure includes: bump, metal probe.
[0011] In the above scheme, the bump and metal probe are made of high-conductivity metal material, which can provide low-resistance electrical connection, reduce loss and delay in signal transmission process, and thus improve signal integrity.
[0012] As an optional way, the interconnection structure is realized by ball planting or ultrasonic bonding process.
[0013] In the above scheme, the ball planting or ultrasonic bonding process can provide low-resistance electrical connection, reduce loss and delay in signal transmission process, and thus improve signal integrity.
[0014] As an optional way, the back metal layer of the chip is embedded with a heat sink, and the heat sink is used for heat dissipation.
[0015] Since the existing technology embeds the heat sink on the packaging substrate, which occupies the wiring space, in order to meet the wiring requirement, the size of the substrate will increase accordingly. In the above scheme, by embedding the heat sink on the back metal layer of the chip, the wiring space is larger, and the size of the substrate can be reduced, so that efficient heat dissipation can be realized without increasing the packaging size.
[0016] As an optional way, a heat dissipation material layer is arranged between the back metal layer and the heat sink, and the heat dissipation material layer is used for heat conduction and bonding and fixing the heat sink and the chip.
[0017] In the above scheme, the heat dissipation material layer can effectively conduct the heat generated by the chip, ensure that the heat is quickly transmitted from the back metal layer of the chip to the heat sink, and significantly reduce the working temperature of the chip.
[0018] As an optional way, the material of the heat dissipation material layer is silicone grease or heat-conducting glue.
[0019] In the above scheme, silicone grease and heat-conducting glue both have high thermal conductivity, which can quickly conduct the heat generated by the chip from the back metal layer to the heat sink.
[0020] As an optional way, it further includes: a plastic encapsulation material wrapping the chip.
[0021] In the above scheme, the plastic package material is generally low in cost, and can significantly reduce the packaging cost compared with the metal ceramic package or other high-end packaging materials.
[0022] As an optional way, the diameter of the shielding ground wire is in the range of 10-50 microns, and the spacing between the shielding ground wires is in the range of 0.5 times the diameter-5 times the diameter.
[0023] In the above scheme, by reasonably setting the diameter and spacing of the shielding ground wire, the electromagnetic shielding effect can be enhanced, and the external electromagnetic interference can be more effectively blocked into the package interior, while reducing the leakage of the internal signals of the chip.
[0024] Other features and advantages of the present application will be described in the following description, and some will become apparent from the description, or will be understood through implementation of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS
[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.
[0026] Figure 1 A structure schematic diagram of a metal ceramic tube shell package provided for the comparative example 1 is shown in the following figure:
[0027] Figure 2 A structure schematic diagram of a wafer level package of RDL provided for the comparative example 2 is shown in the following figure:
[0028] Figure 3 A structure schematic diagram of a plastic package provided for the comparative example 3 is shown in the following figure:
[0029] Figure 4 A front view of a chip package provided for the embodiments of the present application is shown in the following figure:
[0030] Figure 5 A top view of a chip package provided for the embodiments of the present application is shown in the following figure. DETAILED DESCRIPTION
[0031] The embodiments of the technical solutions of the present application will be described in detail below with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present application, and therefore only serve as examples, and cannot limit the protection scope of the present application.
[0032] It should be noted that all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "include" and "have" and any variations thereof in the specification and claims of the present application and the above description of drawings are intended to cover non-exclusive inclusion.
[0033] In the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly and specifically limited.
[0034] In the description of the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.
[0035] In order to facilitate understanding, the professional technology involved in the technical solutions provided by the embodiments of the present application is introduced.
[0036] Chip packaging often uses metal ceramic tube shell packaging, RDL wafer level packaging, and plastic packaging.
[0037] Among them, referring to Figure 1 , Figure 1 A structure diagram of a metal ceramic tube shell packaging body provided for the comparative example 1, the packaging body 100 at least includes a chip 101, a metal ceramic tube shell 102, a gold wire bonding line 103 for signal interconnection between the chip 101 and the substrate, a heat sink 104 embedded in the bottom of the metal ceramic tube shell 102, a signal pad 1001 on the upper part of the chip 101, and a back metal layer 1002 on the bottom of the chip 101. Although the metal ceramic tube shell packaging has higher reliability, in order to ensure performance and heat dissipation, the heat sink needs to be embedded on the packaging substrate, so the size will increase a lot, which cannot meet the demand of miniaturization. In addition, the cost of metal ceramic and heat sink is relatively high. For a chip with higher frequency, the metal ceramic tube shell packaging is easy to produce cavity resonance inside the packaging body, which leads to the decline of chip function or even cannot work normally. In order to suppress the cavity resonance, other measures need to be introduced, which further increases the packaging size and the corresponding cost of packaging.
[0038] Referring to Figure 2 , Figure 2A structure diagram of a wafer level package of an RDL provided for the comparative example 2, the package 200 includes but is not limited to a pre-packaging chip 201 and a metal layer 2001 on the back of the chip (part of the chip does not have 2001), a re-distribution layer 202 and a bump 203 on the outermost side of the re-distribution layer. For this wafer level package of RDL, although the demand of miniaturization is met, due to the process, the packaging cost is relatively high, in addition, the RDL technology has high loss at high frequency, the performance of the chip is greatly reduced, and some chips with high performance requirements cannot meet the requirements, and even worse, the chip with RDL cannot realize shielding of the chip itself, and the chip is easily disturbed by other chips or disturbs other chips, so that the chip cannot work normally.
[0039] Referring to Figure 3 , Figure 3 A structure diagram of a plastic package provided for the comparative example 3, the package 300 at least includes a chip 301, a packaging substrate 304, a signal interconnection line 302 between the chip 301 and the packaging substrate 304, and a plastic package 303. For this low-cost plastic package, the plastic package has a significant impact on the performance of high-frequency chips, in addition, the heat conduction ability of the plastic package is poor, and it is often difficult to meet the electrical performance and heat dissipation requirements of high-frequency and high-power chips, and in addition, it is difficult to achieve high isolation in the plastic package for a high-frequency multi-chip module, and it is often difficult to meet the electromagnetic interference index requirements.
[0040] Referring to Figure 4 , Figure 4 A front view of a chip package provided for the embodiment of the application, the chip package includes: a chip 401, a packaging substrate 402, and a plurality of shielding ground wires 403; the chip 401 includes a signal pad 4011 and a back metal layer 4012 opposite to the signal pad 4011, the signal pad 4011 faces the packaging substrate 402 to complete flip-chip; one end of each shielding ground wire 403 is connected to different positions of the back metal layer 4012 of the chip 401, and the other end is connected to different positions of the metal layer of the packaging substrate 402, so that the shielding ground wire 403 is bonded around the chip 401 to form a grid-shaped metal shielding wall, and the metal shielding wall, the back metal layer 4012 of the chip 401 and the metal layer of the packaging substrate 402 form a metal cage structure.
[0041] Chip mounting and flip-chip mounting are two common chip packaging technologies, the chip mounting is to install the chip with the front face upward on the packaging substrate, and use fine metal wires (usually gold wires or aluminum wires) to connect the pads of the chip with the pins on the substrate, while the flip-chip mounting is to install the chip with the front face downward on the packaging substrate, and directly connect the pads of the chip with the pins on the substrate.
[0042] Referring to Figure 5 , Figure 5A top view of a chip package provided by an embodiment of the present application is shown in Figure 5 As can be seen in the figure, one end of each shielding ground wire 403 is connected to different positions of the back metal layer 4012 of the chip 401, and the other end is connected to different positions of the metal layer of the packaging substrate 402, so that the shielding ground wires 403 are bonded around the chip 401 to form a grid-shaped metal shielding wall.
[0043] The metal cage structure can be equivalent to a closed metal cavity by using the eddy current effect. The thicker the shielding ground wires 403 are and the smaller the spacing between the shielding ground wires 403 is, the better the shielding effect of the metal cage is. The spacing between the shielding ground wires 403 can be matched and evaluated according to the frequency of the chip 401 and the bonding process capability, which is not specifically limited in the present application.
[0044] In the above scheme, the shielding ground wires 403 are bonded around the chip 401 to form a grid-shaped metal shielding wall, which together with the back metal layer 4012 of the chip 401 and the metal layer of the packaging substrate 402 forms a closed metal cage structure. The internal circuit structure of the chip 401 is surrounded by the metal cage, thereby achieving a shielding effect, which can effectively shield external electromagnetic interference and prevent electromagnetic signal leakage inside the chip 401, thereby improving the isolation effect.
[0045] In some embodiments, the plurality of shielding ground wires 403 are arranged in parallel or staggered.
[0046] In Figure 5 the plurality of shielding ground wires 403 are arranged in parallel, and in other embodiments, the plurality of shielding ground wires 403 can also be arranged in a staggered manner. The staggered arrangement means that the shielding ground wires 403 are arranged in a non-parallel manner on the packaging substrate 402 to form intersection points. The shielding ground wires are arranged at a certain angle to form a regular grid-shaped structure. The intersection angle can be 90°, 45°, 60°, etc.
[0047] In the above scheme, the parallel arrangement of the shielding ground wires 403 can form a uniform electromagnetic shielding layer, ensuring that the electromagnetic shielding effect around the chip 401 is consistent, more effectively blocking external electromagnetic interference, and improving the anti-interference capability of the chip 401. The staggered arrangement of the shielding ground wires 403 can increase the intersection points between the shielding ground wires 403, improve the shielding density, and further enhance the electromagnetic shielding effect.
[0048] In some embodiments, the interconnection structure 404 is further included, and the signal pads 4011 and the packaging substrate 402 are bonded through the interconnection structure 404.
[0049] The flip chip has the advantages of low cost, suitable for various packaging forms, but has obvious and more disadvantages, such as the lead bonding needs additional space to arrange the lead, resulting in large packaging size, and the long lead increases the inductance and resistance of signal transmission, which may cause signal delay and electromagnetic interference, not suitable for high frequency application, and the heat of the flip chip is mainly conducted through the back of the chip, the heat dissipation path is long, and the heat dissipation efficiency is low. Although the flip chip overcomes the various performance disadvantages of the vertical chip, it has good high frequency performance and heat dissipation performance, but the wafer level packaging technology involving RDL is high in cost and complex in process.
[0050] The embodiment does not use the wafer level packaging technology of RDL, but uses the interconnection structure 404 to bond between the signal pad 4011 and the packaging substrate 402 to realize the flip chip.
[0051] In the above scheme, the wafer level packaging of RDL is not used, but the interconnection structure 404 is used to realize the flip chip technology, which can significantly reduce the packaging size, and the flip chip technology directly faces the signal pad 4011 of the chip 401 to the packaging substrate 402, reducing the additional space required by the lead bonding in the traditional packaging, meeting the market demand for small chip 401 packaging.
[0052] In some embodiments, the back metal layer 4012 of the chip 401 is embedded with a heat sink 405, and the heat sink 405 is used for heat dissipation.
[0053] The heat sink 405 is a key component for improving the heat dissipation performance of the chip, and its main function is to quickly conduct and dissipate the heat generated by the chip, thereby reducing the working temperature of the chip and ensuring the stability and reliability of the chip during high power operation.
[0054] Since the existing technology embeds the heat sink on the packaging substrate 402, which occupies the wiring space, in order to meet the wiring requirement, the size of the substrate will increase accordingly, in the above scheme, by embedding the heat sink 405 on the back metal layer 4012 of the chip 401, the wiring space is larger, and the size of the substrate can be reduced, so that efficient heat dissipation can be realized without increasing the packaging size.
[0055] In some embodiments, a heat dissipation material layer 406 is arranged between the back metal layer 4012 and the heat sink 405, and the heat dissipation material layer 406 is used for heat conduction and adhesion and fixation of the heat sink 405 and the chip 401.
[0056] For chips with high power consumption and high heat dissipation demand, such as radio frequency power amplifier chips, in order to ensure good heat dissipation capacity, a heat dissipation material layer 406 is arranged between the back metal layer 4012 and the heat sink 405, which can on the one hand more conducive to heat conduction, and on the other hand can play the role of adhesion and fixation of the heat sink 405 and the chip 401.
[0057] The heat dissipation material layer 406 is evenly laid between the back metal layer 4012 and the heat sink 405, which can be laid on the entire back metal layer 4012 or locally laid, and those skilled in the art can adjust it by themselves.
[0058] In addition, in the chip package of the embodiment of the present application, the heat dissipation channel is on the upper side of the chip package, and the signal channel is at the bottom of the chip package, which realizes the isolation of the signal channel and the heat dissipation channel well and ensures that the chip 401 can work normally and stably.
[0059] In the above scheme, the heat dissipation material layer 406 can effectively conduct the heat generated by the chip 401, ensure that the heat is quickly transferred from the back metal layer 4012 of the chip 401 to the heat sink 405, and can significantly reduce the working temperature of the chip 401.
[0060] In some embodiments, the material of the heat dissipation material layer 406 is silicone grease or heat-conducting glue.
[0061] The heat dissipation material layer 406 can be selected from heat dissipation silicone grease or heat-conducting glue with high heat conductivity.
[0062] In the above scheme, the silicone grease and the heat-conducting glue both have high thermal conductivity, which can quickly conduct the heat generated by the chip 401 from the back metal layer 4012 to the heat sink 405.
[0063] In some embodiments, the chip 401 is further wrapped by a plastic package material 407.
[0064] The chip package adopts plastic packaging, and due to the shielding effect of the metal cage, the influence of electromagnetic interference can be reduced. If the heat sink is further arranged, the problem of poor heat dissipation performance of the plastic package is solved, and the balance between the various demands of low cost, miniaturization and high performance of the chip package is realized.
[0065] In addition, if the chip 401 has low power consumption or no high heat dissipation demand, the heat sink 405 and the heat dissipation material layer 406 can not be needed, but are replaced by the plastic package material 407.
[0066] In the above scheme, the plastic package material 407 usually has low cost, which can significantly reduce the packaging cost compared with the metal ceramic packaging or other high-end packaging materials.
[0067] In some embodiments, the interconnection structure 404 includes bump and metal probe.
[0068] The interconnection structure 404 is used to realize the electrical connection between the chip 401 and the package substrate 402. Therefore, the interconnection structure can be a bump or a metal probe. The bump is a small metal bump that directly connects the signal pad 4011 of the chip 401 to the pin on the package substrate 402 to realize the electrical and mechanical connection. The metal probe is an elongated metal needle used in chip testing and packaging, which can temporarily or permanently connect the signal pad 4011 of the chip 401 to the test equipment or the package substrate 402.
[0069] In the above scheme, the bump and the metal probe are made of a metal material with high electrical conductivity, which can provide a low-resistance electrical connection, reduce the loss and delay in the signal transmission process, and thus improve the signal integrity.
[0070] In some embodiments, the diameter of the shielding ground wire 403 is in the range of 10-50 microns, and the spacing between the shielding ground wires 403 is in the range of 0.5 times the diameter to 5 times the diameter.
[0071] The diameter of the shielding ground wire 403 is in the range of 10-50 microns, for example, 10 microns, 20 microns, 25 microns, 50 microns, etc. When the shielding ground wires 403 are arranged in parallel, the spacing between the shielding ground wires 403 is in the range of 0.5 times the diameter to 5 times the diameter, for example, 0.5 times the diameter of the shielding ground wire, 1 times the diameter of the shielding ground wire, or 5 times the diameter of the shielding ground wire. When the shielding ground wires 403 are arranged in staggered manner, the spacing refers to the distance between two adjacent intersection points.
[0072] In the above scheme, the diameter and spacing of the shielding ground wire 403 are reasonably set to enhance the electromagnetic shielding effect, which can more effectively block external electromagnetic interference from entering the inside of the package, while reducing the leakage of the signals inside the chip 401.
[0073] In some embodiments, the interconnection structure 404 is implemented by a ball planting or ultrasonic bonding process.
[0074] In the above scheme, the ball planting or ultrasonic bonding process can provide a low-resistance electrical connection, reduce the loss and delay in the signal transmission process, and thus improve the signal integrity.
[0075] In some embodiments, the material of the heat sink 405 is a thermally conductive material.
[0076] The heat sink 405 is made of a high-thermal-conductivity material, which can be a metal material such as copper, aluminum, etc., or a non-metal material such as graphite, diamond, silicon wafer, etc.
[0077] In the above scheme, the thermally conductive material has a high thermal conductivity coefficient, which can quickly conduct the heat generated by the chip 401 to the outside of the package.
[0078] The above merely provides an example of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims
1. A chip package, characterized by, The application relates to a chip, a packaging substrate and a plurality of shielding ground wires. The chip comprises signal pads and a back metal layer opposite to the signal pads, the signal pads face the packaging substrate to complete flip-chip; One end of each of the shielding ground wires is connected to different positions of the back metal layer of the chip, and the other end is connected to different positions of a metal layer of the packaging substrate, so that the shielding ground wires are bonded around the chip to form a metal shielding wall in a fence shape, and the metal shielding wall, the back metal layer of the chip and the metal layer of the packaging substrate form a metal cage structure. The plurality of shielding ground wires are arranged in parallel or staggered.
2. The chip package of claim 1, wherein, An interconnection structure is further arranged, and the signal pads and the packaging substrate are bonded through the interconnection structure.
3. The chip package of claim 1, wherein, The interconnection structure comprises bumps and metal probes.
4. The chip package of claim 3, wherein, The interconnection structure is realized by a ball mounting or ultrasonic bonding process.
5. The chip package of claim 3, wherein, A heat sink is embedded in the back metal layer of the chip, and the heat sink is used for heat dissipation.
6. The chip package of claim 1, wherein, A heat dissipation material layer is arranged between the back metal layer and the heat sink, the heat dissipation material layer is used for heat conduction and adhesion and fixation of the heat sink and the chip.
7. The chip package of claim 6, wherein, The material of the heat dissipation material layer is silicone grease or heat-conducting glue.
8. The chip package of claim 7, wherein, The application further relates to:
9. The chip package of any one of claims 1-8, wherein, A plastic encapsulation material wrapping the chip. The diameter of the shielding ground wire is in the range of 10-50 microns, and the spacing between the shielding ground wires is in the range of 0.5 times the diameter-5 times the diameter.
10. The chip package of claim 1, wherein,