Output control circuit of direct-current power supply
By setting delay switching circuits at the positive and negative output terminals of the DC power supply, and using an RC circuit composed of an NMOS transistor, capacitor, and resistor, the current surge problem when the relay is energized is solved, achieving higher testing accuracy and circuit reliability, while reducing circuit cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-05
- Publication Date
- 2026-03-03
AI Technical Summary
In the output switching circuit of a traditional DC power supply, the current surge when the relay is energized affects the accuracy of battery testing and the lifespan of the power circuit capacitors, and the pre-charging circuit and relay circuit are costly.
The circuit employs positive and negative delay switching circuits, and uses an RC circuit composed of NMOS transistors, capacitors, and resistors to control the current switching on and off, reducing inrush current. The circuit is also designed with an auxiliary DC power supply and a common ground to ensure safety and reliability.
It reduces current surges, improves battery testing accuracy, extends the lifespan of batteries and capacitors, prevents short circuits, and reduces circuit costs.
Smart Images
Figure CN223967800U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to DC power supplies, specifically to an output control circuit for a DC power supply used in lithium battery testing. Background Technology
[0002] As is well known, in the lithium battery testing industry, the main application of output switching circuits is as a switch between the power circuit and the battery load, used to prevent arcing caused by direct connection between the power circuit capacitor and the battery, or short circuit caused by connection to the battery in the event of power device failure.
[0003] Traditional output switches (on / off) are usually controlled by relays. In actual operation, because there is no buffer when the relay is energized, it causes current surges between the battery and the DC power supply, affecting the battery testing accuracy and the lifespan of the power circuit capacitors. In addition, even if a buffer circuit is added, the time from pre-charging to relay energization is still long due to the characteristics of the relay buffer circuit itself. Moreover, the cost of adding a main relay circuit to the pre-charging circuit is high. Utility Model Content
[0004] The technical problem to be solved by this utility model is to provide an output control circuit for a DC power supply with low inrush current, which can ensure the testing accuracy of the battery under test and extend the service life of the power circuit capacitor.
[0005] To solve the above-mentioned technical problems, the technical solution adopted by this utility model is as follows: an output control circuit for a DC power supply, comprising: a positive output terminal and a negative output terminal of the DC power supply, a positive delay switching circuit, a negative delay switching circuit, a positive and negative switching trigger circuit whose switching control output terminal is connected to the trigger terminals of the positive and negative delay switching circuits, an auxiliary DC power supply for supplying power to the positive and negative delay switching trigger circuits, and a battery under test as a load. A corresponding terminal of the positive delay switching circuit is connected to the positive output terminal of the DC power supply, and the other terminal of the positive delay switching circuit is connected to the positive terminal of the battery under test. A corresponding terminal of the negative delay switching circuit is connected to the negative output terminal of the DC power supply, and the other terminal of the negative delay switching circuit is connected to the negative terminal of the battery under test. The voltage of the auxiliary DC power supply is greater than the voltage of the battery under test, and the voltage of the auxiliary DC power supply is greater than the voltage of the DC power supply. Furthermore, the auxiliary DC power supply and the DC power supply share a common ground.
[0006] As a preferred embodiment, in the output control circuit of the DC power supply, the specific structure of the positive delay switching circuit includes: two first NMOS transistors and a second NMOS transistor connected in series; a first capacitor, a first resistor, and a third resistor cooperating with the first NMOS transistors; a second capacitor, a second resistor, and a fourth resistor cooperating with the second NMOS transistors; the source of the first NMOS transistor, a corresponding terminal of the first capacitor, and one end of the third resistor are connected to the positive output terminal of the DC power supply; the other end of the first capacitor and one end of the first resistor are connected to the gate of the first NMOS transistor; the source of the second NMOS transistor, a corresponding terminal of the second capacitor, and one end of the fourth resistor are connected to the positive terminal of the battery under test; the other end of the second capacitor and one end of the second resistor are connected to the gate of the first NMOS transistor. The gates of two NMOS transistors are connected, and the drain of the first NMOS transistor is connected to the drain of the second NMOS transistor. The other ends of the first resistor, the second resistor, the third resistor, and the fourth resistor are connected as the trigger terminals of the positive delay on / off circuit. The negative delay on / off circuit includes a third NMOS transistor, a third capacitor, a sixth resistor, and a seventh resistor. The source of the third NMOS transistor, the corresponding terminal of the third capacitor, and one end of the sixth resistor are connected to the negative output terminal of the DC power supply. The other end of the third capacitor and one end of the seventh resistor are connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor is connected to the negative terminal of the battery under test. The other ends of the sixth resistor and the seventh resistor are connected as the trigger terminals of the negative delay on / off circuit.
[0007] As a preferred embodiment, in the output control circuit of the DC power supply, the time constant of the RC circuit in the negative delay switching circuit is less than the time constant of the two RC circuits in the positive delay switching circuit.
[0008] As a preferred embodiment, in the output control circuit of the DC power supply, the time constants of the two RC circuits in the positive delay switching circuit are equivalent.
[0009] As a preferred embodiment, in the output control circuit of the DC power supply, the resistance value of the third resistor is greater than the resistance value of the first resistor, the resistance value of the fourth resistor is greater than the resistance value of the second resistor, and the resistance value of the sixth resistor is greater than the resistance value of the seventh resistor.
[0010] As a preferred embodiment, in the output control circuit of the DC power supply, the positive and negative polarity switching trigger circuit includes: a first P-type transistor, a second N-type transistor, a fifth resistor, an eighth resistor, and a ninth resistor. One end of the ninth resistor serves as a trigger terminal, and the other end of the ninth resistor is connected to the base of the second N-type transistor. The emitter of the second N-type transistor is grounded. The collector of the second N-type transistor is connected to one end of the fifth resistor and one end of the eighth resistor. The other end of the fifth resistor and the emitter of the first P-type transistor are connected to the positive terminal of the auxiliary DC power supply. The other end of the eighth resistor is connected to the base of the first P-type transistor. The collector of the first P-type transistor serves as the on / off control output terminal of the positive and negative polarity switching trigger circuit.
[0011] As a preferred embodiment, in the output control circuit of the DC power supply, a tenth resistor is provided between the positive output terminal and the negative output terminal of the DC power supply.
[0012] As a preferred embodiment, in the output control circuit of the DC power supply, the DC power supply is a BUCK-BOOST power supply.
[0013] As a preferred embodiment, in the output control circuit of the DC power supply, a freewheeling diode is provided between the source and drain of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor.
[0014] As a preferred embodiment, in the output control circuit of the DC power supply, a freewheeling diode is built into the source and drain of each of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor.
[0015] The beneficial effects of this utility model are:
[0016] 1. This utility model sets up a positive delay on / off circuit and a negative delay on / off circuit at the positive and negative output terminals of the DC power supply, respectively, so that the amplification state is maintained for a certain period of time during the turn-on process, thereby reducing current spikes and reducing the impact on the DC power supply and battery at the moment of turn-on, thus ensuring the test accuracy of the battery and extending the service life of the battery, DC power supply and output capacitor and other related components; and by setting up a positive and negative on / off trigger circuit that simultaneously triggers the positive and negative delay on / off circuits, the circuit structure is simpler and more reliable.
[0017] 2. This utility model has a negative delay switching circuit at the negative output terminal of the DC power supply, which can prevent short circuits caused by human error in wiring when multiple batteries under test with the same power circuit are using the same bus, thus providing better battery terminal wiring protection in the case of shared bus usage.
[0018] 3. Due to the inherent characteristics of the circuit itself, if the voltage of the battery under test is mistakenly connected to a voltage higher than that of the auxiliary DC power supply, the positive and negative terminal switching trigger circuit will not be turned on, thus ensuring the safety of the DC battery and the battery under test.
[0019] 4. In this utility model, since the time constant of the RC circuit in the negative delay switching circuit is less than the time constant of the two RC circuits in the positive delay switching circuit, it ensures that the negative terminal of the DC power supply and the battery under test are connected first, thereby preventing short circuits caused by incorrect wiring of the battery under test when multiple outputs share a common ground.
[0020] 5. This utility model ensures that the first and second NMOS transistors will not be turned on when the third NMOS transistor is not turned on by connecting the drain of the third NMOS transistor to the battery under test and sharing a common ground with the source and GND, thereby avoiding the generation of inrush current.
[0021] 6. This utility model effectively prevents static virtual voltage of the DC power supply by setting a tenth resistor between the positive and negative output terminals of the DC power supply, and provides a stable level for the positive and negative delay switching circuit. Attached Figure Description
[0022] Figure 1 This is the output control circuit diagram of the DC power supply described in this utility model. Detailed Implementation
[0023] The following describes in detail, with reference to the accompanying drawings, the specific implementation scheme of the output control circuit of the DC power supply of this utility model, taking the BUCK-BOOST power supply as an example.
[0024] like Figure 1As shown, the output control circuit of the DC power supply of this utility model includes: a positive output terminal VDD and a negative output terminal VSS of a BUCK-BOOST power supply, a positive delay on / off circuit, a negative delay on / off circuit, a positive and negative on / off trigger circuit whose on / off control output terminal is connected to the trigger terminals of the positive and negative delay on / off circuits, an auxiliary DC power supply (which is conventional technology in this field and will not be described in detail here) that supplies power to the positive and negative on / off trigger circuits, and a battery under test B1 as a load. The DC power supply and the BUCK-BOOST power supply share a common ground. The voltage of the auxiliary DC power supply is greater than the voltage of the battery under test, B1, and also greater than the voltage of the BUCK-BOOST power supply. The positive delay switching circuit includes: two NMOS transistors connected in series, a first NMOS transistor M1 and a second NMOS transistor M2, a first capacitor C1, a first resistor R1 and a third resistor R3 associated with the first NMOS transistor M1, a second capacitor C2, a second resistor R2 and a fourth resistor R4 associated with the second NMOS transistor M2, and the source of the first NMOS transistor M1 and the corresponding terminal of the first capacitor C1. Figure 1 (left end of the middle), one end of the third resistor R3 ( Figure 1 The upper end of the capacitor C1 is connected to the positive output terminal VDD of the BUCK-BOOST power supply, and the other end of the first capacitor C1 ( Figure 1 The right end of the first resistor R1 (one end of the first resistor R1) Figure 1 The left end of the capacitor is connected to the gate of the first NMOS transistor M1, and the source of the second NMOS transistor M2 and the corresponding terminal of the second capacitor C2 are connected to the gate of the first NMOS transistor M1. Figure 1 The right end of the fourth resistor R4 (one end of the fourth resistor R4) Figure 1 The upper end of the capacitor C2 is connected to the positive terminal of the battery B1 under test, and the other end of the second capacitor C2 is connected to the positive terminal of the battery B1 under test. Figure 1 (left end of the middle), one end of the second resistor R2 ( Figure 1 The right end of the first resistor R1 is connected to the gate of the second NMOS transistor M2, and the drain of the first NMOS transistor M1 is connected to the drain of the second NMOS transistor M2. The other end of the first resistor R1 is connected to the gate of the second NMOS transistor M2. Figure 1 The right end of the first resistor), the other end of the second resistor R2 ( Figure 1 (left end of the middle), the other end of the third resistor R3 ( Figure 1 The lower end of the resistor R4, and the other end of the fourth resistor R4. Figure 1 The lower end of the circuit is connected to serve as the trigger terminal of the positive delay switching circuit; the negative delay switching circuit includes: a third NMOS transistor M3, a third capacitor C3, a sixth resistor R6, and a seventh resistor R7, with the source of the third NMOS transistor M3 and the corresponding terminals of the third capacitor C3 connected to each other. Figure 1 (left end of the middle), one end of the sixth resistor R6 ( Figure 1The upper end of the capacitor C3 is connected to the negative output terminal VSS of the BUCK-BOOST power supply, and the other end of the third capacitor C3 ( Figure 1 The right end of the middle), one end of the seventh resistor R7 ( Figure 1 The upper end of the resistor R6 is connected to the gate of the third NMOS transistor M3, and the drain of the third NMOS transistor M3 is connected to the negative terminal of the battery B1 under test. The other end of the sixth resistor R6 ( Figure 1 The lower end of the middle resistor and the other end of the seventh resistor R7 ( Figure 1 The lower end of the circuit is connected to serve as the trigger terminal of the negative delay on / off circuit; the positive and negative on / off trigger circuit includes: a first P-type transistor Q1, a second N-type transistor Q2, a fifth resistor R5, an eighth resistor R8, and a ninth resistor R9, one end of the ninth resistor R9 ( Figure 1 The left end of the resistor R9 is used as the trigger end, and the other end of the ninth resistor R9 is used as the trigger end. Figure 1 The right end of the resistor R5 is connected to the base of the second N-type transistor Q2, the emitter of the second N-type transistor Q2 is grounded, and the collector of the second N-type transistor Q2 is connected to one end of the fifth resistor R5. Figure 1 The lower end of the middle) and one end of the eighth resistor R8 ( Figure 1 The left end of the fifth resistor R5 is connected to the other end of the fifth resistor R5. Figure 1 The upper end of the resistor R8 and the emitter of the first P-type transistor Q1 are connected to the positive terminal of the auxiliary DC power supply (12V). The other end of the eighth resistor R8 ( Figure 1 The right end of the circuit is connected to the base of the first P-type transistor Q1. The collector of the first P-type transistor Q1 serves as the on / off control output of the positive and negative on / off trigger circuits, and is connected to the trigger terminals of the positive and negative delay on / off circuits. In this embodiment, the time constant of the RC circuit in the negative delay on / off circuit is less than the time constant of the two RC circuits in the positive delay on / off circuit, to ensure that the third NMOS transistor M3 turns on first, otherwise an inrush current will be generated; the time constants of the two RC circuits in the positive delay on / off circuit are equal. The resistance value of the third resistor R3 is usually 10 times the resistance value of the first resistor R1, the resistance value of the fourth resistor R4 is usually 10 times the resistance value of the second resistor R2, and the resistance value of the sixth resistor R6 is usually 10 times the resistance value of the seventh resistor R7. A tenth resistor R10 is provided between the positive and negative output terminals of the BUCK-BOOST power supply; each of the first NMOS transistor M1, the second NMOS transistor M2, and the third NMOS transistor M3 has a freewheeling diode built into its source and drain; in fact, the freewheeling diode is a parasitic diode of the MOS transistor itself. 。
[0025] In practical applications, multiple output control circuits described above can be connected in parallel to the positive output terminal VDD and the negative output terminal VSS of the BUCK-BOOST power supply by sharing a common bus.
[0026] The working process of this utility model is as follows: After the ON (on) signal is given to the ninth resistor R9, the first P-type transistor Q1 is turned on, and the collector of the first P-type transistor Q1 outputs a high level, which charges the first capacitor C1 through the first resistor R1, the second capacitor C2 through the second resistor R2, and the third capacitor C3 through the seventh resistor R7. Since the time constants of R7 and C3 are small, the third NMOS transistor M3 turns on before the first NMOS transistor M1 and the second NMOS transistor M2. After the third NMOS transistor M3 turns on, the negative terminal of the battery under test B1 is connected to GND. As the first capacitor C1 and the second capacitor C2 continue to be charged, the first NMOS transistor M1 and the second NMOS transistor M2 enter the on state, so that the positive terminal of the battery under test B1 is connected to the positive output terminal VDD of the BUCK-BOOST power supply. When the OFF (off) signal is given to the ninth resistor R9, the first P-type transistor Q1 is turned off, and the first NMOS transistor M1, the second NMOS transistor M2 and the third NMOS transistor M3 are turned off.
[0027] In summary, the above description is merely a preferred embodiment of the present utility model and is not intended to limit the scope of the present utility model. All equivalent variations and modifications made to the shape, structure, features and spirit described in the claims of the present utility model should be included within the scope of the claims of the present utility model.
Claims
1. An output control circuit for a direct current power supply, comprising: The positive output terminal of the direct current power supply and the negative output terminal of the direct current power supply, characterized in that the output control circuit further comprises: a positive delay on-off circuit, a negative delay on-off circuit, a positive and negative on-off trigger circuit with its on-off control output terminals connected to the trigger terminals of the positive delay on-off circuit and the negative delay on-off circuit, an auxiliary direct current power supply for powering the positive and negative on-off trigger circuit and a battery to be tested as a load, the corresponding terminal of the positive delay on-off circuit is connected to the positive output terminal of the direct current power supply, the other terminal of the positive delay on-off circuit is connected to the positive terminal of the battery to be tested, the corresponding terminal of the negative delay on-off circuit is connected to the negative output terminal of the direct current power supply, and the other terminal of the negative delay on-off circuit is connected to the negative terminal of the battery to be tested; the voltage of the auxiliary direct current power supply is greater than the voltage of the battery to be tested, the voltage of the auxiliary direct current power supply is greater than the voltage of the direct current power supply, and the auxiliary direct current power supply is grounded with the direct current power supply.
2. The output control circuit of a direct current power supply according to claim 1, characterized by: The specific structure of the positive delay on-off circuit comprises: two first and second NMOS tubes connected in series, a first capacitor matched with the first NMOS tube, a first resistor and a third resistor, a second capacitor matched with the second NMOS tube, a second resistor and a fourth resistor, the source of the first NMOS tube, the corresponding terminal of the first capacitor and one end of the third resistor are connected to the positive output terminal of the direct current power supply, the other end of the first capacitor and one end of the first resistor are connected to the gate of the first NMOS tube, the source of the second NMOS tube, the corresponding terminal of the second capacitor and one end of the fourth resistor are connected to the positive terminal of the battery to be tested, the other end of the second capacitor and one end of the second resistor are connected to the gate of the second NMOS tube, the drain of the first NMOS tube is connected to the drain of the second NMOS tube, the other end of the first resistor, the other end of the second resistor, the other end of the third resistor and the other end of the fourth resistor are connected as the trigger terminal of the positive delay on-off circuit; the specific structure of the negative delay on-off circuit comprises: a third NMOS tube, a third capacitor, a sixth resistor and a seventh resistor, the source of the third NMOS tube, the corresponding terminal of the third capacitor and one end of the sixth resistor are connected to the negative output terminal of the direct current power supply, the other end of the third capacitor and one end of the seventh resistor are connected to the gate of the third NMOS tube, the drain of the third NMOS tube is connected to the negative terminal of the battery to be tested, and the other end of the sixth resistor and the other end of the seventh resistor are connected as the trigger terminal of the negative delay on-off circuit.
3. The output control circuit of a direct current power supply according to claim 2, wherein: The time constant of the RC circuit in the negative delay on-off circuit is less than the time constant of the two RC circuits in the positive delay on-off circuit.
4. The output control circuit of a direct current power supply according to claim 2, wherein: The time constant of the two RC circuits in the positive delay on-off circuit is equivalent.
5. The output control circuit of a direct current power supply according to claim 2, wherein: The resistance value of the third resistor is greater than the resistance value of the first resistor, the resistance value of the fourth resistor is greater than the resistance value of the second resistor, and the resistance value of the sixth resistor is greater than the resistance value of the seventh resistor.
6. The output control circuit of a direct current power supply according to claim 1, wherein: The positive and negative electrode on-off trigger circuit comprises a first P-type transistor, a second N-type transistor, a fifth resistor, an eighth resistor and a ninth resistor, one end of the ninth resistor is a trigger end, the other end of the ninth resistor is connected with the base of the second N-type transistor, the emitter of the second N-type transistor is grounded, the collector of the second N-type transistor is connected with one end of the fifth resistor and one end of the eighth resistor, the other end of the fifth resistor and the emitter of the first P-type transistor are connected with the positive electrode of an auxiliary DC power supply, the other end of the eighth resistor is connected with the base of the first P-type transistor, and the collector of the first P-type transistor is an on-off control output end of the positive and negative electrode on-off trigger circuit.
7. The output control circuit of a DC power supply according to claim 1, characterized by: The tenth resistor is arranged between the positive output end and the negative output end of the DC power supply.
8. The output control circuit of a DC power supply according to claim 1, characterized by: The DC power supply is a BUCK-BOOST power supply.
9. An output control circuit for a DC power supply as claimed in any one of claims 2 to 5, wherein: The source and the drain of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are both provided with freewheeling diodes.
10. An output control circuit for a DC power supply according to claim 9, characterized in that: The source and the drain of the first NMOS transistor, the second NMOS transistor and the third NMOS transistor are both provided with freewheeling diodes.