Data protection circuit of ferroelectric memory

Abstract

The utility model discloses a data protection circuit of a ferroelectric memory, which is characterized by comprising a voltage detection module, a trigger switch module, a signal self-locking module and a power supply module, the voltage detection module is used for monitoring the power supply voltage of the power supply module in real time and comparing the power supply voltage with a preset threshold value in real time, and when the power supply voltage is lower than the preset threshold value, the output end of the voltage detection module outputs a low-level trigger signal to the input end of the trigger switch module. The trigger switch module generates a conduction signal when receiving a low-level trigger signal and sends the conduction signal to the signal self-locking module, and the signal self-locking module generates a locked low-level sleep control signal after receiving the conduction signal to control the ferroelectric memory to enter a sleep mode; the method has the advantages that the system stability can be effectively improved, the service life of the ferroelectric memory is prolonged, and the maintenance cost is reduced.

Description

Technical Field

[0001] This utility model relates to a data protection circuit, and more particularly to a data protection circuit for a ferroelectric memory. Background Technology

[0002] With the rapid development of electronic technology, various electronic devices have been widely used in industries such as industry, medicine, and communications. In these devices, the stability and reliability of data storage are crucial. Ferroelectric memories (FEs), as a type of non-volatile memory, are widely used due to their advantages such as high-speed read / write, low power consumption, and long lifespan. However, in practical applications, electronic devices often face the problem of unstable power supply voltage. When the power supply voltage drops, FEs may receive incorrect data, leading to data corruption or loss. This problem is particularly serious in mission-critical applications, potentially causing system anomalies, data inconsistencies, or even equipment failure.

[0003] Currently, while some technologies are designed to address the impact of voltage instability on storage devices, these technologies are often complex and costly, or fail to effectively prevent data errors. Utility Model Content

[0004] The technical problem to be solved by this utility model is to provide a data protection circuit for ferroelectric memory that can improve the stability and reliability of data storage.

[0005] The technical solution adopted by this utility model to solve the above-mentioned technical problems is as follows: a data protection circuit for a ferroelectric memory, including a voltage detection module, a trigger switch module, a signal self-locking module, and a power supply module. The power supply module is used to provide operating voltage to the trigger switch module and the signal self-locking module respectively. The voltage detection module is used to monitor the supply voltage of the power supply module in real time and compare the supply voltage with a preset threshold in real time. When the supply voltage is greater than the preset threshold, the output terminal of the voltage detection module outputs a high-level signal to the input terminal of the trigger switch module. When the supply voltage is lower than the preset threshold, the output terminal of the voltage detection module outputs a low-level trigger signal to the input terminal of the trigger switch module.

[0006] The trigger switch module remains open when it receives a high-level signal. When it receives a low-level trigger signal, the trigger switch module generates a conduction signal and sends it to the signal self-locking module. After receiving the conduction signal, the signal self-locking module generates a locked low-level sleep control signal and sends it to the sleep control signal input terminal of the ferroelectric memory. After receiving the locked low-level sleep control signal, the ferroelectric memory enters sleep mode.

[0007] Compared with existing technologies, the advantages of this invention lie in its real-time monitoring of the supply voltage via a voltage detection module and its comparison with a preset threshold. Once the supply voltage is detected to drop below the preset threshold, a low-level trigger signal is immediately sent to the trigger switch module, causing the trigger switch module to send a conduction signal to the signal self-locking module. Upon receiving the conduction signal, the signal self-locking module sends a locked low-level sleep control signal to the sleep control signal input of the ferroelectric memory, putting the ferroelectric memory into sleep mode to protect data security, improve system stability, extend equipment lifespan, and reduce maintenance costs. The locked low-level sleep control signal is generated using a circuit structure with a signal self-locking mechanism, ensuring that even after the supply voltage recovers, the ferroelectric memory remains in a protected state until further system operation. This design significantly improves the data reliability of the ferroelectric memory in unstable power supply environments and, due to its flexibility and scalability, can be applied to various application scenarios, providing comprehensive protection for data storage. It not only boasts advantages such as simple structure, fast response speed, low cost, and ease of implementation, but also achieves effective data protection without the need for additional control chips, further simplifying the circuit structure and reducing costs. The voltage detection module is a circuit used to monitor changes in the supply voltage in real time. It typically contains one or more comparators to compare the supply voltage with preset thresholds and output corresponding signals when the voltage is below or above these thresholds.

[0008] The voltage detection module includes a real-time monitoring module, a voltage regulator module, and a comparator module. The real-time monitoring module includes a first resistor, a second resistor, and a first capacitor. The comparator module includes a first comparator and a second capacitor. The power supply module has a 5V voltage output terminal and a 3.3V voltage output terminal. One end of the first resistor is connected to the 5V voltage output terminal of the power supply module. The other end of the first resistor, one end of the first capacitor, one end of the second resistor, and the positive voltage input terminal of the first comparator are connected together. The other end of the first capacitor and the other end of the second resistor are connected to ground. The regulated power supply output terminal of the voltage regulator module is connected to the negative voltage input terminal of the first comparator. The power input terminal of the first comparator, the 3.3V voltage output terminal of the power supply module, and one end of the second capacitor are connected together. The ground terminal of the first comparator and the other end of the second capacitor are respectively grounded. The output terminal of the first comparator is connected to the input terminal of the trigger switch module.

[0009] The voltage regulator module includes a third resistor, a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor, and a three-terminal Zener diode. One end of the third resistor, one end of the third capacitor, and the 3.3V voltage output terminal of the power supply module are connected. The other end of the third resistor, the cathode of the three-terminal Zener diode, the reference terminal of the three-terminal Zener diode, and one end of the fourth resistor are connected. The other end of the fourth resistor, one end of the fifth resistor, and one end of the fourth capacitor are connected and serve as the regulated power output terminal of the voltage regulator module. The other end of the third capacitor, the anode of the three-terminal Zener diode, the other end of the fifth resistor, and the other end of the fourth capacitor are connected to ground. By adjusting the resistance values ​​of each resistor, a trigger threshold can be set. When the voltage at the 5V output terminal of the power supply module drops, once this threshold is reached, the first comparator will output a low-level trigger signal to the input terminal of the trigger switch module. This low-level trigger signal is generated before the operating voltage of the ferroelectric memory is affected, ensuring timely response to voltage drops. Voltage drops refer to the phenomenon of a sudden drop in the supply voltage in a short period of time. Such voltage instability may cause abnormal operation of electronic devices, especially during data storage.

[0010] The trigger switch module includes a sixth resistor, a seventh resistor, and a first PMOS transistor. The signal latching module includes an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a second PMOS transistor, and a first NMOS transistor. One end of the sixth resistor is connected to the seventh resistor and serves as the input terminal of the trigger switch module. The other end of the seventh resistor is connected to the gate of the first PMOS transistor. The other end of the sixth resistor, the source of the first PMOS transistor, the source of the second PMOS transistor, and one end of the eighth resistor are connected and connected to the 3.3V voltage output terminal of the power supply module. The drain of the MOS transistor, the drain of the second PMOS transistor, one end of the tenth resistor, and one end of the eleventh resistor are connected. The gate of the second PMOS transistor is connected to one end of the ninth resistor. The other end of the eighth resistor, the other end of the ninth resistor, and the drain of the first NMOS transistor are connected and serve as the output terminal of the signal self-locking module. The output terminal of the signal self-locking module is used to connect to the sleep control signal input terminal of the ferroelectric memory. The other end of the tenth resistor is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor and the other end of the eleventh resistor are connected to ground in parallel.

[0011] Under normal conditions, the first comparator outputs a high-level signal. At this time, the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are all in the off state and do not conduct. Therefore, the signal output from the signal latching module remains at a high level, and the ferroelectric memory works normally. When the first comparator outputs a low-level trigger signal, the first PMOS transistor turns on first. Subsequently, due to the conduction of the first PMOS transistor, the gate voltage of the first NMOS transistor decreases, causing the first NMOS transistor to also turn on. Then, the gate voltage of the second PMOS transistor is pulled low through the first NMOS transistor, causing the second PMOS transistor to also turn on. This series of conduction actions causes the signal output from the signal latching module to be pulled low and transmitted to the sleep control signal input of the ferroelectric memory, causing the ferroelectric memory to enter sleep mode to protect the data. At this time, the ferroelectric memory stops transmitting data with the controller main chip, thereby effectively avoiding the risk of receiving erroneous data when the power supply voltage is unstable. Attached Figure Description

[0012] Figure 1 This is a circuit block diagram of the present invention;

[0013] Figure 2 This is a circuit diagram of the voltage detection module in this utility model;

[0014] Figure 3 This is a circuit diagram of the trigger switch module and the signal self-locking module in this utility model. Detailed Implementation

[0015] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0016] like Figure 1 , Figure 2As shown, a data protection circuit for a ferroelectric memory includes a voltage detection module, a trigger switch module 1, a signal latching module 2, and a power supply module 3. The power supply module 3 provides operating voltages to the trigger switch module 1 and the signal latching module 2, respectively. The voltage detection module monitors the supply voltage of the power supply module 3 in real time and compares the supply voltage with a preset threshold. When the supply voltage is greater than the preset threshold, the output terminal of the voltage detection module outputs a high-level signal to the input terminal of the trigger switch module 1; when the supply voltage is lower than the preset threshold, the output terminal of the voltage detection module outputs a low-level signal. A signal is sent to the input terminal of the trigger switch module 1; the voltage detection module includes a real-time monitoring module 4, a voltage regulator module 5, and a comparator module 6. The real-time monitoring module 4 includes a first resistor R1, a second resistor R2, and a first capacitor C1. The comparator module 6 includes a first comparator U1 and a second capacitor C2. The power supply module 3 is provided with a 5V voltage output terminal and a 3.3V voltage output terminal. One end of the first resistor R1 is connected to the 5V voltage output terminal of the power supply module 3. The other end of the first resistor R1, one end of the first capacitor C1, one end of the second resistor R2, and the positive voltage input of the first comparator U1 are also connected. The first capacitor C1 is connected to the second capacitor R2, with the other end of the first capacitor C1 connected to ground. The regulated power supply output of the voltage regulator module 5 is connected to the negative voltage input of the first comparator U1. The power input of the first comparator U1, the 3.3V voltage output of the power supply module 3, and one end of the second capacitor C2 are connected. The ground terminal of the first comparator U1 and the other end of the second capacitor C2 are respectively grounded. The output of the first comparator U1 is connected to the input of the trigger switch module 1. The voltage regulator module 5 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5, a third capacitor C3, a fourth resistor R4, a fifth resistor R5, a fifth capacitor R6, a sixth resistor R7, a seventh resistor R8, a seventh resistor R9, a stern resistor R1, a stern resistor R1, a stern resistor R1, a stern resistor R1, a stern resistor R2 ... Capacitor C4 and Zener diode U2 are connected to one end of the third resistor R3, one end of the third capacitor C3, and the 3.3V voltage output terminal of power module 3. The other end of the third resistor R3 is connected to the cathode of Zener diode U2, the reference terminal of Zener diode U2, and one end of the fourth resistor R4. The other end of the fourth resistor R4, one end of the fifth resistor R5, and one end of the fourth capacitor C4 are connected and serve as the regulated power output terminal of voltage regulator module 5. The other end of the third capacitor C3, the anode of Zener diode U2, the other end of the fifth resistor R5, and the other end of the fourth capacitor C4 are connected to ground. The voltage detection module uses a high-precision first comparator U1 as its core component. The positive voltage input terminal of the first comparator U1 is connected to the real-time monitoring module 4, which monitors the voltage output status of the 5V voltage output terminal of power module 3 in real time. The negative voltage input terminal of the first comparator U1 is connected to the regulated power output terminal of voltage regulator module 5, which provides a stable reference voltage for the first comparator U1.

[0017] Trigger switch module 1 remains open when it receives a high-level signal. When it receives a low-level trigger signal, it generates a conduction signal and sends it to signal self-locking module 2. Signal self-locking module 2 generates a locked low-level sleep control signal after receiving the conduction signal and sends it to the sleep control signal input terminal of ferroelectric memory 7. Ferroelectric memory 7 enters sleep mode after receiving the locked low-level sleep control signal. Ferroelectric memory 7 is a non-volatile memory that uses ferroelectric material as the storage medium. It combines the fast read / write characteristics of RAM with the advantages of non-volatile storage and can retain data after power failure. Sleep mode is a low-power operating state in which electronic devices or specific components suspend most functions to save energy. In this embodiment, ferroelectric memory 7 entering sleep mode means that it suspends data transmission with the controller main chip.

[0018] Trigger switch module 1 includes a sixth resistor R6, a seventh resistor R7, and a first PMOS transistor Q1. Signal latching module 2 includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a second PMOS transistor Q2, and a first NMOS transistor Q3. One end of the sixth resistor R6 is connected to the seventh resistor R7 and serves as the input terminal of trigger switch module 1. The other end of the seventh resistor R7 is connected to the gate of the first PMOS transistor Q1. The other end of the sixth resistor R6, the source of the first PMOS transistor Q1, the source of the second PMOS transistor Q2, and one end of the eighth resistor R8 are connected to the 3.3V voltage output terminal of power supply module 3. The drains of the first PMOS transistor Q1 and the second PMOS transistor Q2, one end of the tenth resistor R10, and one end of the eleventh resistor R11 are connected. The gate of the second PMOS transistor Q2 is connected to one end of the ninth resistor R9. The other end of the eighth resistor R8, the other end of the ninth resistor R9, and the drain of the first NMOS transistor Q3 are connected and serve as the output terminal of the signal self-locking module 2. The output terminal of the signal self-locking module 2 is used to connect to the sleep control signal input terminal of the ferroelectric memory 7. The other end of the tenth resistor R10 is connected to the gate of the first NMOS transistor Q3, and the source of the first NMOS transistor Q3 is connected to ground in parallel with the other end of the eleventh resistor R11. When the signal output by the first comparator U1 returns to a high level, although the first PMOS transistor Q1 is no longer turned on, a self-locking state is formed between the second PMOS transistor Q2 and the first NMOS transistor Q3. This self-locking mechanism ensures that even if the signal output by the first comparator U1 returns to a high level, the signal output by the signal self-locking module 2 remains at a low level, thereby continuously protecting the data in the ferroelectric memory 7 from damage.

[0019] The overall workflow is as follows:

[0020] 1. When the system starts up, the voltage detection module, trigger switch module 1 and signal self-locking module 2 are all in the initial state, and the ferroelectric memory 7 is working normally;

[0021] 2. The voltage detection module monitors the power supply voltage of the power module 3 in real time;

[0022] 3. If the power supply voltage drops below the preset threshold, the voltage detection module outputs a low-level trigger signal to the trigger switch module 1;

[0023] 4. After receiving a low-level trigger signal, the trigger switch module 1 generates a conduction signal and sends it to the signal self-locking module 2. The signal output from the output terminal of the signal self-locking module 2 is pulled to a low level and transmitted to the sleep control signal input terminal of the ferroelectric memory 7, so that the ferroelectric memory 7 enters sleep mode to protect the data. At the same time, the signal self-locking module 2 locks the signal output from the output terminal to keep it in a low-level state through the self-locking mechanism.

[0024] 5. After troubleshooting, the system can be restored to its initial state by powering on again. At this time, the voltage detection module and the signal self-locking module 2 will be restored to their default state, i.e., the untriggered state. This means that the low-level trigger signal and the signal output from the output terminal of the signal self-locking module 2 will be restored to the high-level state, preparing for the normal operation of the ferroelectric memory 7. This design effectively prevents the ferroelectric memory 7 from repeatedly starting and stopping due to voltage fluctuations, thereby avoiding possible data errors.

Claims

1. A data protection circuit for a ferroelectric memory, characterized by The application comprises a voltage detection module, a trigger switch module, a signal self-locking module and a power module, the power module is used for providing working voltage to the trigger switch module and the signal self-locking module respectively, the voltage detection module is used for monitoring the power supply voltage of the power module in real time and comparing the power supply voltage with a preset threshold value in real time, when the power supply voltage is greater than the preset threshold value, the output end of the voltage detection module outputs a high level signal to the input end of the trigger switch module, when the power supply voltage is lower than the preset threshold value, the output end of the voltage detection module outputs a low level trigger signal to the input end of the trigger switch module; The trigger switch module keeps off when receiving the high level signal, the trigger switch module generates a conduction signal and sends it to the signal self-locking module when receiving the low level trigger signal, the signal self-locking module generates a locked low level sleep control signal and sends it to the sleep control signal input end of the ferroelectric memory after receiving the conduction signal, the ferroelectric memory enters the sleep mode after receiving the locked low level sleep control signal.

2. A data protection circuit for a ferroelectric memory as claimed in claim 1, characterized in that The voltage detection module comprises a real-time monitoring module, a voltage stabilizing source module and a comparator module, the real-time monitoring module comprises a first resistor, a second resistor and a first capacitor, the comparator module comprises a first comparator and a second capacitor, the power module is provided with a 5V voltage output end and a 3.3V voltage output end, one end of the first resistor is connected with the 5V voltage output end of the power module, the other end of the first resistor, one end of the first capacitor, one end of the second resistor and the positive voltage input end of the first comparator are connected, the other end of the first capacitor and the other end of the second resistor are connected with the ground, the voltage stabilizing source output end of the voltage stabilizing source module is connected with the negative voltage input end of the first comparator, the power input end of the first comparator, the 3.3V voltage output end of the power module and one end of the second capacitor are connected, the ground end of the first comparator and the other end of the second capacitor are grounded respectively, and the output end of the first comparator is connected with the input end of the trigger switch module.

3. A data protection circuit for a ferroelectric memory as claimed in claim 2, characterized in that The voltage stabilizing source module comprises a third resistor, a fourth resistor, a fifth resistor, a third capacitor, a fourth capacitor and a three-terminal voltage stabilizing tube, one end of the third resistor, one end of the third capacitor and the 3.3V voltage output end of the power module are connected, the other end of the third resistor, the cathode of the three-terminal voltage stabilizing tube, the reference end of the three-terminal voltage stabilizing tube and one end of the fourth resistor are connected, the other end of the fourth resistor, one end of the fifth resistor and one end of the fourth capacitor are connected and used as the voltage stabilizing source output end of the voltage stabilizing source module, the other end of the third capacitor, the anode of the three-terminal voltage stabilizing tube, the other end of the fifth resistor and the other end of the fourth capacitor are connected with the ground.

4. A data protection circuit for a ferroelectric memory as recited in claim 2, wherein The trigger switch module comprises a sixth resistor, a seventh resistor and a first PMOS tube, the signal self-locking module comprises an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a second PMOS tube and a first NMOS tube, one end of the sixth resistor is connected with the seventh resistor and serves as an input end of the trigger switch module, the other end of the seventh resistor is connected with the gate of the first PMOS tube, the other end of the sixth resistor, the source of the first PMOS tube, the source of the second PMOS tube, one end of the eighth resistor are connected and connected with the 3.3V voltage output end of the power module, the drain of the first PMOS tube, the drain of the second PMOS tube, one end of the tenth resistor, one end of the eleventh resistor are connected, the gate of the second PMOS tube is connected with one end of the ninth resistor, the other end of the eighth resistor, the other end of the ninth resistor, the drain of the first NMOS tube are connected and serve as an output end of the signal self-locking module, the output end of the signal self-locking module is used for being connected with the sleep control signal input end of the ferroelectric memory, the other end of the tenth resistor is connected with the gate of the first NMOS tube, the source of the first NMOS tube is connected with the other end of the eleventh resistor and grounded.

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