Multiplexing control circuit of multi-bus signal and image signal generator
By using a multiplexing control circuit for multi-bus signals, flexible switching between IIC and QSPI signals is achieved, solving the problems of complexity and high cost of existing image signal generator interfaces, simplifying interface design and reducing manufacturing costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2026-03-06
AI Technical Summary
Existing image signal generators require multiple external interfaces to support different types of bus signals, which increases device complexity and manufacturing costs.
By employing a multiplexing control circuit for multi-bus signals, and through the design of a controller, output line switching module, and external interface module, flexible switching and output of IIC and QSPI signals are achieved, simplifying interface design.
By enabling flexible switching between different bus signals through an external interface module, the complexity of the device and manufacturing costs are reduced.
Smart Images
Figure CN223978671U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of communication technology, and in particular to a multiplexing control circuit for multi-bus signals and an image signal generator. Background Technology
[0002] In display testing, an image signal generator sends at least two different types of bus signals to multiple displays to control the displays during testing. These bus signals can include, but are not limited to, Inter-Integrated Circuit (IIC) signals and Queued Serial Peripheral Interface (QSPI) signals. However, existing image signal generators require multiple external interfaces corresponding to each bus signal type, which increases the complexity and manufacturing cost of the image signal generator to some extent. Summary of the Invention
[0003] In view of this, the present invention provides a multiplexing control circuit for multiple bus signals and an image signal generator.
[0004] In a first aspect, this utility model provides a multiplexing control circuit for multi-bus signals, comprising: a controller, an output line switching module, and an external interface module; the controller includes at least one set of IIC bus protocol pins and six QSPI bus protocol pins; the controller is connected to the first set of input terminals of the output line switching module through the IIC bus protocol pins; the controller is connected to the second set of input terminals of the output line switching module through the multiplexing target number pin among the six QSPI bus protocol pins, and is connected to the external interface module through the remaining pins among the six QSPI bus protocol pins; the output terminal of the output line switching module is connected to the external interface module, and the output line switching module connects the output terminal to the first set of input terminals or to the second set of input terminals according to the switching control signal sent by the controller.
[0005] Secondly, the image signal generator provided in this embodiment of the present invention includes any of the multiplexing control circuits for multi-bus signals provided in this embodiment of the present invention.
[0006] In summary, the multiplexing control circuit for multi-bus signals and the image signal generating device provided by this utility model have at least the following beneficial effects:
[0007] The controller connects to the first set of input terminals of the output line switching module via at least one set of IIC bus protocol pins, to the second set of input terminals of the output line switching module via a multiplexed target number of QSPI bus protocol pins, and to the external interface module via the remaining QSPI bus protocol pins. This allows the controller to input and output IIC and QSPI signals to the output line switching module. Furthermore, the output terminal of the output line switching module is connected to the external interface module. Based on the switching control signal sent by the controller, the output terminal connects to either the first or second set of input terminals, thereby outputting IIC or QSPI signals through the external interface module. In this way, different bus signals can be provided through a single external interface module, enabling flexible signal switching, simplifying interface design, and saving manufacturing costs. Attached Figure Description
[0008] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0009] Figure 1 This diagram illustrates the structure of a multiplexing control circuit for multi-bus signals provided by this utility model.
[0010] Figure 2 This diagram shows a structural schematic of an output line switching module provided by this utility model;
[0011] Figure 3 This diagram shows a structural schematic of a resistance switching submodule provided by this utility model;
[0012] Figure 4 This diagram shows a structural schematic of a level conversion module provided by this utility model;
[0013] Figure 5 This diagram shows the structure of an image signal generator provided by the present invention. Detailed Implementation
[0014] In the description of this application, it should be understood that the use of terms such as "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" to indicate orientation or positional relationship, unless otherwise specified, is understood to be based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0015] Furthermore, features specified with "first" or "second" for descriptive purposes only should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Features specified with "first" or "second" may explicitly or implicitly include at least one of the specified features. The description of "multiple" generally means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0016] In this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can be a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0017] In the description of this specification, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that the specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0018] Figure 1 This diagram illustrates the structure of a multiplexing control circuit for multi-bus signals provided by this invention. Figure 1As shown, the multiplexing control circuit 10 for multi-bus signals may include a controller 11, an output line switching module 12, and an external interface module 13.
[0019] The controller 11 may include at least one set of IIC bus protocol pins and six QSPI bus protocol pins. One set of IIC bus protocol pins is used to output a set of IIC signals, which may include a serial data line (SDA) pin and a serial clock line (SCL) pin. The number of sets of IIC bus protocol pins shall not exceed three.
[0020] The six QSPI bus protocol pins can be used to output QSPI signals, including one Chip Select (CS) signal pin, a Serial Clock (SCK) signal pin, and four data signal pins. The four data signal pins can be represented as IO0-IO3.
[0021] The controller 11 is connected to the first set of input terminals of the output line switching module 12 via IIC bus protocol pins. That is, each IIC bus protocol pin in the controller 11 is connected to each input terminal in the first set of input terminals of the output line switching module 12, so that the controller 11 can input all IIC signals to the output line switching module 12.
[0022] The controller 11 is connected to the second set of input terminals of the output line switching module 12 through the multiplexing target number pin among the six QSPI bus protocol pins. That is, the controller 11 can input a portion of the QSPI signals to the output line switching module 12.
[0023] The controller 11 is connected to the external interface module 13 via the remaining pins of the six QSPI bus protocol pins. In other words, the controller 11 can input another part of the QSPI signals to the external interface module 12.
[0024] The target number of multiplexed pins in this utility model can refer to the pins among the six QSPI bus protocol pins that have the same number as the IIC bus protocol pins and are connected to the second group of input terminals of the output line switching module 12. The remaining pins can refer to the other pins among the six QSPI bus protocol pins besides the target number of multiplexed pins.
[0025] For example, the number of IIC bus protocol pins is 2, the number of multiplexed target pins is 2, and the number of remaining pins is 4. Alternatively, the number of IIC bus protocol pins is 4, the number of multiplexed target pins is 4, and the number of remaining pins is 2. Or, the number of IIC bus protocol pins is 6, the number of multiplexed target pins is 6, and the number of remaining pins is 0.
[0026] The output terminal of the output line switching module 12 is connected to the external interface module 13. According to the switching control signal SW_Ctrl sent by the controller 11, the output terminal of the output line switching module 12 is connected to the first group of input terminals or the second group of input terminals, so as to input the IIC signal or part of the QSPI signal to the external interface module 13, so that the external interface module 13 can provide the IIC signal or QSPI signal to the outside.
[0027] In one embodiment of this utility model, when the switching control signal indicates a switch to the IIC signal, the output line switching module 12 connects its output terminal to the first set of input terminals. Furthermore, the output terminal of the output line switching module 12 is connected to the external interface module 13. Thus, the IIC signal sent by the controller 11 can be transmitted to the external interface module 13 through the output line switching module 12, enabling the external interface module 13 to provide the IIC signal to external devices.
[0028] In another embodiment of this utility model, when the switching control signal indicates a switch to the QSPI signal, the output line switching module 12 connects its output terminal to the second set of input terminals. Furthermore, the output terminal of the output line switching module 12 is connected to the external interface module 13. Thus, the external interface module 13 can receive a portion of the QSPI signal through the output line switching module 12 and another portion of the QSPI signal directly transmitted by the controller 11 through the remaining pins, thereby enabling the external interface module 13 to provide a complete QSPI signal to external devices.
[0029] It should be noted that external devices refer to devices connected to the external interface module 13.
[0030] In the above embodiment, the controller connects to the first set of input terminals of the output line switching module through at least one set of IIC bus protocol pins, connects to the second set of input terminals of the output line switching module through multiplexing a target number of QSPI bus protocol pins, and connects to the external interface module through the remaining QSPI bus protocol pins. This allows the controller to input IIC and QSPI signals to the output line switching module. Furthermore, the output terminal of the output line switching module is connected to the external interface module. Based on the switching control signal sent by the controller, the output terminal connects to either the first or second set of input terminals, thereby outputting IIC or QSPI signals to the external interface module. In this way, different bus signals can be provided externally through a single external interface module, enabling flexible signal switching, simplifying interface design, and saving manufacturing costs.
[0031] Figure 2 This diagram illustrates the structure of an output line switching module provided by this utility model. Figure 2 As shown, the output line switching module 12 may include a set of switches 21. The first set of input terminals and the second set of input terminals of the output line switching module 12 are connected one-to-one with the set of switches 21. The output terminals of the set of switches 21 are connected to the external interface module 13.
[0032] The number of switches 21 in a group of switches 21 is equal to the number of IIC bus protocol pins, which is also equal to the number of multiplexed target pins.
[0033] Switch 21 can be a single-pole double-throw switch, which can include two input terminals and one output terminal. One input terminal of the first group of input terminals and one input terminal of the second group of input terminals of the output line switching module 12 can be connected to the two input terminals of the same switch one by one. The output terminal of switch 21 is connected to the external interface module 13.
[0034] It should be noted that the different input terminals in the first group of input terminals and the second group of input terminals correspond to the input terminals of different switches.
[0035] Multiple outputs of a group of switches 21 need to be simultaneously connected to the corresponding inputs of a group of inputs of the output line switching module 12. That is, when the switching control signal is 1, each output of each switch 21 needs to be simultaneously connected to the input of each input in the first group of inputs of the output line switching module 12 in order to provide an IIC signal to the external interface module 13. Alternatively, when the switching control signal is 0, each output of each group of switches 21 needs to be simultaneously connected to the input of each input in the second group of inputs of the output line switching module 12 in order to provide a portion of the QSPI signal to the external interface module 13.
[0036] In the above embodiments, a set of switches can be used to flexibly switch between IIC and QSPI signals.
[0037] In some embodiments, the number of IIC bus protocol pin groups is two. The controller is connected to the second group of input terminals of the output line switching module through the multiplexed target number pins of the six QSPI bus protocol pins, and connected to the external interface module through the remaining pins of the six QSPI bus protocol pins. This includes: the controller is connected to the second group of input terminals of the output line switching module through four pins of the six QSPI bus protocol pins, and connected to the external interface module through two pins of the six QSPI bus protocol pins.
[0038] In one embodiment of this utility model, the target number of pins can be four pins, including one CS signal pin, one SCK signal pin, and two data signal pins.
[0039] In some embodiments, when there are two groups of IIC bus protocol pins, one group of switches 21 consists of four switches 21. The controller 11 controls the four switches 21 to be connected to the first group of input terminals or to the second group of input terminals simultaneously via control signals.
[0040] It should be noted that, Figure 1 The diagram shows a multiplexing circuit structure when there are two pin groups for the IIC bus protocol, and... Figure 2 This diagram shows a switch 21 with two groups of IIC bus protocol pins.
[0041] In some embodiments, such as Figure 1 As shown, the multiplexing control circuit also includes a pull-up resistor switching module 14.
[0042] The input terminal of the pull-up resistor switching module 14 is connected to the controller, and the multiple output terminals are connected to the first set of input terminals of the output line switching module.
[0043] In one embodiment of this utility model, the input terminal of the pull-up resistor switching module 14 is used to receive the resistance value switching signal sent by the controller 11. The number of output terminals of the pull-up resistor switching module 14 is equal to the number of the first group of input terminals of the output line switching module. For example, the first group of input terminals includes four input terminals, and the pull-up resistor switching module 14 includes four output terminals.
[0044] Furthermore, each output terminal of the pull-up resistor switching module 14 is connected to each input terminal in the first group of input terminals in a one-to-one correspondence. That is, each output terminal of the pull-up resistor switching module 14 is connected to each input terminal in the first group of input terminals in a one-to-one correspondence, and is also connected to each IIC bus protocol pin in a one-to-one correspondence.
[0045] The pull-up resistor switching module 14 can be used to control the transmission rate of the IIC signal according to the resistor switching signal R_Ctrl, or to ground the IIC bus protocol pin in non-IIC mode.
[0046] The pull-up resistor switching module includes multiple parallel resistance value switching sub-modules. Each resistance value switching sub-module includes multiple pull-up resistors with different resistance values and a grounding resistor. The number of resistance value switching sub-modules is equal to the number of IIC bus protocol pins. For example, if there are 4 IIC bus protocol pins, there are 4 resistance value switching sub-modules.
[0047] The output of each resistance switching submodule serves as an output of the pull-up resistor switching module 14. That is, each resistance switching module is connected to each input in the first group of inputs and also to each IIC bus protocol pin.
[0048] Each of the aforementioned resistance switching submodules is used to switch to different pull-up resistors or ground resistors based on the resistance switching signal. When a resistance switching submodule switches to different pull-up resistors according to the resistance switching signal, it can correspond to different rise and fall times of the signal, thereby controlling the transmission rate of the SDA or SCL signal on the IIC bus protocol pin connected to the corresponding resistance switching submodule. When a resistance switching submodule switches to the ground resistor according to the resistance switching signal, it can control the grounding of the IIC bus protocol pin connected to the corresponding resistance switching submodule.
[0049] It should be noted that the resistors used in all resistance switching submodules must be consistent. A larger pull-up resistor value results in longer signal rise and fall times, and a lower transmission rate.
[0050] Each resistance switching submodule may also include at least one switch, which enables the resistance switching submodule to switch between different resistances.
[0051] It should be noted that when the switch is a single-pole double-throw switch, the resistance switching submodule can include two switches. When the switch is a single-pole multi-throw switch, the resistance switching submodule can include one switch.
[0052] Figure 3 This diagram illustrates the structure of a resistance switching submodule provided by this invention. Figure 3 As shown, the resistance switching submodule 30 may include two pull-up resistors (R1 and R2) with different resistance values, a grounding resistor R3, a first switch 31, and a second switch 32. Optionally, R1 can be 1 kΩ, R2 can be 100 kΩ, and R3 can have any resistance value.
[0053] It should be noted that switching to R1 enables high-speed transmission of the IIC signal, while switching to R2 enables low-speed transmission of the IIC signal.
[0054] like Figure 3 As shown, one end of R1 and R2 is connected to the power supply IIC_VCC_ADJ, and one end of R3 is connected to ground. The other ends of R1 and R2 are connected to the two input terminals of the first switch 31, respectively. The output terminal of the first switch 31 is connected to one input terminal of the second switch 32, and the other input terminal of the second switch 32 is connected to the other end of R3.
[0055] The output terminal of the second switch 32 serves as the output terminal of the resistance switching submodule 30.
[0056] The resistor switching signal may include a control signal ctrl0 for controlling the first switch 31 and a control signal ctrl1 for controlling the second switch 32.
[0057] When the first switch 31 and the second switch 32 are connected, the SDA signal or SCL signal on the IIC bus protocol pin corresponding to the resistance switching submodule 30 can be pulled up to the power supply IIC_VCC_ADJ through R1 or R2.
[0058] In the above embodiments, the pull-up resistor switching module can control the transmission rate of the IIC signal and connect the IIC bus protocol pin to ground in non-IIC mode.
[0059] In some embodiments, since the signal level required by the external device connected to the external interface module 13 may not match the signal level of the controller 11, level conversion is required.
[0060] It should be noted that level conversion can refer to converting a signal from one voltage level to another.
[0061] When the IIC signal level required by the external device does not match the IIC signal level output by the controller 11, such as when the IIC signal level output by the controller 11 is 1.2 volts and the IIC signal level required by the external device is 3.3 volts, ... Figure 1 As shown, the multiplexing control circuit 10 for multiple bus signals may include an IIC level conversion module 15.
[0062] The IIC level conversion module 15 is connected in series between the IIC bus protocol pins and the first set of input terminals of the output line switching module 12. The IIC level conversion module 15 includes multiple input terminals and multiple output terminals, and the number of input terminals and output terminals of the IIC level conversion module 15 is the same as the number of IIC bus protocol pins.
[0063] In other words, each input terminal of the IIC level conversion module 15 is connected to each IIC bus protocol pin in a one-to-one correspondence, and each output terminal is connected to each input terminal in the first group of input terminals of the output line switching module 12 in a one-to-one correspondence.
[0064] For example, the IIC signal level output by the controller 11 is 1.2 volts, while the IIC signal level required by the external device is 3.3 volts. The 1.2 volt IIC signal can be converted into a 3.3 volt signal by the IIC level conversion module 15.
[0065] The controller 11 can be used to send an IIC enable signal IIC_EN to the IIC level conversion module 15. The IIC level conversion module 15 determines whether it is enabled based on the IIC enable signal. When IIC_EN is 1, the IIC level conversion module 15 is enabled; when IIC_EN is 0, the IIC level conversion module 15 is not enabled.
[0066] When enabled, the IIC level conversion module 15 is used to convert the level of the IIC signal output by the controller 11 into a specified level of IIC signal that matches the external device.
[0067] For example, the IIC signal level output by the controller 11 is 1.2 volts, and the IIC signal level required by the external device is 3.3 volts. The IIC level conversion module 15 can be enabled to convert the 1.2 volt IIC signal into a 3.3 volt IIC signal and input it to the output line switching module 12.
[0068] The IIC level conversion module 15 can be constructed using existing IIC level conversion circuits, which will not be described in detail in this utility model.
[0069] When the IIC signal level required by the external device does not match the IIC signal level output by the controller 11, such as when the QSPI signal level output by the controller 11 is 1.2 volts and the QSPI signal level required by the external device is 3.3 volts, ... Figure 1 As shown, the multiplexing control circuit 10 for multiple bus signals may include a QSPI level conversion module 16.
[0070] The QSPI level conversion module 16 includes six input terminals and six output terminals. The six input terminals are respectively connected to six QSPI bus protocol pins. The target multiplexing quantity output terminal among the six output terminals is respectively connected to the second group of input terminals of the output line switching module 12. The remaining output terminals among the six output terminals are respectively connected to the external interface module 13.
[0071] The controller 11 can be used to send a QSPI enable signal QSPI_OE to the QSPI level conversion module 16. The QSPI level conversion module 16 determines whether it is enabled based on the QSPI enable signal. When QSPI_OE is 1, the QSPI level conversion module 16 is enabled; when QSPI_OE is 0, the QSPI level conversion module 16 is not enabled.
[0072] When enabled, the QSPI level conversion module 16 is used to convert the level of the QSPI signal output by the controller 11 into a QSPI signal with a specified level that matches the external device.
[0073] For example, the QSPI signal level output by the controller 11 is 1.2 volts, while the QSPI level required by the external device is 3.3 volts. The QSPI level conversion module 16 can be enabled to convert the 1.2 volt QSPI signal into a 3.3 volt QSPI signal, and input a part of the signal to the output line switching module 12 and another part of the signal to the external interface module 13.
[0074] The QSPI level conversion module 16 can be constructed using existing QSPI level conversion circuits, which will not be described in detail in this utility model.
[0075] In some embodiments, since the IIC level conversion module 15 and the QSPI level conversion module 16 need to provide a specified conversion level in order to convert the signal level output by the controller to a specified level, a level conversion module can be added for flexible level conversion.
[0076] like Figure 1 As shown, the multiplexing control circuit 10 for multiple bus signals may include a level conversion module 17.
[0077] The level conversion module 17 includes two input terminals, a first output terminal, and a second output terminal. The two input terminals are connected to the controller 11, the first output terminal is connected to the IIC level conversion module 15, and the second output terminal is connected to the QSPI level conversion module 16. One input terminal is a voltage input terminal, and the other is a control signal input terminal.
[0078] Controller 11 provides input levels to level conversion module 17 and provides level conversion control signals to level conversion module 17. The voltage input terminal receives the input level V_in provided by controller 11. The control signal input terminal receives the level conversion control signal V_Ctrl sent by the control signal.
[0079] The level conversion control module 17 converts the input level to a specified level VCC_ADJ output based on the level conversion control signal. The specified level can refer to the level required by the external device. Optionally, the input level can be 5 volts. The specified level can be 1.8 volts or 3.3 volts.
[0080] Figure 4 This diagram illustrates the structure of a level conversion module provided by this utility model. Figure 4 As shown, the level conversion module 17 may include a low dropout linear regulator module 41, multiple resistors (i.e., R4 to R6) and a switch 42.
[0081] The low dropout linear regulator module 41 may include an input terminal IN, an output terminal OUT, and a voltage adjustment terminal ADJ.
[0082] like Figure 4 As shown, one end of R4 is connected to the output terminal of the low-dropout linear regulator module 41, and the other end of R4 is connected to one end of R5, as well as the output terminal of the low-dropout linear regulator module 41. The other end of R5 is connected to the output terminal of the switch 42. One input terminal of the switch 42 is connected to ground, and the other input terminal is connected to R6. The other end of R6 is connected to ground.
[0083] Switch 42 can connect its output to ground or to resistor R6 based on the level conversion control signal. For example, if the input level provided by controller 11 is 5 volts, R4 is 1 kΩ, R5 is 442 Ω, and R6 is 1.2 kΩ, when the level conversion control signal is 0, switch 42 connects its output to ground, and the level conversion module outputs 1.8 volts. When the level conversion control signal is 0, switch 42 connects its output to R6, and the level conversion module outputs 3.3 volts.
[0084] The formula for calculating the output voltage of the level conversion module can be as follows.
[0085]
[0086] Where Rt is the resistance value of R4, Rb is the resistance value of R5 when the level conversion control signal is 0, and Rb is the sum of the resistance values of R5 and R6 when the level conversion control signal is 0.
[0087] In addition, the level conversion module 17 may also include multiple capacitors. These multiple capacitors may include capacitors with three different capacitance values. At least three capacitors with different capacitance values (e.g., C1 to C3) are connected in parallel, with one end of each of the at least three parallel capacitors connected to the voltage input terminal and the other end connected to ground. The at least three parallel capacitors are used to filter the input level.
[0088] At least two capacitors with different capacitance values (such as C4 and C5) are connected in parallel. One end of the at least two parallel capacitors is connected to the first input terminal and the second output terminal, and the other end is grounded. The at least two parallel capacitors are used to filter the output level.
[0089] Thus, the level conversion module 17 can provide a stable specified level to the IIC level conversion module 15 and the QSPI level conversion module 16, so that the IIC level conversion module 15 and the QSPI level conversion module can convert the controller output signal into a specified level signal.
[0090] In one embodiment, the multiplexing control circuit 10 disables the IIC level conversion module 15 and the QSPI level conversion module 16 during initialization, thereby not outputting any signals.
[0091] In some embodiments, the controller 11 integrates a fully programmable system-on-a-chip, including a first processor and a second processor. The first processor has IIC bus protocol pins, and the second processor has six QSPI bus protocol pins.
[0092] Another embodiment of this utility model provides an image signal generator. Figure 5 This invention provides a schematic diagram of the structure of an image signal generator, as shown below. Figure 5 As shown, the image signal generator 50 may include any of the multiplexing control circuits 10 for multi-bus signals provided by this utility model.
[0093] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.
Claims
1. A multiplexing control circuit for a plurality of bus signals, characterized by The application relates to a multiplexing control circuit. The controller, the output line switching module and the external interface module; The controller comprises at least one IIC bus protocol pin group and six QSPI bus protocol pins; The controller is connected with a first group of input ends of the output line switching module through the IIC bus protocol pins; The controller is connected with a second group of input ends of the output line switching module through multiplex target quantity pins in the six QSPI bus protocol pins and is connected with the external interface module through the remaining pins in the six QSPI bus protocol pins; The output end of the output line switching module is connected with the external interface module, and the output line switching module is connected with the first group of input ends or the second group of input ends according to a switching control signal sent by the controller.
2. The multiplex control circuit of claim 1, wherein, The output line switching module comprises a group of switchers, the first group of input ends and the second group of input ends of the output line switching module are respectively connected with the group of switchers one by one, and the output end of the group of switchers is connected with the external interface module.
3. The multiplex control circuit of claim 1, wherein, The IIC bus protocol pin group is two groups, the controller is connected with the second group of input ends of the output line switching module through multiplex target quantity pins in the six QSPI bus protocol pins and is connected with the external interface module through the remaining pins in the six QSPI bus protocol pins, and the method comprises the following steps: The controller is connected with the second group of input ends of the output line switching module through four pins in the six QSPI bus protocol pins and is connected with the external interface module through two pins in the six QSPI bus protocol pins.
4. The multiplex control circuit of claim 2, wherein, The group of switchers is four switchers, and the controller controls the four switchers to be simultaneously connected with the first group of input ends or the second group of input ends through a control signal.
5. The multiplex control circuit of claim 1, wherein, The multiplexing control circuit further comprises a pull-up resistance switching module: The input end of the pull-up resistance switching module is connected with the controller, and a plurality of output ends are respectively connected with the first group of input ends of the output line switching module one by one; The pull-up resistance switching module comprises a plurality of parallel resistance value switching submodules, each resistance value switching submodule comprises a plurality of pull-up resistors with different resistance values and a grounding resistor, and the controller sends a resistance switching signal to the pull-up resistance switching module in an IIC mode; Each resistance value switching submodule is used for switching to different pull-up resistors or grounding resistors based on the resistance switching signal.
6. The multiplex control circuit of claim 1, wherein, The multiplexing control circuit further comprises an IIC level conversion module; The IIC level conversion module is connected in series between the IIC bus protocol pins and the first group of input ends of the output line switching module.
7. The multiplex control circuit of claim 6, wherein, The multiplexing control circuit further comprises a QSPI level conversion module; The QSPI level conversion module includes six input ends and six output ends, the six input ends are connected with the six QSPI bus protocol pins respectively, target multiplexing number of output ends in the six output ends are connected with the second group of input ends of the output line switching module one by one respectively, the remaining output ends in the six output ends are connected with the external interface module respectively.
8. The multiplex control circuit of claim 7, wherein, The multiplexing control circuit further includes a level conversion module. The level conversion module includes two input ends, a first output end and a second output end, the two input ends are connected with the controller, the first output end is connected with the IIC level conversion module, and the second output end is connected with the QSPI level conversion module.
9. The multiplex control circuit of claim 1, wherein, The controller integrates a full programmable system on chip, including a first processor and a second processor. The first processor has IIC bus protocol pins. The second processor has six QSPI bus protocol pins.
10. An image signal generator, characterized by The multiplexing control circuit of the multi-bus signal includes any one of claims 1 to 9.