Video image storage system

Abstract

The utility model relates to a video image storage system in the field of video image storage, which comprises an image acquisition unit, a programmable logic processing unit and a storage unit, the programmable logic processing unit is electrically connected with the image acquisition unit and the storage unit, the image acquisition unit is used for synchronously acquiring at least two paths of video image data, and the storage unit is used for storing the at least two paths of video image data. The programmable logic processing unit is used for processing at least two paths of video image data in parallel, the storage unit is used for storing the video image data processed by the programmable logic processing unit, and the programmable logic processing unit comprises a JFM7VX690T80 chip. Through cooperative work of the image acquisition unit and the JFM7VX690T80 chip, by utilizing the parallel processing capability of the chip, the acquisition efficiency of video image data is improved, and efficient acquisition of multi-channel video image data is realized; meanwhile, the JFM7VX690T80 chip is a domestic chip, so that the dependence on foreign chips is broken, and the key technology can be autonomously controlled.

Description

Technical Field

[0001] This application relates to the field of video image storage, and more particularly to a video image storage system. Background Technology

[0002] In the field of video image storage, traditional video image storage systems mostly rely on general-purpose processors to process and store data. However, with the increasing number of multi-channel video image application scenarios, this approach has exposed many problems. General-purpose processor architecture is not suitable for high-speed parallel data processing. When processing multiple video images, data acquisition and processing delays are significant. In scenarios with extremely high real-time requirements, such as security monitoring and industrial inspection, critical video footage is easily lost or stuttered. Utility Model Content

[0003] To address the aforementioned technical problems, this application provides a video image storage system.

[0004] This application provides a video image storage system, including:

[0005] An image acquisition unit is used to simultaneously acquire at least two channels of video image data;

[0006] A programmable logic processing unit, electrically connected to the image acquisition unit, is used to process the at least two channels of video image data in parallel. The programmable logic processing unit includes a JFM7VX690T80 chip.

[0007] The storage unit is electrically connected to the programmable logic processing unit and is used to store video image data processed by the programmable logic.

[0008] Optionally, the JFM7VX690T80 chip includes:

[0009] An encryption module, electrically connected to the image acquisition unit, is used to encrypt the acquired video image data.

[0010] Optionally, the encryption module includes an Advanced Encryption Standard (AES) encryption module.

[0011] Optionally, the video image storage system further includes:

[0012] At least two image acquisition interfaces are provided for connecting to different types of image sources.

[0013] Optionally, the image acquisition interface includes at least one of an SDI image acquisition interface, an HDMI image acquisition interface, and a Cameralink image acquisition interface.

[0014] Optionally, the image acquisition unit includes:

[0015] At least two image acquisition chips are electrically connected to the corresponding image acquisition interface for receiving video image data.

[0016] Optionally, the image acquisition unit further includes:

[0017] A signal conditioning circuit is electrically connected to the image acquisition chip, and the signal conditioning circuit is used to process the signal output by the image acquisition chip;

[0018] The buffer module is electrically connected to the signal conditioning circuit and is used to temporarily store the acquired video image data.

[0019] Optionally, the JFM7VX690T80 chip also includes:

[0020] An image acquisition control module is electrically connected to the cache module and the encryption module; the image acquisition control module is used to control the reading of the video image data.

[0021] Optionally, the JFM7VX690T80 chip also includes:

[0022] The storage control module is electrically connected to the encryption module and the storage unit; the storage control module is used to interact with the storage unit.

[0023] Optionally, the storage unit includes a non-volatile hard disk drive, and the video image storage system further includes:

[0024] A high-speed serial computer expansion bus storage interface is electrically connected to the programmable logic processing unit and is used to connect to the non-volatile hard disk.

[0025] The technical solution provided in this application has the following advantages compared with the prior art:

[0026] The video image storage system provided in this application includes an image acquisition unit, a programmable logic processing unit, and a storage unit. The image acquisition unit is electrically connected to the programmable logic processing unit, and the programmable logic processing unit is electrically connected to the storage unit. The image acquisition unit is used to synchronously acquire at least two channels of video image data, and the programmable logic processing unit is used to process at least two channels of video image data in parallel. The programmable logic processing unit includes a JFM7VX690T80 chip, and the storage unit is used to store the video image data processed by the programmable logic processing unit. With this configuration, the image acquisition unit and the JFM7VX690T80 chip work together, utilizing the parallel processing capability of the JFM7VX690T80 chip to improve the acquisition efficiency of video image data, achieving efficient acquisition of multiple channels of video image data. This meets the needs of simultaneous acquisition of multiple video channels in scenarios such as large-scale monitoring systems and multi-camera video recording. Furthermore, the JFM7VX690T80 chip is a domestically produced chip, breaking the dependence on foreign chips and facilitating the independent control of key technologies. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a video image storage system provided in an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of another video image storage system provided in an embodiment of this application;

[0031] Figure 3 A schematic diagram of the structure of another video image storage system provided in this application embodiment;

[0032] Figure 4 A schematic diagram of the structure of another video image storage system provided in this application embodiment;

[0033] Figure 5 A schematic diagram of the structure of another video image storage system provided in this application embodiment;

[0034] Figure 6 This is a schematic diagram of the structure of another video image storage system provided in an embodiment of this application.

[0035] The components include: 1. Image acquisition module; 11. Image acquisition chip; 111. SDI image acquisition chip; 112. HDMI image acquisition chip; 113. Camera Link image acquisition chip; 12. Signal conditioning circuit; 13. Buffer module; 2. Programmable logic processing unit; 20. JFM7VX690T80 chip; 21. Encryption module; 211. Advanced Encryption Standard (AES) encryption module; 22. Image acquisition control module; 23. Storage control module; 231. NVMe storage control module; 3. Storage module; 31. Non-volatile memory (NVMe) hard disk; 4. Image acquisition interface; 41. SDI image acquisition interface; 42. HDMI image acquisition interface; 43. Camera Link image acquisition interface; 5. Storage interface; 51. High-speed serial computer expansion bus (PCIe) storage interface; 100. Video image acquisition module; 200. Image source. Detailed Implementation

[0036] To better understand the above-mentioned objectives, features, and advantages of this application, the solution of this application will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0037] Many specific details are set forth in the following description in order to provide a full understanding of this application, but this application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of this application, and not all embodiments.

[0038] The video image storage system provided in the embodiments of this application will be described exemplarily below with reference to the accompanying drawings.

[0039] In some embodiments, such as Figure 1 The diagram shown is a structural schematic of a video image storage system provided in an embodiment of this application. (Refer to...) Figure 1 The video image storage system 100 includes: an image acquisition unit 1, a programmable gate array (FPGA) processing unit 2, and a storage unit 3. The image acquisition unit 1 is electrically connected to the FPGA processing unit 2, and the FPGA processing unit 2 is electrically connected to the storage unit 3.

[0040] The image acquisition unit 1 is used to simultaneously acquire at least two channels of video image data and transmit the acquired video image data to the programmable logic processing unit 2.

[0041] The programmable logic processing unit 2 is the core of the video image storage system 100. It processes the acquired video image data, such as through encryption. The programmable logic processing unit 2 has parallel processing capabilities, enabling it to process at least two video image data streams in parallel. This improves the efficiency of video image data acquisition and allows for the efficient acquisition of multiple video image data streams, meeting the needs of scenarios such as large-scale monitoring systems and multi-camera video recording for simultaneous acquisition of multiple video streams.

[0042] The programmable logic processing unit 2 includes a JFM7VX690T802 chip 20. The image acquisition unit 1 works in conjunction with the JFM7VX690T802 chip 20. The image acquisition unit 1 transmits the acquired video image data to the JFM7VX690T802 chip 20 in a serial or parallel manner. The JFM7VX690T802 chip 20 acquires and buffers multiple channels of video image data through its internal logic circuitry.

[0043] The JFM7VX690T802 chip is an integrated circuit chip with a large number of pins on its surface. It integrates a wealth of logic gates, look-up tables (LUTs), and flip-flops, which are connected by internal wiring to form a complex logic structure.

[0044] The JFM7VX690T802 chip is a domestically produced chip, breaking the dependence on foreign chips and facilitating independent control of key technologies. This not only reduces the risks posed by external technological restrictions but also supports the development of related domestic industries. In the context of a complex and volatile international situation, it is of great significance for safeguarding national information security and promoting the development of the domestic chip industry and video image processing technology.

[0045] Storage unit 3 is used to store video image data processed by programmable logic processing unit 2. When receiving data sent by programmable logic processing unit 2, storage unit 3 stores the data in flash memory chip; when programmable logic processing unit 2 requests to read data, storage unit 3 reads the data from flash memory chip and sends it to programmable logic processing unit 2.

[0046] The type of storage unit 3 is not limited in this application embodiment. All types of storage devices or storage apparatuses known to those skilled in the art can be used, such as hard disks, solid-state drives, memory and optical disks, and are not limited herein.

[0047] The video image storage system 100 provided in this application embodiment includes: an image acquisition unit 1, a programmable logic processing unit 2, and a storage unit 3. The image acquisition unit 1 is electrically connected to the programmable logic processing unit 2, and the programmable logic processing unit 2 is electrically connected to the storage unit 3. The image acquisition unit 1 is used to synchronously acquire at least two channels of video image data, and the programmable logic processing unit 2 is used to process at least two channels of video image data in parallel. The programmable logic processing unit 2 includes a JFM7VX690T80 chip 20. The storage unit 3 is used to store the video image data processed by the programmable logic processing unit 2. With this configuration, the image acquisition unit 1 and the JFM7VX690T80 chip 20 work together, utilizing the parallel processing capability of the JFM7VX690T80 chip 20 to improve the acquisition efficiency of video image data, achieving efficient acquisition of multiple channels of video image data, and meeting the needs of simultaneous acquisition of multiple video channels in scenarios such as large-scale monitoring systems and multi-camera video recording. At the same time, the JFM7VX690T80 chip 20 is a domestically produced chip, breaking the dependence on foreign chips and facilitating the independent control of key technologies.

[0048] In some embodiments, such as Figure 2 As shown, in the video data storage system 100, the JFM7VX690T80 chip 20 includes an encryption module 21, which is electrically connected to the image acquisition unit 1. The encryption module 21 is used to encrypt the acquired video image data, thereby ensuring the security of the video image data.

[0049] In this embodiment, the encryption algorithm of the encryption module 21 is not limited, including all encryption modules known to those skilled in the art, such as the Advanced Encryption Standard (AES), Data Encryption Algorithm (DEA), and Rivest Cipher 4 (RC4) symmetric encryption algorithms, as well as the RSA encryption algorithm and Digital Signature Algorithm (DSA) asymmetric encryption algorithms.

[0050] In some embodiments, such as Figure 6 As shown, encryption module 21 includes Advanced Encryption Standard (AES) encryption module 211.

[0051] The AES encryption module 211 is composed of the internal logic circuit of the FM7VX690T80 chip 20. The logic structure of the AES encryption algorithm is implemented through programming and exists in the FM7VX690T80 chip 20 in a logical form.

[0052] The programmable logic processing unit 2 divides the acquired video image data into groups according to the AES algorithm's block length, and then performs encryption operations on each data group using a key. The encryption process includes operations such as byte substitution, row shifting, column obfuscation, and round key addition. After multiple rounds of operations, ciphertext data is generated.

[0053] In this embodiment, the AES encryption module 211 encrypts video image data based on the AES encryption algorithm. Compared to simple encryption methods or no encryption measures in related technologies, it can effectively resist various network attacks and data theft, preventing video image data from being stolen or tampered with during storage and transmission, thus providing a solid guarantee for the security of video image data during storage and transmission. Especially in fields with extremely high data security requirements, it greatly reduces the risk of data leakage and ensures the confidentiality and integrity of video content.

[0054] In some embodiments, such as Figure 3 As shown, the video image storage system 100 also includes at least two image acquisition interfaces 4, which are used to connect to image sources 200 of different types.

[0055] With this configuration, the video image storage system 100 can be directly compatible with various types of image source interfaces, which greatly improves the system's adaptability to different video devices compared to traditional single-interface video image storage systems.

[0056] In some embodiments, such as Figure 3 As shown, in the video image storage system 100, the image acquisition interface 4 includes at least one of the following: SDI image acquisition interface 41, HDMI image acquisition interface 42, and Camera Link image acquisition interface 43.

[0057] For example, such as Figure 3 As shown, the SDI image acquisition interface 41 is used to connect to an SDI image source, the HDMI image acquisition interface 42 is used to connect to an HDMI image source, and the Camera Link image acquisition interface 43 is used to connect to a Camera Link image source.

[0058] In some embodiments, such as Figure 4 As shown, the image acquisition unit 1 includes at least two image acquisition chips 11, which are electrically connected to the corresponding image acquisition interface 4. The image acquisition chip 11 is used to receive video image data.

[0059] The image acquisition chip 11 is connected to the external image source 200 through the corresponding image acquisition interface 4. The image acquisition chip 11 is configured to convert the external video image signal into an electrical signal suitable for transmission inside the circuit board according to the interface protocol of the corresponding image acquisition interface 4, and transmit the electrical signal to the FM7VX690T80 chip 20.

[0060] For example, such as Figure 4 As shown, the image acquisition chip 11 includes: an SDI image acquisition chip 111, an HDMI image acquisition chip 112, and a Camera Link image acquisition chip 113. The SDI image acquisition chip 111 is electrically connected to the SDI image acquisition interface 41, the HDMI image acquisition chip 112 is electrically connected to the HDMI image acquisition interface 42, and the Camera Link image acquisition chip 113 is electrically connected to the Camera Link image acquisition interface 43.

[0061] The image acquisition chip 11 is an integrated circuit chip with pins covering its surface. The pin definitions and arrangements of different image acquisition chips 11 vary depending on their corresponding interface protocols. For example, the pin layout of the SDI image acquisition chip 111 is specifically designed for transmitting serial digital video signals, while the HDMI image acquisition chip 112 has pin designs for high-definition multimedia signal transmission. This configuration enables compatibility between different image acquisition interfaces 4 and the internal circuitry of the system, ensuring that video image signals can be accurately input into the system, providing raw data for subsequent processing.

[0062] In some embodiments, the image acquisition chip 11 is located on the internal circuit board of the system near the image acquisition interface 4, which facilitates wiring and connection.

[0063] In some embodiments, such as Figure 4 As shown, the image acquisition unit 1 also includes a signal conditioning circuit 12, which is electrically connected to the image acquisition chip 11. The signal conditioning circuit 12 is used to process the signal output by the image acquisition chip 11, remove noise and interference from the signal, improve signal quality, avoid data loss or errors due to signal problems, and improve the accuracy of video image acquisition.

[0064] The signal conditioning circuit 12 includes at least one of resistors, capacitors, and inductors, which are connected by lines on a circuit board to form a specific circuit structure. Utilizing the characteristics of components such as resistors, capacitors, and inductors, the signal output from the image acquisition chip 11 is processed through filtering, amplification, and level conversion.

[0065] It should be noted that, Figure 4The SDI image acquisition interface 41, HDMI image acquisition interface 42, and Camera Link image acquisition interface 43 are shown as examples, all electrically connected to the same signal conditioning circuit 12, but this does not constitute a limitation on the video image storage system provided in the embodiments of this application. In other embodiments, the image acquisition unit 1 includes at least two signal conditioning circuits 12, and the SDI image acquisition interface 41, HDMI image acquisition interface 42, and Camera Link image acquisition interface 43 are electrically connected to at least one of the signal conditioning circuits 12, which is not limited here.

[0066] In some embodiments, the signal conditioning circuit 12 is located close to the image acquisition chip 11, which facilitates timely processing of the signal output by the image acquisition chip 11.

[0067] In some embodiments, such as Figure 4 As shown, the image acquisition unit 1 also includes a buffer module 13, which is electrically connected to the signal conditioning circuit 12. The buffer module 13 is used to temporarily store the acquired video image data, waiting for the programmable logic processing unit 2 to read it.

[0068] In some embodiments, such as Figure 5 As shown, the JFM7VX690T80 chip 20 also includes an image acquisition control module 22, which is electrically connected to the cache module 13 and the encryption module 21 respectively; the image acquisition control module 22 is used to control the reading of video image data.

[0069] The image acquisition control module 22 is composed of logic circuits inside the JFM7VX690T80 chip 20. It implements specific control logic through programming, has no specific physical shape, and exists in the form of a logical structure inside the JFM7VX690T80 chip 20.

[0070] The image acquisition control module 22 is configured to send read commands to the cache module 13 according to the preset acquisition strategy and timing, coordinate the data acquisition order and rhythm of different image acquisition chips 11, realize the synchronous acquisition of multiple video image data, and ensure that multiple video image data can be acquired in an orderly and accurate manner into the JFM7VX690T80 chip 20, providing stable data input for subsequent processing.

[0071] In some embodiments, such as Figure 5 As shown, the JFM7VX690T80 chip 20 also includes a storage control module 23, which is electrically connected to the encryption module 21 and the storage unit 3 respectively; the storage control module 23 is used to interact with the storage unit 3.

[0072] The storage control module 23 is composed of the internal logic circuit of the JFM7VX690T80 chip 20. It implements control logic that conforms to the storage protocol through programming and exists in the JFM7VX690T80 chip 20 in logical form.

[0073] The storage control module 23 is configured to: package the encrypted video data into data packets that conform to the storage protocol according to the interface timing and data format specified in the storage protocol, send them to the storage unit 3, and process the response signals from the storage unit 3.

[0074] This configuration enables data interaction control between the JFM7VX690T80 chip 20 and the storage unit 3, ensuring that the encrypted video image data can be stored quickly and accurately in the storage unit 3, while also efficiently reading data from the storage unit 3.

[0075] In some embodiments, the storage control module 23 is located near the pin area connected to the storage unit 3.

[0076] In some embodiments, such as Figure 3 As shown, the video image storage system 100 also includes a storage interface 5, which is used to connect to the storage unit 3.

[0077] In some embodiments, such as Figure 3 As shown, in the video image storage system 100, the storage unit 3 includes a non-volatile storage hard disk (i.e., NVMe hard disk) 31, and the storage interface 5 includes a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe) storage interface 51. The PCIe storage interface 51 is electrically connected to the programmable logic processing unit 2 and is used to connect the NVMe hard disk 31.

[0078] For example, such as Figure 6 As shown, the NVMe hard drive 31 is electrically connected to the NVMe storage control module 231 of the programmable logic processing unit 2 via the PCIe storage interface 51 to achieve data transmission. The NVMe hard drive 31 is based on flash memory storage technology and uses the main control chip to interact with the programmable logic processing unit 2 according to the NVMe protocol. When it receives video image data sent by the programmable logic processing unit 2, it stores the video image data in the flash memory chip; when it receives a read request command sent by the programmable logic processing unit 2, it reads the relevant data from the flash memory chip and sends it to the programmable logic processing unit 2.

[0079] In this embodiment, an NVMe hard drive 31 is used as the storage unit 3, and it is connected to the programmable logic processing unit 2 through a PCIe storage interface 51. Based on the high-speed PCIe storage interface 51, the NVMe hard drive 31 has write and read speeds far exceeding those of traditional hard drives. This high-speed storage method solves the speed bottleneck problem that traditional storage methods encounter when dealing with large amounts of video data, enabling encrypted video data to be quickly stored in the NVMe hard drive 31. Simultaneously, it can respond quickly when video data needs to be retrieved, greatly improving the storage and retrieval performance of the entire system and providing strong support for the efficient management and use of video image data.

[0080] For example, such as Figure 6As shown, in this video image storage system 100, the image acquisition unit 1 includes an image acquisition chip 11 and a signal conditioning circuit 12. The image acquisition chip 11 includes an SDI image acquisition chip 111, an HDMI image acquisition chip 112, and a camera. The image acquisition chip 113 and the programmable logic processing unit 2 include a JFM7VX690T80 chip 20, which includes an image acquisition control module 22, an AES encryption module 211, and an NVMe storage control module 231. The storage unit 3 includes an NVMe hard drive 31. The SDI image acquisition chip 111, the HDMI image acquisition chip 112, and the Cameralink image acquisition chip 113 are connected to the corresponding image acquisition interface 4 via lines on the circuit board and are electrically connected to the signal conditioning circuit 12. The signal conditioning circuit 12 is electrically connected to the image acquisition control module 22, which is electrically connected to the AES encryption module 211. The AES encryption module 211 is electrically connected to the NVMe storage control module 231, which is electrically connected to the PCIe storage interface 51. The image acquisition interface 4 is used to connect to the image source 200, and the PCIe storage interface 51 is used to connect to the NVMe hard drive 31. Image acquisition chip 11 converts external video image signals into electrical signals suitable for internal system transmission according to its respective interface protocol, achieving compatibility between different video source interfaces and internal system circuits. Signal conditioning circuit 12 performs filtering, amplification, and level conversion on the signal output by image acquisition chip 11 to remove noise and interference and improve signal quality. Image acquisition control module 22 sends read commands to buffer module according to preset acquisition strategy and timing, coordinating the data acquisition order and rhythm of different image acquisition units 11 to achieve synchronous acquisition of multiple video data. AES encryption module 211 performs byte substitution, row shifting, column obfuscation, and round key addition on the input video image data according to the steps of the AES encryption algorithm, and encrypts the data using a preset key. NVMe storage control module 231 is configured to: package the encrypted video image data into data packets conforming to the NVMe protocol according to the interface timing and data format specified by the NVMe protocol, send them to NVMe hard disk 31, and process the response signals from NVMe hard disk 31. The NVMe hard drive 31 is based on flash memory storage technology. It uses the main controller chip to interact with the JFM7VX690T80 chip 20 according to the NVMe protocol. When it receives video image data sent by the JFM7VX690T80 chip 20, it stores the video image data in the flash memory chip. When it receives a request to read from the JFM7VX690T80 chip 20, it reads the relevant data from the flash memory chip and sends it to the JFM7VX690T80 chip 20.

[0081] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0082] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A video image storage system characterized by comprising: The application relates to a video image storage system. The application comprises: An image acquisition unit for synchronously acquiring at least two channels of video image data; A programmable logic processing unit electrically connected with the image acquisition unit and used for parallel processing of the at least two channels of video image data, wherein the programmable logic processing unit comprises a JFM7VX690T80 chip; 2. The video image storage system of claim 1, wherein, A storage unit electrically connected with the programmable logic processing unit and used for storing video image data processed by the programmable logic processing unit. The JFM7VX690T80 chip comprises:

3. The video image storage system of claim 2, wherein, An encryption module electrically connected with the image acquisition unit and used for encrypting the acquired video image data.

4. The video image storage system of claim 2, wherein, The encryption module comprises an advanced encryption standard encryption module. The application further comprises:

5. The video image storage system of claim 4, wherein, At least two image acquisition interfaces used for connecting with different types of image sources.

6. The video image storage system according to claim 4 or 5, characterized by The image acquisition interfaces comprise at least one of an SDI image acquisition interface, an HDMI image acquisition interface and a Camer link image acquisition interface. The image acquisition unit comprises:

7. The video image storage system of claim 6, wherein, At least two image acquisition chips electrically connected with the corresponding image acquisition interfaces and used for receiving video image data. The image acquisition unit further comprises: A signal conditioning circuit electrically connected with the image acquisition chips, wherein the signal conditioning circuit is used for processing signals output by the image acquisition chips; 8. The video image storage system of claim 7, wherein, A cache module electrically connected with the signal conditioning circuit, wherein the cache module is used for temporarily storing the acquired video image data. The JFM7VX690T80 chip further comprises:

9. The video image storage system of claim 2, wherein, An image acquisition control module electrically connected with the cache module and the encryption module, wherein the image acquisition control module is used for controlling reading of the video image data. The JFM7VX690T80 chip further comprises:

10. The video image storage system of claim 1, wherein, A storage control module electrically connected with the encryption module and the storage unit, wherein the storage control module is used for data interaction with the storage unit. The storage unit comprises a non-volatile storage hard disk, and the video image storage system further comprises: A high-speed serial computer expansion bus storage interface electrically connected with the programmable logic processing unit and used for connecting the non-volatile storage hard disk.

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