Multiplexing digital sampler circuit
By using a multiplexed digital sampler circuit, synchronous analog-to-digital conversion of multiple signal sources is achieved, solving the problems of high cost, large area, and high power consumption in existing technologies, and improving the accuracy and efficiency of chip testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2026-03-13
AI Technical Summary
In existing testing equipment, each signal source's test channel is configured with an independent pre-conditioning circuit and analog-to-digital converter, resulting in problems such as high cost, large PCB area, and high power consumption.
A multiplexed digital sampler circuit is adopted. By setting a sample-and-hold circuit in the digital sampler sub-circuit corresponding to each signal source, and controlling all sample-and-hold circuits by the same pulse signal generator, combined with a multiplexer and analog-to-digital converter circuit, synchronous analog-to-digital conversion of multiple signal sources is achieved.
This reduces the number of analog-to-digital converters and their peripheral circuits, lowers PCB footprint and power consumption, reduces costs, and improves the accuracy of chip test results.
Smart Images
Figure CN223993673U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to automated testing techniques, and in particular to a multiplexed digital sampler circuit. Background Technology
[0002] During the testing of chips such as Liquid Crystal Display (LCD) chips and Organic Light-Emitting Diode Display (OLED) chips, the testing machine needs to simultaneously acquire medium-voltage analog test signals from a large number of pins, which requires a digital sampler (Digitizer) function.
[0003] To implement the digitizer function, current test equipment typically configures an independent pre-conditioning circuit and analog-to-digital converter for each signal source's test channel. However, this approach has problems such as high cost, large footprint on printed circuit boards (PCBs), and high power consumption. Utility Model Content
[0004] This disclosure provides a multiplexed digital sampler circuit that can reduce the number of analog-to-digital converters and their peripheral circuits in the digital sampler circuit, thereby reducing the PCB footprint and circuit power consumption.
[0005] One aspect of this disclosure provides a multiplexed digital sampler circuit, including at least two digital sampler sub-circuits, wherein the at least two digital sampler sub-circuits are respectively connected to different signal sources, and each digital sampler sub-circuit is provided with a sample-and-hold circuit;
[0006] The sample-and-hold circuits in the at least two digital sampler sub-circuits are connected to the same pulse signal generator. The sample-and-hold circuits are used to sample and hold the output level of the signal source corresponding to the digital sampler sub-circuit when a pulse signal is received.
[0007] The output terminals of the at least two digital sampler sub-circuits are connected to the input terminals of the multiplexer, and the digital sampler sub-circuits are used to transmit the sampling level to the multiplexer after the pulse signal ends;
[0008] The output of the multiplexer is connected to the analog-to-digital converter circuit. The multiplexer is used to transmit the sampling level of each digital sampler sub-circuit to the analog-to-digital converter circuit in a preset order.
[0009] Optionally, the sample-and-hold circuit includes a sampling switch, a first buffer, and a capacitor. One end of the sampling switch is connected to the signal source, and the other end of the sampling switch is connected to the first buffer and the capacitor. The output of the first buffer is connected to the multiplexer.
[0010] The sampling switch is configured to close when the pulse signal is received and to open when the pulse signal ends;
[0011] The first buffer is configured to cut off the current when the sampling switch is closed so that the capacitor samples and holds the output level of the signal source, and to transmit the sampled level to the multiplexer after the sampling switch is open.
[0012] Optionally, a second buffer is provided between the pulse signal generator and the sampling switch;
[0013] The second buffer is used to generate a drive current to drive the sampling switch to close when the pulse signal is received, and to stop generating the drive current when the pulse signal ends, so as to open the sampling switch.
[0014] Optionally, the signal period of the pulse signal is greater than the polling period of the multiplexer, where the polling period is the duration for the multiplexer to sequentially transmit the sampling levels of all digital sampler sub-circuits to the analog-to-digital conversion circuit.
[0015] Optionally, an instrumentation amplifier circuit is provided between the signal source and the sample-and-hold circuit corresponding to each digital sampler sub-circuit. The instrumentation amplifier circuit is used to adjust the amplitude and buffer the received level signal.
[0016] Optionally, the instrument amplifier circuit includes a first instrument amplifier and a second instrument amplifier;
[0017] The input terminal of the first instrumentation amplifier is connected to the output terminal of the signal source, and is used to adjust the amplitude and buffer the effective level of the signal source;
[0018] The input terminal of the second instrumentation amplifier is connected to the ground terminal of the signal source, and is used to adjust the amplitude and buffer the signal at the zero point level of the signal source;
[0019] The output level of the instrument amplifier circuit is the amplification level corresponding to the difference between the effective level and the zero-point level.
[0020] Optionally, a low-pass filter circuit is provided between the multiplexer and the sample-and-hold circuit corresponding to each digital sampler sub-circuit. The low-pass filter circuit is used to smooth the received level signal.
[0021] Based on the embodiments of this disclosure, for signal sources that require simultaneous acquisition of output levels and analog-to-digital conversion, a sample-and-hold circuit is set in the digital sampler sub-circuit corresponding to each signal source, and each sample-and-hold circuit is connected to the same pulse signal generator. The pulse signal generator can control all sample-and-hold circuits to simultaneously sample and hold the output level of the signal source, and transmit the sampled level to the multiplexer after the pulse signal ends. The analog-to-digital converter can sequentially perform analog-to-digital conversion on the sampled levels of each digital sampler sub-circuit through the multiplexer, thereby achieving the effect of synchronous analog-to-digital conversion of signals from multiple signal sources through a single analog-to-digital converter. This can reduce the number of analog-to-digital converters and their peripheral circuits in the digital sampler circuit of the test machine, reduce the power consumption and PCB area occupied by the digital sampler circuit, thereby reducing costs. Furthermore, due to the reduction in the number and density of analog-to-digital converters and their peripheral circuits, crosstalk between channels can be reduced, improving the accuracy of chip test results.
[0022] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0023] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0024] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:
[0025] Figure 1 A schematic diagram of the structure of a multiplexed digital sampler circuit provided in an exemplary embodiment of this disclosure;
[0026] Figure 2 A schematic diagram of the sample-and-hold circuit provided in an exemplary embodiment of this disclosure;
[0027] Figure 3 A schematic diagram of the sample-and-hold circuit provided as another exemplary embodiment of this disclosure;
[0028] Figure 4 A schematic diagram of the structure of a multiplexed digital sampler circuit provided for another exemplary embodiment of this disclosure.
[0029] The attached figures are labeled as follows:
[0030] Signal source-1; Digital sampler sub-circuit-2; Pulse signal generator-3; Multiplexer-4; Analog-to-digital converter circuit-5;
[0031] Sample and hold circuit-21; Instrumentation amplifier circuit-22; Low-pass filter circuit-23; Second buffer-31;
[0032] Sampling switch-211; First buffer-212; Capacitor-213; First instrumentation amplifier-221; Second instrumentation amplifier-222. Detailed Implementation
[0033] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.
[0034] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.
[0035] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.
[0036] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.
[0037] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.
[0038] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.
[0039] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.
[0040] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.
[0041] Technologies and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies and equipment should be considered part of the specification.
[0042] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.
[0043] Figure 1 This is a structural block diagram of a multiplexed digital sampler circuit provided in an exemplary embodiment of this disclosure. For example... Figure 1 As shown, the multiplexed digital sampler circuit includes at least two digital sampler sub-circuits 2, which are respectively connected to different signal sources 1, and each digital sampler sub-circuit 2 is provided with a sample-and-hold circuit 21. Figure 1 Only one multiplexed digital sampler circuit including two digital sampler sub-circuits 2 is shown. In actual application scenarios, more digital sampler sub-circuits 2 can be set according to actual needs.
[0044] At least two sample-and-hold circuits 21 in the digital sampler sub-circuit 2 are connected to the same pulse signal generator 3. The sample-and-hold circuit 21 is used to sample and hold the output level of the signal source 1 corresponding to the digital sampler sub-circuit 2 when a pulse signal (Trig signal) is received. The pulse signal generator 3 can be any type of signal generator that supports the generation of triangular waves. The pulse signal can be a triangular wave (Trig) signal, a pulse width modulation (PWM) signal, a sawtooth wave pulse signal, etc. This embodiment of the disclosure does not limit the type of pulse signal generator 3 or the type of pulse signal.
[0045] Optionally, the sample-and-hold circuits 21 in all digital sampler sub-circuits 2 are connected to the same pulse signal generator 3. Alternatively, when there are many digital sampler sub-circuits 2, the sample-and-hold circuits 21 of every n digital sampler sub-circuits 2 can be connected to the same pulse signal generator 3, and all pulse signal generators 3 synchronously send pulse signals of the same frequency so that all sample-and-hold circuits 21 synchronously sample and hold the level signal. The pulse signal generator 3 can also be replaced with a pulse signal generator or other device that can drive the sample-and-hold circuits 21.
[0046] At least two digital sampler sub-circuits 2 have their outputs connected to the inputs of multiplexer 4. The digital sampler sub-circuits 2 transmit the sampled level to multiplexer 4 after the pulse signal ends. The output of multiplexer 4 is connected to analog-to-digital converter 5. Multiplexer 4 transmits the sampled levels of each digital sampler sub-circuit 2 to analog-to-digital converter 5 sequentially according to a preset order. Multiplexer 4 can be any type of multiplexer, and this embodiment does not limit the type of multiplexer 4.
[0047] Multiplexer 4 can receive multiple input signals and select one of them to output to a single output line according to the control signal. Therefore, by controlling the signal selection frequency and order of multiplexer 4, the sampling levels of multiple digital sampler sub-circuits 2 can be sequentially input into analog-to-digital converter circuit 5, thereby enabling analog-to-digital converter circuit 5 to sequentially output digital signals from multiple signal sources 1. Multiplexer 4 can fully utilize the capacity of the communication channel, reduce system cost, and simultaneously sample and hold the level signals of the corresponding signal sources 1 at the same time using sample-and-hold circuit 21, achieving the effect of outputting level signals generated by multiple signal sources 1 at the same time through a single output path of multiplexer 4.
[0048] Based on the embodiments of this disclosure, for signal sources that require simultaneous acquisition of output levels and analog-to-digital conversion, a sample-and-hold circuit is set in the digital sampler sub-circuit corresponding to each signal source, and each sample-and-hold circuit is connected to the same pulse signal generator. The pulse signal generator can control all sample-and-hold circuits to simultaneously sample and hold the output level of the signal source, and transmit the sampled level to the multiplexer after the pulse signal ends. The analog-to-digital converter can sequentially perform analog-to-digital conversion on the sampled levels of each digital sampler sub-circuit through the multiplexer, thereby achieving the effect of synchronous analog-to-digital conversion of signals from multiple signal sources through a single analog-to-digital converter. This can reduce the number of analog-to-digital converters and their peripheral circuits in the digital sampler circuit of the test machine, reduce the power consumption and PCB area occupied by the digital sampler circuit, thereby reducing costs. Furthermore, due to the reduction in the number and density of analog-to-digital converters and their peripheral circuits, crosstalk between channels can be reduced, improving the accuracy of chip test results.
[0049] In one possible implementation, such as Figure 2 As shown, the sample-and-hold circuit 21 includes a sampling switch 211, a first buffer 212, and a capacitor 213. One end of the sampling switch 211 is connected to the signal source 1, and the other end is connected to the first buffer 212 and the capacitor 213. The output of the first buffer 212 is connected to the multiplexer 4. The sampling switch 211 can be directly connected to the signal source 1, or it can be connected to the signal source 1 through an amplifier or other device to receive the amplitude-adjusted output level. The first buffer 212 can be directly connected to the multiplexer 4, or it can be connected to the multiplexer 4 through a filter or other device, thereby achieving smoothing of the sampling level.
[0050] The sampling switch 211 is used to close when a pulse signal is received and to open when the pulse signal ends. Optionally, the sampling switch 211 is connected to the pulse signal generator 3 and its state is switched under the control of the pulse signal.
[0051] The buffer 212 (hereinafter referred to as the first buffer 212) in the sample-and-hold circuit 21 is used to cut off the current so that the capacitor 213 samples and holds the output level of the signal source 1 when the sampling switch 211 is closed, and to transmit the sampled level to the multiplexer 4 after the sampling switch 211 is open. Figure 2 As shown, when the sampling switch 211 is closed, the current output by the signal source 1 can be transmitted to the sample-and-hold circuit 21. At this time, the first buffer 212 can impede the current, while the capacitor 213 is grounded, thereby charging the capacitor 213 to achieve sample-and-hold. When the sampling switch 211 is open, the current output by the signal source 1 no longer flows into the sample-and-hold circuit 21. At this time, the multiplexer 4 can collect the output level of the capacitor 213, that is, the sampling level.
[0052] In one possible implementation, such as Figure 3 As shown, a buffer 31 (hereinafter referred to as the second buffer 31) is provided between the pulse signal generator 3 and the sampling switch 211. The second buffer 31 is used to generate a drive current to drive the sampling switch 211 to close when a pulse signal is received, and to stop generating the drive current when the pulse signal ends, so that the sampling switch 211 is opened.
[0053] The sampling switch 211 can be any type of single-pole single-throw switch, but some types require a strong signal for control. If this type of sampling switch 211 is directly connected to the pulse signal generator 3, the pulse signal generator 3 needs to generate a strong pulse signal, which can easily interfere with other devices in the multiplexed digital sampler circuit. Therefore, by setting a second buffer 31 between the pulse signal generator 3 and the sampling switch 211, the pulse signal generated by the pulse signal generator 3 triggers the second buffer 31 to generate a corresponding drive current, driving the sampling switch 211 to close, which can reduce interference to other devices.
[0054] In one possible implementation, the signal period of the pulse signal is greater than the polling period of the multiplexer 4, which is the duration for the multiplexer 4 to sequentially transmit the sampled levels of all digital sampler sub-circuits 2 to the analog-to-digital converter circuit 5. By controlling the polling period of the multiplexer 4 to be less than the signal period of the pulse signal, it can be ensured that the analog-to-digital converter circuit 5 can receive the sampled levels of all digital sampler sub-circuits 2 and perform analog-to-digital conversion.
[0055] In one possible implementation, such as Figure 4As shown, an instrumentation amplifier circuit 22 is provided between the signal source 1 and the sample-and-hold circuit 21 corresponding to each digital sampler sub-circuit 2. The instrumentation amplifier circuit 22 is used to adjust the amplitude and buffer the received level signal. Optionally, the instrumentation amplifier circuit 22 can amplify the received level signal, add DC bias, etc., to ensure that the level signal is at a suitable operating point. In addition, the instrumentation amplifier circuit 22 can also provide impedance conversion of the level signal from the signal source 1 to the digital sampler sub-circuit 2, preventing the signal source 1 from being affected by the current or voltage that may be applied by the digital sampler sub-circuit 2.
[0056] Specifically, when the analog-to-digital converter circuit 5 needs to perform analog-to-digital conversion on the voltage difference between the two ends of the signal source 1, such as... Figure 4 As shown, the instrumentation amplifier circuit 22 includes at least two instrumentation amplifiers, including a first instrumentation amplifier 221 and a second instrumentation amplifier 222. The input terminal of the first instrumentation amplifier 221 is connected to the output terminal of the signal source 1, and it is used to adjust the amplitude and buffer the signal at the effective level of the signal source 1. The input terminal of the second instrumentation amplifier 222 is connected to the ground terminal of the signal source 1, and it is used to adjust the amplitude and buffer the signal at the zero-point level of the signal source 1. The output level of the instrumentation amplifier circuit 22 is the amplified level corresponding to the difference between the effective level and the zero-point level. The first instrumentation amplifier 221 and the second instrumentation amplifier 222 can be, for example, differential amplifiers, three-op-amp instrumentation amplifiers, etc. This embodiment does not limit the type of the first instrumentation amplifier 221 and the second instrumentation amplifier 222.
[0057] In one possible implementation, a low-pass filter circuit 23 is provided between the multiplexer 4 and the sample-and-hold circuit 21 corresponding to each digital sampler sub-circuit 2. The low-pass filter circuit 23 can be used to smooth the received level signal.
[0058] The low-pass filter circuit 23 can filter out high-frequency noise signals in the level signal. In particular, the noise generated when the sampling switch 211 in the sample-and-hold circuit 21 is frequently turned on and off can cause glitches in its output level signal. Therefore, the low-pass filter circuit 23 can smooth the sampling level, thereby further improving the signal-to-noise ratio of the channel and thus improving the accuracy of the chip test results.
[0059] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.
[0060] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or corresponding parts between embodiments can be referred to interchangeably. The basic principles of this disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of the various embodiments of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the specific details required for its implementation.
[0061] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0062] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.
[0063] The apparatus and device of this disclosure may be implemented in many ways. For example, the apparatus and device of this disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware.
[0064] It should also be noted that in the apparatus and equipment disclosed herein, the components or steps can be disassembled and / or recombined. Such disassembly and / or recombination should be considered as equivalent solutions to this disclosure.
[0065] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.
[0066] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, adjustments, additions, and sub-combinations thereof.
Claims
1. A multiplexed digital sampler circuit, comprising: The at least two digital sampler sub-circuits are respectively connected with different signal sources, and a sample-and-hold circuit is arranged in each digital sampler sub-circuit; The sample-and-hold circuits in the at least two digital sampler sub-circuits are connected with the same pulse signal generator, and the sample-and-hold circuits are used to sample and hold the output level of the signal source corresponding to the digital sampler sub-circuit when the pulse signal is received; The output ends of the at least two digital sampler sub-circuits are connected with the input end of a multiplexer, and the digital sampler sub-circuits are used to transmit the sample level to the multiplexer after the pulse signal ends; The output end of the multiplexer is connected with an analog-to-digital conversion circuit, and the multiplexer is used to transmit the sample level of each digital sampler sub-circuit to the analog-to-digital conversion circuit in a preset order.
2. The multiplexed digital sampler circuit of claim 1, wherein, The sample-and-hold circuit is provided with a sampling switch, a first buffer and a capacitor, one end of the sampling switch is connected with the signal source, the other end of the sampling switch is connected with the first buffer and the capacitor, and the output end of the first buffer is connected with the multiplexer; The sampling switch is used to close when the pulse signal is received, and is used to open when the pulse signal ends; The first buffer is used to cut off the current to make the capacitor sample and hold the output level of the signal source when the sampling switch is in the closed state, and is used to transmit the sample level to the multiplexer after the sampling switch is opened.
3. The multiplexed digital sampler circuit of claim 2, wherein, A second buffer is arranged between the pulse signal generator and the sampling switch; The second buffer is used to generate a driving current to drive the sampling switch to close when the pulse signal is received, and is used to stop generating the driving current to make the sampling switch open when the pulse signal ends.
4. The multiplexed digital sampler circuit of any of claims 1 to 3, wherein, The signal period of the pulse signal is greater than the polling period of the multiplexer, and the polling period is the time length for the multiplexer to transmit the sample level of all digital sampler sub-circuits to the analog-to-digital conversion circuit in turn.
5. The multiplexed digital sampler circuit of any of claims 1 to 3, wherein, An instrument amplification circuit is arranged between the signal source corresponding to each digital sampler sub-circuit and the sample-and-hold circuit, and the instrument amplification circuit is used to adjust the amplitude and buffer the signal of the received level signal.
6. The multiplexed digital sampler circuit of claim 5, wherein, The instrument amplification circuit is provided with a first instrument amplifier and a second instrument amplifier; The input end of the first instrument amplifier is connected with the output end of the signal source, and is used to adjust the amplitude and buffer the signal of the effective level of the signal source; The input end of the second instrument amplifier is connected with the ground end of the signal source, and is used to adjust the amplitude and buffer the signal of the zero point level of the signal source; The output level of the instrument amplification circuit is an amplified level corresponding to the difference between the effective level and the zero point level.
7. The multiplexed digital sampler circuit of any of claims 1 to 3, wherein, A low-pass filter circuit is arranged between the multiplexer and the sample-and-hold circuit corresponding to each digital sampler sub-circuit, and the low-pass filter circuit is used to perform smoothing processing on the received level signal.