Receive front-end amplifier, signal amplification method and network device

Abstract

The embodiment of the present application provides a receiving front-end amplifier, a signal amplification method and network equipment. The receiving front-end amplifier comprises: a current mode logic unit, which is used for converting a first single-ended input signal into a differential signal according to a reference voltage generated by the receiving front-end amplifier locally; a negative capacitance unit, which is used for expanding the bandwidth of the differential signal; and a conversion unit, which is used for converting the differential signal with the expanded bandwidth into a second single-ended signal and outputting the second single-ended signal. Through the embodiment of the present application, based on the current mode logic, the negative capacitance and the differential-to-single-ended three-stage circuit design, the problems of insufficient bandwidth, signal quality decline and excessive power consumption when the single-ended signal is input can be solved effectively, and the performance of high-speed signal processing is enhanced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of communications, and more specifically, to a receiving front-end amplifier, a signal amplification method, and a network device. Background Technology

[0002] The increased computing power driven by Artificial Intelligence (AI) and Machine Learning (ML) has led to a greater demand for chip integration using 2.5D or 3D packaging. 2.5D or 3D packaging technologies enable higher chip integration densities.

[0003] Chip-to-chip integration not only enhances the chip's computing power but also improves the overall system performance and efficiency by shortening signal transmission paths. This is particularly beneficial in scenarios requiring the processing of large amounts of data and high-speed computation, such as AI model training and complex data analysis.

[0004] However, achieving chip integration for high-speed applications such as 32GHz and 64GHz still faces significant technical challenges. Particularly in the design of receiver amplifiers (RX AMPs), related technologies struggle to simultaneously guarantee signal bandwidth, signal quality, and power consumption control in single-ended signal input scenarios, a problem that urgently needs to be solved. Traditional amplifier technologies are typically designed around differential signals, and their performance, power consumption, and latency cannot fully meet the stringent requirements of high-speed applications. Therefore, existing RX AMPs urgently need to possess the following key characteristics: the ability to handle single-ended signal input to simplify circuit design and reduce system complexity; low power consumption to ensure long-term operation and high efficiency; a small footprint to accommodate high-density integration packaging requirements; and low latency, which is crucial for ensuring the real-time performance of high-speed data transmission. Summary of the Invention

[0005] This invention provides a receiving front-end amplifier, a signal amplification method, and a network device to at least solve the problem in related technologies that it is impossible to guarantee the bandwidth, signal quality, and power consumption control of a signal in a single-ended signal input scenario.

[0006] According to an embodiment of the present invention, a receiver front-end amplifier is provided, comprising: a current-mode logic unit for converting a first single-ended input signal into a differential signal based on a reference voltage locally generated by the receiver front-end amplifier; a negative capacitor unit for extending the bandwidth of the differential signal; and a conversion unit for converting the bandwidth-extended differential signal into a second single-ended signal and outputting the second single-ended signal.

[0007] According to another embodiment of the present invention, a signal amplification method is provided, applied to the receiving front-end amplifier in the above embodiment, comprising: converting a first single-ended input signal into a differential signal according to a reference voltage locally generated by the receiving front-end amplifier; expanding the bandwidth of the differential signal; converting the bandwidth-expanded differential signal into a second single-ended signal, and outputting the second single-ended signal.

[0008] According to yet another embodiment of the present invention, a network device is also provided, including the receiver front-end amplifier in the above embodiments.

[0009] Through the above embodiments of the present invention, based on current-mode logic, negative capacitors, and a three-stage differential-to-single-ended circuit design, the problems of insufficient bandwidth, signal quality degradation, and excessive power consumption during single-ended signal input can be effectively solved, thereby enhancing the performance of high-speed signal processing. Attached Figure Description

[0010] Figure 1 This is a structural block diagram of a receiving front-end amplifier according to an embodiment of the present invention; Figure 2 This is a structural block diagram of a receiving front-end amplifier according to another embodiment of the present invention; Figure 3 This is a schematic diagram of the internal circuit structure of the CML unit according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the internal circuit structure of the NC unit according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the internal circuit structure of the conversion unit according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the internal circuit structure of the bandwidth extension unit according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the internal circuit structure of the receiving front-end amplifier according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the internal circuit structure of the receiving front-end amplifier according to another embodiment of the present invention; Figure 9 This is a schematic flowchart of a signal amplification method according to an embodiment of the present invention. Detailed Implementation

[0011] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings and examples.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0013] The Universal Chiplet Interconnect Express (UCIe) standard standardizes and specifies high-speed interconnects between chips, ensuring that chips from different vendors can work together seamlessly, enabling modular chip design and manufacturing.

[0014] Specifically, the UCIe standard sets several key technical metrics, including bandwidth density, energy efficiency, and latency, to meet the needs of next-generation high-performance computing systems. These metrics require that chiplet interconnects not only be able to carry high-bandwidth data transmission but also operate with extremely low power consumption while maintaining low latency in signal transmission to ensure the overall system's communication efficiency and energy efficiency.

[0015] In achieving high-speed data transmission using the UCIe protocol, the receiver front-end amplifier (RX AMP) plays a crucial role as the first step in signal processing. However, traditional amplifier technology suffers from the following problems when dealing with single-ended high-speed signal processing: 1. Many existing amplifier designs are primarily designed for differential signals and are not very effective at processing single-ended signals, especially in high-speed transmission scenarios where signal distortion and noise are particularly prominent.

[0016] 2. Traditional amplifiers increase bandwidth and reduce latency, but this comes at the cost of significantly increased power consumption, which contradicts the low power consumption target required by the UCIe standard.

[0017] 3. In high-density packaging environments, the physical size of the amplifier is critical to the overall chip design. Related technologies cannot simultaneously meet performance requirements and maintain an extremely small circuit area.

[0018] 4. Under different operating conditions (such as temperature and voltage changes), the performance of existing amplifiers fluctuates greatly, which is not conducive to stable data transmission.

[0019] This invention proposes a receiving front-end amplifier, which is specially designed to handle single-ended signal input scenarios and can simultaneously meet multiple requirements such as high signal bandwidth, high signal quality, and low power consumption.

[0020] Figure 1 This is a structural block diagram of the receiving front-end amplifier according to an embodiment of the present invention, such as... Figure 1 As shown, the receiver front-end amplifier includes: a current mode logic (CML) unit 11, a negative capacitor (NC) unit 12, and a conversion unit 13.

[0021] CML unit 11 is used to convert the first single-ended input signal into a differential signal based on the reference voltage generated locally by the receiving front-end amplifier. NC unit 12 is used to extend the bandwidth of the differential signal; Conversion unit 13, namely the differential signal to single-ended signal (D2S) unit, is used to convert the bandwidth-extended differential signal into a second single-ended signal and output the second single-ended signal.

[0022] Figure 2 This is a structural block diagram of a receiving front-end amplifier according to another embodiment of the present invention, such as... Figure 2 As shown, the receiving front-end amplifier, in addition to Figure 1 In addition to the units shown, a bandwidth expansion unit 14 is also included.

[0023] The bandwidth extension unit 14 is used to receive the second single-ended signal output by the conversion unit and extend the bandwidth of the second single-ended signal.

[0024] In one embodiment, the differential signal output by CML unit 11 includes a first positive phase signal V. p and the first negative phase signal V n The CML unit is also used to determine the reference voltage V. ref The first single-ended input signal V in It is converted into a current signal, and then the current signal is converted into the first positive phase signal V. p and the first negative phase signal V n .

[0025] Figure 3 This is a schematic diagram of the internal circuit structure of the CML unit according to an embodiment of the present invention, such as... Figure 3 As shown, in order to expand the frequency response range, i.e. bandwidth, of the signal processed by the CML unit 11, the CML unit 11 is provided with: a first field-effect transistor M1, a second field-effect transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first inductor L1, and a second inductor L2, so as to achieve bandwidth expansion through inductor peaking technology and source-level decay technology.

[0026] In this embodiment, the inductance peaking technique, that is, in the high-frequency band, by adding a first inductor L1 and a second inductor L2 to the circuit, can improve the gain of the circuit, compensate for the high-frequency attenuation caused by parasitic capacitance and other factors, and thus increase the bandwidth of the circuit.

[0027] Source-level degradation technology, which involves introducing a first resistor R1, a second resistor R2, a third resistor R3, and a first capacitor C1, can stabilize the operating point of the amplifier while reducing the low-frequency gain of the signal in exchange for higher high-frequency gain and wider bandwidth.

[0028] By combining inductor peak technology and source-level decay technology, the CML unit 11 can more effectively transmit and amplify signals when processing high-speed signals (such as 32GHz / 64GHz signals), thereby meeting the stringent requirements of the UCIE protocol.

[0029] In one embodiment, a first resistor R1 and a first inductor L1 are connected in series on the drain of a first field-effect transistor M1; a second resistor R2 and a second inductor L2 are connected in series on the drain of a second field-effect transistor M2; a third resistor R3 and a first capacitor C1 are connected in parallel to form a parallel branch, and the two ends of the parallel branch are respectively connected to the source of the first field-effect transistor M1 and the source of the second field-effect transistor M2.

[0030] Figure 4 This is a schematic diagram of the internal circuit structure of the NC unit according to an embodiment of the present invention, such as... Figure 4 As shown, the NC unit 12 includes a negative capacitor module, a third inductor L3, and a fourth inductor L4; the first end of the negative capacitor module is connected to the output path of the first positive phase signal, and the second end of the negative capacitor module is connected to the output path of the first negative phase signal; the third inductor L3 is connected in series in the output path of the first positive phase signal, and the fourth inductor L4 is connected in series in the output path of the first negative phase signal.

[0031] In this embodiment, the negative capacitor module is used to interact with V p Path or V n Positive capacitance in the path ( Figure 4 (not shown in the diagram) connected in parallel to extend V p and V n The bandwidth.

[0032] Specifically, in the signal path of a circuit, capacitors are usually connected in parallel with resistors to form an RC network, which limits the high-frequency response of the circuit. By configuring negative capacitor modules in parallel, the effect of these positive capacitors C can be canceled or reduced.

[0033] Components such as transistors and transmission lines exhibit positive capacitance at high frequencies, which can lead to signal delay and bandwidth limitation. Negative capacitance modules, through their negative capacitance characteristics, can compensate for these positive capacitances, reducing signal delay and improving the high-frequency response of the signal.

[0034] The negative capacitor module can also reduce the total capacitance on the signal path, increase the circuit bandwidth, and ensure V p and V n It can maintain good transmission quality and amplification effect over a wider frequency range.

[0035] In this embodiment, the third inductor L3 and the fourth inductor L4 are respectively connected to the two output terminals of the CML unit 11, and are used to adjust the V output of the negative capacitor module through inductance peaking technology. p or V n Further bandwidth expansion will be carried out.

[0036] Figure 5 This is a schematic diagram of the internal circuit structure of the conversion unit according to an embodiment of the present invention, such as... Figure 5 As shown, the conversion unit 13 includes a differential amplifier for converting the received first positive phase signal V. p and the first negative phase signal V n Signal amplification is performed. The first positive phase signal V... p and the first negative phase signal V n It has undergone bandwidth expansion processing by NC unit 12.

[0037] like Figure 5 As shown, the differential amplifier includes: eleventh field-effect transistor M7 and twelfth field-effect transistor M8.

[0038] In one embodiment, the first output terminal of CML unit 11 is connected to the gate of the eleventh field-effect transistor M7, and the second output terminal of CML unit is connected to the gate of the twelfth field-effect transistor M8; the first output terminal of CML unit is used to output a first positive phase signal, and the second output terminal of CML unit is used to output a first negative phase signal.

[0039] In one embodiment, such as Figure 5 As shown, the conversion unit 13 also includes a second adjustable resistor R4, a first adjustable resistor R5, an eighth field-effect transistor M3, a seventh field-effect transistor M4, a sixth field-effect transistor M5, and a fifth field-effect transistor M6.

[0040] In one embodiment, such as Figure 5 As shown, the first end of the first adjustable resistor R5 is connected to the common node of the gate of the fifth field-effect transistor M6 and the drain of the sixth field-effect transistor M5, and the second end of the first adjustable resistor R5 is connected to the gate of the sixth field-effect transistor M5; the first end of the second adjustable resistor is connected to the gate of the seventh field-effect transistor M4, and the second end of the second adjustable resistor is connected to the common node of the drain of the seventh field-effect transistor M4 and the gate of the eighth field-effect transistor M3; the source of the fifth field-effect transistor M6 is grounded, and the drain of the fifth field-effect transistor M6 is used to output the second single-ended signal; the source of the sixth field-effect transistor M5 is grounded, the source of the seventh field-effect transistor M4 is grounded, the drain of the eighth field-effect transistor M3 is connected to other field-effect transistors, and the source of the eighth field-effect transistor M3 is grounded.

[0041] In one embodiment, the conversion unit 13 is further configured to combine the amplified first positive phase signal and the first negative phase signal to convert them into a second single-ended signal.

[0042] Figure 6 This is a schematic diagram of the internal circuit structure of the bandwidth extension unit according to an embodiment of the present invention, such as... Figure 6 As shown, the bandwidth expansion unit 14 includes: an uplink resistor module R 11 Downlink resistor module R 12 Ninth field-effect transistor M9 and tenth field-effect transistor M 10 .

[0043] like Figure 6 As shown, the upstream resistor module R 11 The first terminal is connected to the output terminal of the conversion unit, and the upstream resistor module R 11 The second terminal is connected to the gate of the ninth field-effect transistor M9; the downstream resistor module R 12 The first end is connected to the output end of the conversion unit 13, and the downstream resistor module R 12 The second end is connected to the tenth field-effect transistor M. 10 The gate.

[0044] In one embodiment, the ninth field-effect transistor M9 can be a PMOS transistor, and the tenth field-effect transistor M... 10 It can be an NMOS transistor. Uplink resistor module R 11 Downlink resistor module R 12 Ninth field-effect transistor M9 and tenth field-effect transistor M 10 This forms a bandwidth-enhancing unit, used to further extend the bandwidth of the second single-ended signal.

[0045] Figure 7 This is a schematic diagram of the internal circuit structure of the receiver front-end amplifier according to an embodiment of the present invention, such as... Figure 7 As shown, the receiving front-end amplifier includes: CML unit 11 is used to convert the first single-ended input signal into a differential signal based on the reference voltage generated locally by the receiving front-end amplifier. NC unit 12 is used to extend the bandwidth of the differential signal; The conversion unit 13 is used to convert the bandwidth-extended differential signal into a second single-ended signal and output the second single-ended signal. The bandwidth extension unit 14 is used to receive the second single-ended signal output by the conversion unit and extend the bandwidth of the second single-ended signal.

[0046] The CML unit 11 includes: a first field-effect transistor M1, a second field-effect transistor M2, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a first inductor L1, and a second inductor L2.

[0047] The first resistor R1 and the first inductor L1 are connected in series on the drain of the first field-effect transistor M1; the second resistor R2 and the second inductor L2 are connected in series on the drain of the second field-effect transistor M2; the third resistor R3 and the first capacitor C1 are connected in parallel to form a parallel branch, and the two ends of the parallel branch are respectively connected to the source of the first field-effect transistor M1 and the source of the second field-effect transistor M2.

[0048] The NC unit 12 includes a negative capacitor module, a third inductor L3, and a fourth inductor L4; the first end of the negative capacitor module is connected to the output path of the first positive phase signal, and the second end of the negative capacitor module is connected to the output path of the first negative phase signal; the third inductor L3 is connected in series in the output path of the first positive phase signal, and the fourth inductor L4 is connected in series in the output path of the first negative phase signal.

[0049] The conversion unit 13 includes an eighth field-effect transistor M3, a seventh field-effect transistor M4, a second adjustable resistor R4, a first adjustable resistor R5, a sixth field-effect transistor M5, a fifth field-effect transistor M6, an eleventh field-effect transistor M7, and a twelfth field-effect transistor M8.

[0050] The first output terminal of CML unit 11 is connected to the gate of the eleventh field-effect transistor M7, and the second output terminal of CML unit is connected to the gate of the twelfth field-effect transistor M8; the first terminal of the first adjustable resistor R5 is connected to the common node of the gate of the fifth field-effect transistor M6 and the drain of the sixth field-effect transistor M5, and the second terminal of the first adjustable resistor R5 is connected to the gate of the sixth field-effect transistor M5; the first terminal of the second adjustable resistor is connected to the gate of the seventh field-effect transistor M4, and the second terminal of the second adjustable resistor is connected to the common node of the drain of the seventh field-effect transistor M4 and the gate of the eighth field-effect transistor M3; the source of the fifth field-effect transistor M6 is grounded, and the drain of the fifth field-effect transistor M6 is used to output the second single-ended signal; the source of the sixth field-effect transistor M5 is grounded; the source of the seventh field-effect transistor M4 is grounded; the drain of the eighth field-effect transistor M3 is connected to other field-effect transistors, and the source of the eighth field-effect transistor M3 is grounded.

[0051] Bandwidth expansion unit 14 includes: uplink resistor module R 11 Downlink resistor module R 12 Ninth field-effect transistor M9 and tenth field-effect transistor M 10 .

[0052] Uplink resistor module R 11 The first terminal is connected to the output terminal of the conversion unit, and the upstream resistor module R 11 The second terminal is connected to the gate of the ninth field-effect transistor M9; the downstream resistor module R 12 The first end is connected to the output end of the conversion unit 13, and the downstream resistor module R 12 The second end is connected to the tenth field-effect transistor M. 10The gate.

[0053] Figure 8 This is a schematic diagram of the internal circuit structure of the receiver front-end amplifier according to another embodiment of the present invention, as shown below. Figure 8 As shown, with Figure 7 Unlike the receiver front-end amplifier shown, in this embodiment, the NC unit 12 includes a negative capacitor module. The first end of the capacitor module is connected to the output path of the first positive phase signal, and the second end of the negative capacitor module is connected to the output path of the first negative phase signal.

[0054] This invention also provides a signal amplification method, which can be applied to the receiving front-end amplifier in any of the above embodiments. Figure 9 This is a schematic flowchart of a signal amplification method according to an embodiment of the present invention, as shown below. Figure 9 As shown, the method includes the following steps: Step S901: Convert the first single-ended input signal into a differential signal based on the reference voltage generated locally by the receiving front-end amplifier. Step S902: Expand the bandwidth of the differential signal; Step S903: Convert the bandwidth-extended differential signal into a second single-ended signal and output the second single-ended signal.

[0055] In one embodiment, the differential signal includes a first positive phase signal and a first negative phase signal; converting the first single-ended input signal into a differential signal based on a reference voltage locally generated by the receiving front-end amplifier includes: converting the first single-ended input signal into a current signal based on the reference voltage; and converting the current signal into a first positive phase signal and a first negative phase signal.

[0056] In one embodiment, converting a bandwidth-extended differential signal into a second single-ended signal includes: amplifying the received first positive-phase signal and first negative-phase signal; and combining the amplified first positive-phase signal and first negative-phase signal to obtain a second single-ended signal.

[0057] This invention also provides a network device that includes the receiver front-end amplifier described in any of the above embodiments.

[0058] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0059] It is obvious to those skilled in the art that the modules or steps of the present invention described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those described herein, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the present invention is not limited to any particular combination of hardware and software.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A receiving front-end amplifier, characterized in that, include: A current-mode logic (CML) unit is used to convert a first single-ended input signal into a differential signal based on a reference voltage locally generated by the receiving front-end amplifier; wherein the differential signal includes a first positive phase signal and a first negative phase signal. A negative capacitor NC unit is provided to extend the bandwidth of the differential signal; wherein the negative capacitor NC unit includes a negative capacitor module, a third inductor, and a fourth inductor; the first terminal of the negative capacitor module is connected to the output path of the first positive phase signal, and the second terminal of the negative capacitor module is connected to the output path of the first negative phase signal; the third inductor is connected in series in the output path of the first positive phase signal, and the fourth inductor is connected in series in the output path of the first negative phase signal; A conversion unit is used to convert the bandwidth-extended differential signal into a second single-ended signal and output the second single-ended signal.

2. The receiving front-end amplifier according to claim 1, characterized in that, The current-mode logic (CML) unit is further configured to convert the first single-ended input signal into a current signal based on the reference voltage, and then convert the current signal into the first positive phase signal and the first negative phase signal.

3. The receiving front-end amplifier according to claim 1, characterized in that, The current-mode logic (CML) unit includes: a first field-effect transistor, a second field-effect transistor, a first resistor, a second resistor, a third resistor, a first capacitor, a first inductor, and a second inductor.

4. The receiving front-end amplifier according to claim 3, characterized in that, in, The first resistor and the first inductor are connected in series across the drain of the first field-effect transistor; the second resistor and the second inductor are connected in series across the drain of the second field-effect transistor; the third resistor and the first capacitor are connected in parallel to form a parallel branch, the two ends of the parallel branch are respectively connected to the source of the first field-effect transistor and the source of the second field-effect transistor, the gate of the first field-effect transistor is used to input the first single-ended input signal, and the gate of the second field-effect transistor is used to output the reference voltage.

5. The receiving front-end amplifier according to claim 2, characterized in that, The conversion unit includes a differential amplifier for amplifying the received first positive phase signal and the first negative phase signal.

6. The receiving front-end amplifier according to claim 5, characterized in that, in, The differential amplifier includes a third field-effect transistor and a fourth field-effect transistor.

7. The receiving front-end amplifier according to claim 6, characterized in that, in, The first output terminal of the current-mode logic CML unit is connected to the gate of the third field-effect transistor, and the second output terminal of the current-mode logic CML unit is connected to the gate of the fourth field-effect transistor. The first output terminal of the current-mode logic (CML) unit is used to output the first positive phase signal, and the second output terminal of the current-mode logic (CML) unit is used to output the first negative phase signal.

8. The receiving front-end amplifier according to claim 7, characterized in that, in, The conversion unit further includes a first adjustable resistor, a second adjustable resistor, a fifth field-effect transistor, a sixth field-effect transistor, a seventh field-effect transistor, and an eighth field-effect transistor.

9. The receiving front-end amplifier according to claim 8, characterized in that, in, The first end of the first adjustable resistor is connected to the common node of the gate of the fifth field-effect transistor and the drain of the sixth field-effect transistor, and the second end of the first adjustable resistor is connected to the gate of the sixth field-effect transistor. The first end of the second adjustable resistor is connected to the gate of the seventh field-effect transistor, and the second end of the second adjustable resistor is connected to the common node of the drain of the seventh field-effect transistor and the gate of the eighth field-effect transistor. The source of the fifth field-effect transistor is grounded, and the drain of the fifth field-effect transistor is used to output the second single-ended signal. The source of the sixth field-effect transistor is grounded, the source of the seventh field-effect transistor is grounded, the drain of the eighth field-effect transistor is connected to a field-effect transistor connected to the power supply, and the source of the eighth field-effect transistor is grounded.

10. The receiving front-end amplifier according to claim 5, characterized in that, The conversion unit is further configured to combine the amplified first positive phase signal and the first negative phase signal to convert them into the second single-ended signal.

11. The receiving front-end amplifier according to claim 1, characterized in that, Also includes: A bandwidth extension unit is used to receive the second single-ended signal output by the conversion unit and extend the bandwidth of the second single-ended signal.

12. The receiving front-end amplifier according to claim 11, characterized in that, The bandwidth extension unit includes: an uplink resistor module, a downlink resistor module, a ninth field-effect transistor, and a tenth field-effect transistor.

13. The receiving front-end amplifier according to claim 12, characterized in that, in, The first end of the uplink resistor module is connected to the output end of the conversion unit, the second end of the uplink resistor module is connected to the gate of the ninth field-effect transistor, the source of the ninth field-effect transistor is connected to the power supply, the drain of the ninth field-effect transistor is connected to the drain of the tenth field-effect transistor, the first end of the downlink resistor module is connected to the output end of the conversion unit, the second end of the downlink resistor module is connected to the gate of the tenth field-effect transistor, and the source of the tenth field-effect transistor is grounded.

14. A signal amplification method, characterized in that, The receiver front-end amplifier described in any one of claims 1-13 comprises: Based on the reference voltage generated locally by the receiving front-end amplifier, the first single-ended input signal is converted into a differential signal; Extend the bandwidth of the differential signal; The bandwidth-extended differential signal is converted into a second single-ended signal, and the second single-ended signal is output.

15. The method according to claim 14, characterized in that, in, The differential signal includes a first positive phase signal and a first negative phase signal; based on the reference voltage locally generated by the receiving front-end amplifier, the first single-ended input signal is converted into a differential signal, including: Based on the reference voltage, the first single-ended input signal is converted into a current signal; The current signal is converted into the first positive phase signal and the first negative phase signal.

16. The method according to claim 15, characterized in that, Converting the bandwidth-extended differential signal into a second single-ended signal includes: The received first positive phase signal and the first negative phase signal are amplified; The amplified first positive phase signal and the first negative phase signal are combined to obtain the second single-ended signal.

17. A network device, characterized in that, Includes the receiving front-end amplifier as described in any one of claims 1-13.

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