Linear voltage regulator system based on low power supply rejection ratio

Abstract

The utility model discloses a linear voltage regulator system based on a low power supply rejection ratio, which belongs to the field of voltage regulators and comprises a primary power supply, a secondary power supply and an LDO (Low Dropout Regulator). The primary power supply is connected with one end of the resistor R, the other end of the resistor R is simultaneously connected with a drain electrode and a grid electrode of the MOS tube Q1, a source electrode of the MOS tube Q1 is connected with the secondary power supply, and the secondary power supply is connected with the LDO. According to the utility model, high-voltage input can be supported, the power supply rejection ratio is relatively high, the power supply rejection ratio of the system is remarkably improved through the collaborative design of the primary power supply, the secondary power supply and the LDO module, and the influence of power supply noise on output voltage is reduced. And low-noise voltage can be stably output. The circuit is compact in structure, easy to implement and maintain and suitable for various application scenes. The high-precision voltage stabilizing circuit is high in voltage stabilizing precision, high-precision voltage stabilizing is achieved through the LDO module, and the application requirement for sensitivity to power noise is met.

Description

Technical Field

[0001] This utility model relates to a linear voltage regulator system based on a low power supply rejection ratio. Background Technology

[0002] A voltage regulator is an electronic device primarily used to convert unstable input voltages into stable output voltages. This ensures that electronic equipment operates within its normal operating range, protects it from voltage fluctuations, and improves equipment performance and system stability. Voltage regulators provide a stable voltage output during power supply fluctuations or power failures, preventing damage to equipment and electronic components from voltage changes. Many electronic devices and systems have extremely high requirements for voltage stability. By providing a stable voltage output, voltage regulators ensure that electronic components and circuits operate within their normal operating range, avoiding problems such as unstable operation, performance degradation, or data loss. Voltage regulators can filter out noise and interference in the power supply, providing a high-quality power supply, thereby improving the signal quality, anti-interference capability, and operating efficiency of equipment. This is particularly important for precision equipment such as communication equipment and medical instruments. By stabilizing the output voltage, voltage regulators enable electronic equipment to operate within its optimal voltage range, reducing energy waste, improving energy efficiency, and thus reducing energy consumption and carbon dioxide emissions. Voltage regulators can reduce damage to equipment caused by voltage fluctuations, extend equipment lifespan, and reduce maintenance and replacement costs. The filters and suppression devices inside a voltage regulator can reduce output voltage ripple and electromagnetic radiation, preventing interference to other equipment and improving the system's anti-interference capability. Voltage regulators are widely used in communication equipment, medical equipment, industrial automation, optoelectronic equipment, scientific research experiments, and other fields to ensure that these devices can operate normally under voltage fluctuations or unstable power grid conditions.

[0003] However, traditional LDOs suffer from a low power supply rejection ratio (PSRR) under high-voltage input conditions, resulting in insufficient power supply noise suppression and affecting system stability and performance. Utility Model Content

[0004] To address the aforementioned problems in the prior art, the purpose of this invention is to provide a linear regulator system based on a low power supply rejection ratio, thereby solving the problems mentioned in the background art.

[0005] To achieve the above objectives, this utility model provides the following technical solution:

[0006] The linear regulator system based on low power supply rejection ratio includes a primary power supply, a secondary power supply, and an LDO; the primary power supply is connected to one end of a resistor R, the other end of the resistor R is connected to both the drain and gate of a MOSFET Q1, the source of the MOSFET Q1 is connected to the secondary power supply, and the secondary power supply is connected to the LDO.

[0007] As a further embodiment of this invention: the LDO includes an error amplifier U1, a MOS transistor M1, a resistor R1, and a resistor R2.

[0008] As a further aspect of this invention: the source of the MOS transistor M1 in the LDO is connected to the secondary power supply.

[0009] As a further embodiment of this invention: the gate of the MOS transistor M1 in the LDO is connected to the output terminal of the error amplifier U1.

[0010] As a further embodiment of this invention: the drain of the MOS transistor M1 in the LDO is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the positive input terminal of the error amplifier U1.

[0011] As a further embodiment of this invention: the negative input terminal of the error amplifier U1 in the LDO is connected to the reference power supply Vref.

[0012] As a further embodiment of this invention: the positive input terminal of the error amplifier U1 in the LDO is connected to one end of the resistor R2, and the other end of the resistor R2 is grounded.

[0013] As a further embodiment of this utility model: the LDO further includes capacitor C1, capacitor C2, capacitor C3, resistor R3, and resistor R4;

[0014] The output terminal of the error amplifier U1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

[0015] The output terminal of error amplifier U1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the secondary power supply.

[0016] The source of MOSFET M1 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the drain of MOSFET M1.

[0017] The drain of MOSFET M1 is connected to one end of capacitor C3, and the other end of capacitor C3 is grounded.

[0018] The two ends of capacitor C3 and the two ends of resistor R4 are connected in parallel.

[0019] As a further embodiment of this invention, the power supply terminal of the LDO error amplifier U1 is connected to the secondary power supply.

[0020] As a further embodiment of this invention, the grounding terminal of the LDO error amplifier U1 is grounded.

[0021] Compared with the prior art, the beneficial effects of this utility model are:

[0022] This invention features a high power supply rejection ratio (PSRR). Through the coordinated design of the primary power supply, secondary power supply, and LDO module, the PSRR of the system is significantly improved, reducing the impact of power supply noise on the output voltage. This invention supports high-voltage input and is suitable for high-voltage input scenarios, enabling stable low-noise voltage output. This invention has a simple and reliable structure, a compact circuit structure, and is easy to implement and maintain, making it suitable for various applications. This invention offers high voltage regulation accuracy, achieving high-precision voltage regulation through the LDO module, meeting the needs of applications sensitive to power supply noise. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the framework of a linear regulator system based on low power supply rejection ratio disclosed in an embodiment.

[0024] Figure 2 This is a schematic diagram of the circuit structure of a linear regulator system based on low power supply rejection ratio disclosed in an embodiment.

[0025] Figure 3 This is a schematic diagram of the internal structure of an LDO in a linear regulator system based on a low power supply rejection ratio disclosed in an embodiment. Detailed Implementation

[0026] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0027] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "equipped with," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0028] This invention proposes a linear regulator system based on low power supply rejection ratio (PSRR). Through the coordinated design of the primary power supply, secondary power supply, and LDO, the PSRR of the system is improved, and the impact of power supply noise on the system is reduced.

[0029] Please see Figure 1-3A linear regulator system based on low power supply rejection ratio includes a primary power supply, a secondary power supply, and an LDO; the primary power supply is connected to one end of a resistor R, the other end of the resistor R is connected to both the drain and gate of a MOSFET Q1, the source of the MOSFET Q1 is connected to the secondary power supply, and the secondary power supply is connected to the LDO.

[0030] The primary power supply provides the input power. The secondary power supply provides initial voltage regulation of the primary power supply's output voltage. The LDO module provides precise voltage regulation of the secondary power supply's output voltage and delivers a low-noise output voltage.

[0031] The LDO includes an error amplifier U1, a MOSFET M1, resistors R1 and R2. The source of the MOSFET M1 is connected to the secondary power supply; the gate of the MOSFET M1 is connected to the output of the error amplifier U1; the drain of the MOSFET M1 is connected to one end of the resistor R1; the other end of the resistor R1 is connected to the positive input of the error amplifier U1; and the negative input of the error amplifier U1 is connected to the reference power supply Vref.

[0032] The positive input terminal of error amplifier U1 is connected to one end of resistor R2, and the other end of resistor R2 is grounded.

[0033] The power supply terminal of the LDO error amplifier U1 is connected to the secondary power supply, and the ground terminal of the LDO error amplifier U1 is grounded.

[0034] The LDO also includes capacitors C1, C2, and C3, resistors R3 and R4;

[0035] The output terminal of the error amplifier U1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

[0036] The output terminal of error amplifier U1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the secondary power supply.

[0037] The source of MOSFET M1 is connected to one end of resistor R3, and the other end of resistor R3 is connected to the drain of MOSFET M1.

[0038] The drain of MOSFET M1 is connected to one end of capacitor C3, and the other end of capacitor C3 is grounded.

[0039] The two ends of capacitor C3 and the two ends of resistor R4 are connected in parallel;

[0040] The primary power supply, secondary power supply, and LDO are integrated into the same hardware module, saving space and reducing the chip's footprint.

[0041] The working principle of this invention is as follows: The primary power supply provides the input power, which is initially regulated by a secondary power supply composed of resistor R and MOSFET Q1 to reduce input voltage fluctuations. The output voltage of the secondary power supply serves as the input to the LDO module, and is precisely regulated through a feedback loop composed of MOSFET M1 and error amplifier U1. Error amplifier U1 adjusts the gate voltage of MOSFET M1 by comparing the reference power supply Vref with the voltage divided by resistors R1 and R2, thereby controlling the stability of the output voltage.

[0042] The power supply can be applied to the ZQ calibration circuit to provide a stable power supply for the internal oscillator, thereby making the clock signal generated by the oscillator more stable and less affected by PVT, which is beneficial to improving the stability of ZQ calibration. Simultaneously, this invention can also serve as a voltage regulator for the oscillator in the ZQ circuit of DDR5 products; previously, the power supply of the oscillator and other modules in the ZQ circuit shared the same power supply, which affected power supply stability. The power supply of this invention can better ensure the stability of the power supply within the oscillator.

[0043] By employing a collaborative design involving a primary power supply, a secondary power supply, and an LDO module, a higher power supply rejection ratio (PSRR) can be achieved. The primary and secondary power supplies provide initial voltage regulation and filtering, reducing high-frequency noise and low-frequency ripple in the input power supply. The LDO module further regulates the voltage, focusing on suppressing residual noise, thereby improving the overall PSRR of the system. The system's ability to suppress input power supply noise is significantly enhanced, making it suitable for applications sensitive to power supply noise.

[0044] By coordinating the design of the primary and secondary power supplies and the LDO module, the input voltage stress on the LDO module can be reduced. The primary and secondary power supplies gradually lower the input voltage to an intermediate voltage range suitable for LDO module operation. The LDO module only needs to handle lower input voltages, reducing voltage stress and power consumption of its internal components. This improves the efficiency and reliability of the LDO module and reduces heat generation issues.

[0045] By coordinating the design of the primary power supply, secondary power supply, and LDO module, system efficiency can be optimized. The primary and secondary power supplies share part of the voltage step-down task, reducing the input-output voltage difference of the LDO module. The LDO module operates at a lower voltage drop, resulting in significantly improved efficiency. Overall system efficiency is improved, energy loss is reduced, and it is suitable for battery-powered or low-power applications.

[0046] The coordinated design of the primary power supply, secondary power supply, and LDO module enhances system stability and reliability. The primary and secondary power supplies provide initial voltage regulation and filtering for the input voltage, reducing voltage fluctuations and noise. The LDO module operates under a stable input voltage, resulting in a more stable and reliable output. The system maintains high stability and reliability even under high-voltage input conditions, extending equipment lifespan.

[0047] By coordinating the design of the primary power supply, secondary power supply, and LDO module, the design complexity of the LDO module can be reduced. The primary and secondary power supplies handle the input processing, simplifying the LDO module design. The LDO module only needs to focus on low-noise output and high-precision voltage regulation. This reduces the design difficulty and cost of the LDO module while improving the overall system performance.

[0048] This invention can adapt to various application scenarios. The primary and secondary power supplies can be flexibly adjusted according to the input voltage range to adapt to different input conditions. The LDO module provides low-noise, high-precision output voltage, meeting the needs of applications with high power quality requirements. The system has stronger versatility and adaptability, suitable for various fields such as communication equipment, medical instruments, and industrial control.

[0049] This invention reduces output noise and ripple. The primary and secondary power supplies perform initial filtering on the input power, reducing noise and ripple. The LDO module further filters out residual noise, providing a clean output voltage. The significantly reduced output voltage noise and ripple make it suitable for applications with extremely high power quality requirements.

[0050] This invention improves the dynamic response capability of the system; the primary and secondary power supplies provide a stable intermediate voltage, reducing the impact of input voltage fluctuations on the LDO module. Under a stable input voltage, the LDO module can respond more quickly to load changes. The system's dynamic response capability is significantly improved, making it suitable for applications with frequent load changes.

[0051] This invention can reduce system costs; the primary and secondary power supplies use low-cost components to share the input workload. The LDO module can use low-voltage components, further reducing costs. The overall system cost is reduced while maintaining high performance.

[0052] This invention improves system scalability; the primary and secondary power supplies can adjust their output voltage ranges as needed. LDO modules can be selected in different specifications to meet application requirements. The system has higher scalability and can adapt to different input voltages and output requirements.

[0053] Through the synergistic action of the primary power supply, secondary power supply, and LDO module, the system achieves high power rejection ratio, low noise output, high efficiency, and high stability under input conditions. This design not only optimizes system performance but also reduces cost and design complexity, making it suitable for various applications with high power quality requirements.

[0054] This invention features a high power supply rejection ratio (PSRR). Through the coordinated design of the primary power supply, secondary power supply, and LDO module, the PSRR of the system is significantly improved, reducing the impact of power supply noise on the output voltage. This invention supports high-voltage input and is suitable for high-voltage input scenarios, enabling stable low-noise voltage output. This invention has a simple and reliable structure, a compact circuit structure, and is easy to implement and maintain, making it suitable for various applications. This invention offers high voltage regulation accuracy, achieving high-precision voltage regulation through the LDO module, meeting the needs of applications sensitive to power supply noise.

[0055] It will be apparent to those skilled in the art that this invention is not limited to the details of the exemplary embodiments described above, and that it can be implemented in other specific forms without departing from the spirit or essential characteristics of this invention. Therefore, the embodiments should be considered exemplary and not restrictive in all respects. The scope of this invention is defined by the appended claims rather than the foregoing description, and therefore all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0056] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A low power supply rejection ratio based linear voltage regulator system, characterized by, The LDO comprises an error amplifier U1, a MOS transistor M1, a resistor R1 and a resistor R2.

2. The low power supply rejection ratio based linear voltage regulator system of claim 1, wherein, The LDO comprises an error amplifier U1, a MOS transistor M1, a resistor R1 and a resistor R2.

3. The low power supply rejection ratio based linear voltage regulator system of claim 2, wherein, The source of the MOS transistor M1 in the LDO is connected with the secondary power supply.

4. The low power supply rejection ratio based linear voltage regulator system of claim 3, wherein, The gate of the MOS transistor M1 in the LDO is connected with the output terminal of the error amplifier U1.

5. The low power supply rejection ratio based linear voltage regulator system of claim 4, wherein, The drain of the MOS transistor M1 in the LDO is connected with one end of the resistor R1, and the other end of the resistor R1 is connected with the positive input terminal of the error amplifier U1.

6. The low power supply rejection ratio based linear voltage regulator system of claim 5, wherein, The negative input terminal of the error amplifier U1 in the LDO is connected with the reference power supply Vref.

7. The low power supply rejection ratio based linear voltage regulator system of claim 6, wherein, The positive input terminal of the error amplifier U1 in the LDO is connected with one end of the resistor R2, and the other end of the resistor R2 is grounded.

8. The low power supply rejection ratio based linear voltage regulator system of claim 7, wherein The LDO further comprises a capacitor C1, a capacitor C2, a capacitor C3, a resistor R3 and a resistor R4. The output terminal of the error amplifier U1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is grounded. The output terminal of the error amplifier U1 is connected with one end of the capacitor C2, and the other end of the capacitor C2 is connected with the secondary power supply. The source of the MOS transistor M1 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the drain of the MOS transistor M1. The drain of the MOS transistor M1 is connected with one end of the capacitor C3, and the other end of the capacitor C3 is grounded. The capacitor C3 and the resistor R4 are connected in parallel.

9. The low power supply rejection ratio based linear voltage regulator system of claim 8, wherein, The power supply terminal of the error amplifier U1 in the LDO is connected with the secondary power supply.

10. The low power supply rejection ratio based linear voltage regulator system of claim 9, wherein, The grounding terminal of the error amplifier U1 in the LDO is grounded.

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