Array substrate, display panel and display device
By setting up magnetic touch signal lines inside the array substrate and forming an EMR sensing coil with existing signal lines, the problems of susceptibility to interference and increased thickness caused by external EMR electrodes are solved, achieving a thin and light design and good electromagnetic touch function.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2026-03-17
AI Technical Summary
The external EMR electrodes in existing electronic paper display devices make them susceptible to external interference, increase thickness and cost, and prevent effective touch functionality.
Magnetic touch signal lines are set inside the array substrate, and an EMR sensing coil is formed using the existing signal lines. The loop coil is composed of common electrode lines and redundant signal lines to realize electromagnetic touch function.
It achieves excellent electromagnetic touch functionality in a slim and lightweight design, reducing the overall thickness and cost while ensuring the electromagnetic pen's sensing performance.
Smart Images
Figure CN224005488U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology
[0002] In existing electronic paper display devices, the electromagnetic resonance (EMR) electrodes are generally external (out-cell), meaning the electromagnetic plate is attached separately to the transistor module and is independent of the display module. Because the EMR electrodes are outside the display module, they are easily affected by external environmental interference and damage. Furthermore, external EMR electrodes increase the overall thickness of the device, hindering miniaturization and portability, and also increase overall cost. However, placing the EMR electrodes inside the display module limits space and the number of coils, making effective touch functionality impossible. Utility Model Content
[0003] To address at least one of the aforementioned problems, a first aspect of this disclosure provides an array substrate, comprising: a driving circuit layer formed on a substrate, the driving circuit layer including a plurality of thin-film transistors, and the driving circuit layer further comprising:
[0004] The first electrode is arranged in a multi-array configuration;
[0005] Multiple common electrode lines extend along a first direction and are arranged along a second direction, the common electrode lines being electrically connected to a row of first electrodes, the first direction and the second direction intersecting; and
[0006] Multiple redundant signal lines extend along the second direction and are arranged along the first direction. The redundant signal lines are electrically isolated from the common electrode line.
[0007] Multiple common electrode wires are electrically connected at one end to form multiple first-loop coils.
[0008] One end of multiple redundant signal lines is electrically connected together to form multiple second-loop coils.
[0009] One of the common electrode line and the redundant signal line is disposed on the same layer as the source and drain of the thin-film transistor, and the other is disposed on the same layer as the gate of the thin-film transistor.
[0010] Optionally, the driving circuit layer also includes:
[0011] Multiple first signal lines extend along a first direction and are arranged along a second direction;
[0012] Multiple second signal lines, extending along a second direction and arranged along a first direction; and
[0013] Multiple adapter signal lines extend along a second direction and are arranged along a first direction, with each adapter signal line electrically connected to a corresponding first signal line.
[0014] The sum of the number of signal lines between two adjacent columns of first electrodes is the same, and the signal lines include at least two of the following: second signal lines, transition signal lines, and redundant signal lines.
[0015] Optionally, the driving circuit layer includes: N first signal lines and M second signal lines.
[0016] when At that time, the number of redundant signal lines is (n+1)MN.
[0017] when At that time, the number of redundant signal lines is MN.
[0018] Where N and M are integers greater than 1, and n = 1, 2, 3, ...
[0019] Optionally, the driving circuit layer includes: a gate layer and a source / drain metal layer sequentially stacked on the substrate.
[0020] The source and drain electrodes, the second signal line, the transition signal line, and the redundant signal line are disposed in the source and drain metal layer, while the gate, the first signal line, and the common electrode line are disposed in the gate layer.
[0021] Optionally, the driving circuit layer includes: a gate layer and a source / drain metal layer sequentially stacked on the substrate.
[0022] The source and drain electrodes, the first signal line, and the common electrode line are disposed in the source and drain metal layer, while the gate, the second signal line, the transition signal line, and the redundant signal line are disposed in the gate layer.
[0023] Optionally, the drive circuit layer further includes: multiple electrode lines,
[0024] Multiple electrode lines extend along a second direction and are arranged along a first direction, and include multiple first electrode line groups arranged one-to-one with redundant signal lines, each first electrode line group including at least one electrode line.
[0025] The number of first electrode lines in each first electrode line group is equal, and the electrode lines in the same first electrode line group are connected in parallel to the same redundant signal line.
[0026] Optionally, the array substrate includes a display area and a non-display area surrounding the display area, and the driving circuit layer further includes a wiring layer disposed on the side of the source / drain metal layer away from the substrate.
[0027] The routing layer includes a first routing layer and a second routing layer surrounding the display area.
[0028] The common electrode line is electrically connected to the first trace via a via that passes through to the first trace to form a first loop coil.
[0029] The redundant signal line is electrically connected to the second trace via a via that passes through to the second trace to form a second loop coil.
[0030] Optionally, the first electrode and the common electrode line are arranged in the same layer, and the first electrode and the common electrode line are directly electrically connected, or
[0031] The first electrode and the common electrode line are located on different layers. The first electrode is electrically connected to the common electrode line via a via that extends to the common electrode line.
[0032] Optionally, one end of the multiple common electrode lines constituting different first loop coils are electrically connected together, while the other end is electrically isolated.
[0033] A second aspect of this disclosure provides a display panel including an array substrate as described above.
[0034] A third aspect of this disclosure provides a display device including a display panel as described above.
[0035] The beneficial effects of this disclosure are as follows:
[0036] This disclosure addresses existing problems by providing an array substrate, display panel, and display device. By placing magnetic touch signal lines inside the array substrate and utilizing existing signal lines within the array substrate, a thin and light design can achieve excellent electromagnetic touch functionality, which has broad application prospects. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 A schematic diagram showing the arrangement of electromagnetic touch signal lines in related technologies is provided.
[0039] Figure 2 A schematic diagram of an array substrate applying an embodiment of the present disclosure is shown;
[0040] Figure 3 A schematic diagram of an array substrate applying another embodiment of the present disclosure is shown;
[0041] Figure 4 A schematic top view of an array substrate according to an embodiment of the present disclosure is shown;
[0042] Figure 5 Show along Figure 4 A schematic cross-sectional view of the array substrate taken by line AA' in the diagram;
[0043] Figure 6 and Figure 7 A simplified view of the array substrate according to an embodiment of the present disclosure is shown;
[0044] Figure 8 A schematic top view of an array substrate according to another embodiment of the present disclosure is shown;
[0045] Figure 9 Show along Figure 8 A schematic cross-sectional view of the array substrate taken by line BB' in the diagram;
[0046] Figure 10 A schematic top view of an array substrate according to another embodiment of the present disclosure is shown;
[0047] Figure 11 Show along Figure 10 A schematic cross-sectional view of the array substrate taken by line CC' in the diagram;
[0048] Figure 12 A schematic top view of an array substrate according to another embodiment of the present disclosure is shown;
[0049] Figures 13 to 16 Show respectively Figure 2 A schematic diagram of regions C, B, E, and D in the middle;
[0050] Figure 17 A schematic timing diagram of a driving method for an array substrate according to an embodiment of the present disclosure is shown. Detailed Implementation
[0051] To more clearly illustrate this disclosure, the preferred embodiments and accompanying drawings will be used for further description. Similar components in the drawings are indicated by the same or similar reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of this disclosure.
[0052] It should be noted that the terms "having," "comprising," and "including" used in this disclosure are all open-ended, meaning that when a module is described as "having," "comprising," or "including" a first element, a second element, and / or a third element, it indicates that the module includes other elements besides the first, second, and / or third elements. Furthermore, the ordinal numbers "first," "second," and "third" used in this disclosure are not intended to define a specific order, but only to distinguish between the various parts. In this disclosure, when describing layer A and layer B as "co-located," it means that layer A and layer B are manufactured using the same materials and processes.
[0053] Figure 1 This illustrates an example scheme in the related art of arranging electromagnetic electrodes using an array substrate. From Figure 1 As can be seen, this illustrates an array substrate in an electronic paper display device. Both data and scan signals originate from a driver chip. Therefore, the array substrate includes not only Data and Gate signal lines that provide signals to transistors, but also adapter leads. In this example, scan signals from the driver chip are transmitted to X-direction Gate signal lines via Y-direction Gate leads. Furthermore, X-direction electromagnetic electrodes are additionally provided on the layer containing the Gate signal lines, and Y-direction electromagnetic electrodes are additionally provided on the layer containing the Data signal lines, to form an electromagnetic touch system using each X-direction and Y-direction electromagnetic coil.
[0054] However, since the same metal film layer as the display signal is used, the routing space will be limited. There is no space to widen the electromagnetic touch electrodes further. In order to meet the impedance requirements, the outer electromagnetic lines need to be widened, which will lead to an increase in the bezel width. This limitation is more significant, especially for display products that require adapter leads in electronic paper display devices.
[0055] To address at least one of the above problems, embodiments of this disclosure provide an array substrate, comprising: a driving circuit layer formed on a substrate, the driving circuit layer including a plurality of thin-film transistors, and the driving circuit layer further comprising:
[0056] The first electrode is arranged in a multi-array configuration;
[0057] Multiple common electrode lines extend along a first direction and are arranged along a second direction, the common electrode lines being electrically connected to a row of first electrodes, the first direction and the second direction intersecting; and
[0058] Multiple redundant signal lines extend along the second direction and are arranged along the first direction. The redundant signal lines are electrically isolated from the common electrode line.
[0059] At least a portion of the multiple common electrode lines have one end electrically connected together to form multiple first loop coils.
[0060] At least a portion of the redundant signal lines are electrically connected at one end to form multiple second-loop coils.
[0061] One of the common electrode line and the redundant signal line is disposed on the same layer as the source and drain of the thin-film transistor, and the other is disposed on the same layer as the gate of the thin-film transistor.
[0062] In this embodiment, by placing the magnetic touch signal lines inside the array substrate and utilizing the existing signal lines within the array substrate, a good electromagnetic touch function can be achieved using a thin and light design.
[0063] To understand the structural characteristics of the electromagnetic coils in the array substrate of this disclosure, we first combine... Figure 2 The connection relationships of electromagnetic coils and signal lines within the array substrate according to embodiments of this disclosure are described. To better illustrate the display module scenario using the array substrate, the figures show the bonding area D-IC electrically connected to the display driver chip D-IC and the bonding area electrically connected to the flexible circuit board FPC within the array substrate. For ease of understanding, the bonding areas are labeled with the components to be bonded, "D-IC" and "FPC".
[0064] Reference Figure 2 As shown, the array substrate includes a display area AA and a non-display area NA. The loop coil for EMR sensing includes multiple first loop coils Y1, Y2, ..., Y... m-1 and Y m and multiple second-circuit coils X1, X2, ..., X m-1 and X m In this example, each first loop coil Y1, Y2, ..., Y... m-1 and Y m and each of the second circuit coils X1, X2, ..., X m-1 and X m This disclosure includes multiple electrodes connected in parallel, but is not limited to this; a loop coil may also include only one electrode. Additionally, multiple first loop coils Y1, Y2, ..., Y... m-1 and Y m and multiple second-circuit coils X1, X2, ..., X m-1 and X m Each coil is an independent coil; that is, they are electrically connected together at one end, while the other end is electrically connected to the flexible printed circuit board (FPC) via traces in the non-display area (NA). This allows them to receive drive signals from the FPC and transmit sensing signals to the FPC. One end of the flexible printed circuit board is electrically connected to the display panel, while the other end can be electrically connected to a driver circuit board. This driver circuit board may include display driver chips and EMR sensing driver chips. The EMR sensing driver chips receive sensing signals from each loop coil to determine the magnetic touch position, thereby enabling the display of touch-written handwriting or touch-related operations on the display panel. Alternatively, the non-display area (NA) of the array substrate may also be electrically connected to a display driver chip (D-IC) to facilitate display driving.
[0065] It is understood that when an array substrate is loaded into a display panel, the display panel may include the array substrate and the display substrate disposed on the array substrate. For example, if the display panel is an electronic paper display panel, it may include the array substrate, an electronic paper film disposed on the array substrate, a PS film, and other adhesives, etc., which will not be described in detail here.
[0066] exist Figure 2 In the example, the display module uses a flexible printed circuit board (FPC) to transmit signals for driving EMR sensing and signals for display driving. However, this disclosure is not limited thereto; see also [link to relevant documentation]. Figure 3 As shown, the array substrate of this embodiment can also be applied to display modules where the flexible circuit board D-FPC for display driving and the flexible circuit board E-FPC for driving EMR sensing are set independently.
[0067] It should be noted that in the embodiments of this disclosure, the loop coil for EMR sensing is implemented using existing signal lines in the array substrate used for display. Therefore, when using independent flexible circuit boards D-FPC and E-FPC, the signal lines used for EMR sensing need to be multiplexed by transmitting signals through the flexible circuit board E-FPC for EMR sensing. Furthermore, in the embodiments of this disclosure, the relevant signal lines for transmitting scan signals and data signals remain independent signal lines and receive signals separately from the display driver chip D-IC and / or the flexible circuit board FPC (or D-FPC). Specific driving methods will be described in detail in the driving method section below and will not be repeated here.
[0068] The following is combined Figure 4 and Figure 5 An array substrate according to a specific example of this disclosure is described. Wherein, Figure 4 This example shows the location of Figure 2 or Figure 3 A schematic top view of region A on the diagonal of the display area AA within the array substrate of the display module. Figure 5 Show Figure 4 A schematic cross-sectional view taken along line AA'.
[0069] In a specific example, refer to Figure 4 and Figure 5 As shown, the display panel includes a display substrate 100 and a driving circuit layer disposed on the display substrate 100. The driving circuit layer includes a plurality of thin-film transistors (TFTs) T. Each TFT T includes a source / drain electrode 201 and a gate electrode 202.
[0070] Reference Figure 4 and Figure 5 As shown, the driving circuit layer includes a gate layer and a source / drain metal layer sequentially stacked on the substrate 100. Specifically, the driving circuit layer includes a gate layer, a gate insulating layer 203, an active layer 204, and a source / drain metal layer sequentially stacked on the substrate 100. Figure 4-5 As shown, the source and drain electrodes 201 are disposed in the source and drain metal layer, and the gate electrode 202 is disposed in the gate layer.
[0071] The gate layer can be a multilayer metal structure, and the film layer combination can be selected from one or a stack of molybdenum / aluminum / molybdenum (Mo / Al / Mo), molybdenum / copper (Mo / Cu), molybdenum-niobium alloy / copper (MoNb / Cu), molybdenum-niobium alloy / copper / molybdenum-titanium alloy (MoNb / Cu / MoTi). The gate insulating layer 203 can be made of silicon oxide, silicon nitride, or other inorganic insulating materials, and the gate insulating layer 203 can be a single layer or multiple layers. The active layer 204 can be a polycrystalline silicon layer, and the source / drain metal layer film layer combination can be selected from one or a stack of Mo / Al / Mo, Mo / Cu, MoNb / Cu, MoNb / Cu / MoTi, etc.
[0072] It should be noted that, although Figure 5 The example shows a thin-film transistor T with a bottom-gate structure, but the embodiments of this disclosure are not limited to this. Thin-film transistors can also have a top-gate structure, the difference depending on the position of the gate layer and the active layer, which will not be elaborated here.
[0073] Continue to refer to Figure 4 As shown, the array substrate also includes: multiple array-arranged first electrodes 205 and multiple common electrode lines DVCOM.
[0074] Specifically, the common electrode line DVCOM extends along a first direction and is arranged along a second direction, and the common electrode line DVCOM is electrically connected to a row of first electrodes 205. In this example, the first direction is the X direction, the second direction is the Y direction, and the first direction is perpendicular to the second direction, but this disclosure is not limited to this. In the case of mutual perpendicularity, the first direction can also be the Y direction, and the second direction can also be the X direction. Of course, this disclosure does not limit the first direction and the second direction to be perpendicular; they can simply intersect.
[0075] In embodiments of this disclosure, each row of first electrodes 205 is electrically connected together via a common electrode line DVCOM and receives the same signal; the first electrodes 205 may also be referred to as common electrodes.
[0076] In embodiments of this disclosure, the array substrate further includes a plurality of redundant signal lines Dummy, which extend along a second direction (Y direction in the figure) and are arranged along a first direction (X direction in the figure) to improve the consistency of the wiring pattern of the display area AA, thereby improving the height uniformity of the display area AA.
[0077] Figure 4 Show Figure 2 or Figure 3In the example of region A, for instance, the redundant signal line Dummy will extend along the Y direction through the display area AA. Therefore, based on the wiring pattern in the array substrate, the redundant signal line Dummy should be provided at the same position in the display area AA where the region in the X direction has the same width as region A.
[0078] In particular, in embodiments of this disclosure, at least a portion of the plurality of common electrode lines are electrically connected at one end to form a plurality of first loop coils, and at least a portion of the plurality of redundant signal lines are electrically connected at one end to form a plurality of second loop coils; and one of the common electrode line and the redundant signal line is disposed on the same layer as the source and drain of the thin-film transistor, and the other is disposed on the same layer as the gate of the thin-film transistor.
[0079] Specifically, in this example, the common electrode line DVCOM is located in the gate layer, that is, the common electrode line DVCOM is located in the same layer as the gate 202; the redundant signal line Dummy is located in the source and drain metal layer, that is, the redundant signal line Dummy is located in the same layer as the source and drain electrodes 201 of the thin film transistor T.
[0080] Through the above configuration, multiple first-loop coils extending along a first direction and multiple second-loop coils extending along a second direction can be formed using the existing common electrode line DVCOM and redundant signal lines Dummy in the array substrate. This allows for the deployment of EMR sensing coils using the existing signal lines in the array substrate. In particular, the common electrode line DVCOM itself has the characteristics of wider linewidth, lower resistance, and a larger number of lines. Using this signal line to construct the EMR sensing coil ensures that the formed EMR sensing coil has a sufficient number of coils and enough space to set the linewidth, even when using the existing metal layers of the array substrate. This improves the induced electromotive force, thus ensuring good performance for both active and passive electromagnetic pen sensing methods while achieving thinner and smaller display products. Furthermore, the above configuration does not change existing processes or significantly increase bill of materials (BOM) costs, achieving low-cost design.
[0081] Continue to refer to Figure 2 and Figure 3 For example, in ultra-narrow bezel display products designed to provide scan and data signals to pixels in the display area AA via an external driver chip, especially when the array substrate of this disclosure is applied to an electronic paper display product, it is necessary to use adapter leads to convert signal lines arranged in different directions to the same direction in order to receive scan and data signal lines from the driver chip. In this case, the array substrate typically includes regularly arranged redundant signal lines (Dummy) to compensate for the wiring inconsistencies caused by the adapter leads.
[0082] Optionally, the driving circuit layer further includes: a plurality of first signal lines extending along a first direction and arranged along a second direction; a plurality of second signal lines extending along the second direction and arranged along the first direction; and a plurality of transition signal lines extending along the second direction and arranged along the first direction, wherein the transition signal lines are electrically connected to the first signal lines in a one-to-one correspondence, and the sum of the number of signal lines between two adjacent columns of first electrodes is the same, and the signal lines include at least two of the second signal lines, transition signal lines, and redundant signal lines. That is, the specific types of signal lines between two adjacent columns of first electrodes may be different, but the number is the same.
[0083] For example, Figure 6 It shows Figure 2-4 A simplified schematic diagram of an array substrate based on the structure shown. (For ease of illustration) Figure 6 The illustration will only take an array substrate comprising 12 columns and 9 rows of first electrodes 205 as an example, wherein one first electrode 205 corresponds to one pixel unit. It should be understood that this disclosure is not limited thereto, and the number and layout of the first electrodes in actual applications depend on the number and layout of the pixel units.
[0084] It should be noted that Figure 4 The structure of region A shown in the figure, without considering the redundant signal line Dummy, is similar to... Figure 6 The structures of each region highlighted by the thick solid line are identical. Without considering redundant signal lines (Dummy) and vias (TK1), the structure of region A, consisting of 4 columns and 3 rows of first electrodes 205, is equivalent to the smallest repeating unit of an array substrate comprising 12 columns and 9 rows of first electrodes 205. It should be understood that if the array substrate includes N first electrodes 205 in the Y direction and M first electrodes 205 in the X direction, with a N / M ratio of 3 / 4, then the structure of the smallest repeating unit, excluding redundant signal lines (Dummy) and vias (TK1), is identical to... Figure 4 The structures shown are similar, with N and M being integers greater than 1.
[0085] Reference Figure 4 and Figure 6 As shown, in this example, the first signal line extending along the first direction is the gate signal line Gx, and the second signal line extending along the second direction is the data signal line Dy.
[0086] Specifically, region A includes four columns and three rows of first electrodes 205, each corresponding to a pixel unit. Correspondingly, each column of first electrodes 205 corresponds to a data signal line Dy, and each row of first electrodes 205 corresponds to a gate signal line Gx, as well as a common signal line DVCOM. Therefore, region A has a total of four data signal lines Dy1, Dy2, Dy3, and Dy4, and three gate signal lines Gx1, Gx2, and Gx3. When no distinction is needed, in this example, the gate signal lines are collectively referred to as gate signal lines Gx, and the data signal lines are collectively referred to as Dy.
[0087] Combination Figure 2-3 As shown in the example, the display driver chip D-IC is located in the non-display area NA at the bottom of the figure. Data signals and scan signals are correspondingly accessed from the bottom side of the figure. Area A has three transition signal lines LGx1, LGx2, and LGx3 extending along the Y direction and arranged along the X direction. The number of transition signal lines LGx is the same as the number of gate signal lines Gx. Each transition signal line LGx can be electrically connected to the corresponding gate signal line Gx through a via TK1 to achieve gate signal line transition. Similarly, in this example, when no distinction is needed, the transition signal lines are collectively referred to as transition signal lines LGx.
[0088] Reference Figure 4 As shown, a data signal line Dy is provided between two adjacent columns of first electrodes 205, and three transition signal lines LGx extending along the Y direction are provided correspondingly for the four columns of first electrodes 205. Figure 4 As shown, if the data signal lines Dy are all located to the left of the corresponding column's first sub-electrode 205, and the transition signal lines LGx are all located between the two columns of first electrodes 205 in region A, then each minimum repeating unit includes two signal lines extending along the Y direction between adjacent columns of first electrodes 205, and one signal line extending along the Y direction is provided to the left of the minimum repeating unit. After all the minimum repeating units are spliced into an array substrate, there will be only one signal line between two columns of minimum repeating units. Therefore, referring to... Figure 6 As shown, a redundant signal line Dummy is set between the two columns of smallest repeating units, that is, the number of redundant signal lines Dummy is 12-9=3. Then, there are 2 signal lines between the pixel units corresponding to all first electrodes 205. There is a data signal line Dy on the left side of the first electrode 205 in the first column, and a redundant signal line dummy on the right side of the first electrode 205 in the 12th column, which can ensure the uniformity of wiring in the display area AA.
[0089] Of course, the embodiments of this disclosure are not limited to the above proportional relationships. Optionally, the driving circuit layer includes N first signal lines and M second signal lines. When the redundant signal lines Dummy are MN, N and M are integers greater than 1.
[0090] In some alternative embodiments, if the number N of the first signal lines that need to be drawn out by the transition signal lines is greater than the number M of the second signal lines, the number of redundant signal lines Dummy will follow another rule.
[0091] For example, Figure 7 A simplified schematic diagram of another exemplary array substrate is shown. Figure 8 A schematic top view of region A on the diagonal is shown. Also for ease of illustration, Figure 7 The illustration will be based on an array substrate comprising 9 columns and 12 rows of first electrodes 205, wherein one first electrode 205 corresponds to one pixel unit. Of course, this disclosure is not limited to this, and the number and layout of the first electrodes in actual applications depend on the number and layout of the pixel units.
[0092] It should be noted that, without considering redundant signal lines (Dummy) and vias (TK1), Figure 8 The structure of region A, consisting of 3 columns and 4 rows of first electrodes 205, is equivalent to the smallest repeating unit of an array substrate comprising 9 columns and 12 rows of first electrodes 205. It should be understood that if the array substrate includes N first electrodes 205 in the Y direction and M first electrodes 205 in the X direction, with a N / M ratio of 4 / 3, then the structure of the smallest repeating unit, excluding the redundant signal line Dummy and the via TK1, is similar to... Figure 8 The structures shown are similar, with N and M being integers greater than 1.
[0093] Reference Figure 8 As shown, in this example, the first signal line extending along the first direction is the data signal line Dx, and the second signal line extending along the second direction is the gate signal line Gy.
[0094] Specifically, region A includes three columns and four rows of first electrodes 205, each corresponding to a pixel unit. Correspondingly, each column of first electrodes 205 corresponds to a gate signal line Gy, and each row of first electrodes 205 corresponds to a data signal line Gx, as well as a common signal line DVCOM. Therefore, region A has a total of four data signal lines Dx1, Dx2, Dx3, and Dx4, and three gate signal lines Gy1, Gy2, and Gy3. When no distinction is needed, in this example, the gate signal lines are collectively referred to as gate signal lines Gy, and the data signal lines are collectively referred to as Dx.
[0095] In this example, the display driver chip D-IC is located in the non-display area NA at the bottom of the diagram. Data signals and scan signals are correspondingly accessed from the bottom of the diagram. Area A has four transition signal lines LDx1, LDx2, LDx3, and LDx4 extending along the Y direction and arranged along the X direction. The number of transition signal lines LDx is the same as the number of data signal lines Dx. Each transition signal line LDx can be electrically connected to the corresponding data signal line Dx through a via TK1 to achieve data signal line switching. Similarly, in this example, when no distinction is needed, the transition signal lines are collectively referred to as transition signal lines LDx.
[0096] Reference Figure 8 As shown, a gate signal line Gy is provided between two adjacent columns of first electrodes 205, and four transition signal lines LDx extending along the Y direction are correspondingly provided between the three columns of first electrodes 205. Figure 8As shown, if the gate signal lines Gy are all located on the left side of the corresponding column's first sub-electrode 205, a transfer signal line LDx needs to be set on both sides of each column's first electrode 205 in region A to achieve the transfer of all data signal lines Dx in region A. Therefore, each minimum repeating unit includes two signal lines extending along the Y direction between two adjacent columns of first electrodes 205. The left side of the minimum repeating unit has two signal lines extending along the Y direction, and the right side has one signal line extending along the Y direction. Thus, after all minimum repeating units are spliced into an array substrate, there will be three signal lines between two columns of minimum repeating units. Therefore, referring to... Figure 8 As shown, when one redundant signal line Dummy is set between the two columns of first electrodes 205 within each minimum repeating unit, that is, the number of redundant signal lines Dummy is 9*2-12=6, then there are 3 signal lines between all pixel units corresponding to the first electrodes 205, thereby ensuring the uniformity of wiring in the display area AA.
[0097] It should be noted that, since two transition signal lines LDx are set between the two columns of minimum repeating units via via TK1, to avoid ambiguity, Figure 8 The diagram shows a gap between the two columns of the smallest repeating units.
[0098] Of course, the embodiments of this disclosure are not limited to the above proportional relationships. Optionally, the driving circuit layer includes N first signal lines and M second signal lines. At that time, the number of redundant signal lines Dummy is (n+1)MN, where N and M are integers greater than 1, and n = 1, 2, 3...
[0099] It should also be noted that although the above examples are illustrated with the first direction being the X direction in the attached figures and the second direction being the Y direction in the attached figures, this disclosure is not limited to this. When the first direction is the Y direction and the second direction is the X direction, the display driver chip and the flexible circuit board can also be arranged on the left and right sides in the attached figures, and the number of their redundant signal lines also satisfies the relationship described above, which will not be repeated below.
[0100] It can be seen that when the number of first signal lines that need to be switched is greater than the number of second signal lines, under the same conditions, the number of redundant signal lines (Dummy) is greater and their arrangement is relatively denser than when the number of first signal lines that need to be switched is less than the number of second signal lines.
[0101] This disclosure does not intend to use all redundant signal lines (Dummy) on the array substrate as second loop coils. That is, a portion of the redundant signal lines (Dummy) can be used to form multiple second loop coils as needed. When only a portion of the redundant signal lines (Dummy) are used to form a second loop coil, one end of all the redundant signal lines (Dummy) can be electrically connected together, with only a portion led out to receive drive signals. Alternatively, one end of the required portion of the redundant signal lines (Dummy) can be electrically connected together, and the formed second loop coil can be led out to the flexible circuit board to receive drive signals. Furthermore, this disclosure does not intend to limit each redundant signal line used to form a second loop coil to an independent second loop coil. One or more of them can be connected in parallel to form the same second loop coil according to the distribution pattern.
[0102] Similarly, in the embodiments of this disclosure, only a portion of the common electrode line DVCOM can be used to form the first loop coil. Of course, because the distribution of the common electrode line DVCOM is uniform, all the common electrode lines DVCOM can be used to form multiple first loop coils to improve sensing accuracy and reduce driving difficulty.
[0103] Continue to refer to Figure 4 and Figure 5 As shown, when the switching signal line switches to the gate signal line, the second signal line is the data signal line Dy, the first signal line is the gate signal line Gx, and the switching signal line is LGx.
[0104] Optionally, the source / drain electrode 201, the second signal line, the transition signal line LGx, and the redundant signal line Dummy are disposed in the source / drain metal layer, and the gate electrode 202, the first signal line, and the common electrode line DVCOM are disposed in the gate layer.
[0105] In this case, refer to Figure 5 As shown, the array substrate may further include a pixel electrode 209. One of the source and drain electrodes of the thin-film transistor T is directly electrically connected to the data signal line Dy, and the other is electrically connected to the pixel electrode 209 via a via through the passivation layer 206 and the planarization layer 207 through the wiring layer 208. Additionally, through... Figure 5 As can be seen, the first electrode 205 is electrically isolated from the thin-film transistor T, thereby electrically isolating the common electrode line DVCOM from the data signal line and the gate signal line.
[0106] Alternatively, refer to Figure 5As shown, the array substrate may also include a capacitor plate Cs disposed in the gate layer. The capacitor plate Cs is electrically connected to the pixel electrode 209 through a via through the gate insulating layer 203 and an electrode in the source drain 201 connected to the pixel electrode 209, thereby enabling the pixel electrode 209 to be charged by means of the capacitor plate Cs, thereby improving the stability of the display.
[0107] It should be noted that this setting method is not limited to... Figure 4 and Figure 5 The case shown is where the first direction is the X direction and the second direction is the Y direction. That is to say, even though it is not shown, even if the first direction is the X direction and the second direction is the Y direction, and the data signal line is adjusted to extend laterally and the gate signal line is adjusted to extend vertically, as long as the transfer signal line still transfers the gate signal line, the film layer relationship is still satisfied.
[0108] Continue to refer to Figure 8 and Figure 9 As shown, when the switching signal line switches to the data signal line, the second signal line is the gate signal line Gy, the first signal line is the data signal line Dx, and the switching signal line is LDx.
[0109] Optionally, the source / drain electrode 201, the first signal line, and the common electrode line DVCOM are disposed in the source / drain metal layer, and the gate electrode 202, the second signal line, the transition signal line LDx, and the redundant signal line Dummy are disposed in the gate layer.
[0110] In this case, refer to Figure 9 As shown, the array substrate may also include a pixel electrode 209. One of the source and drain electrodes of the thin film transistor T is directly electrically connected to the data signal line Dy, and the other is electrically connected to the pixel electrode 209 via a via through the passivation layer 206 and the planarization layer 207 through the wiring layer 208.
[0111] Alternatively, refer to Figure 9 As shown, the array substrate may also include a capacitor plate Cs disposed in the gate layer. The capacitor plate Cs is electrically connected to the pixel electrode 209 through a via through the gate insulating layer 203 and an electrode in the source drain 201 connected to the pixel electrode 209, thereby enabling the pixel electrode 209 to be charged by means of the capacitor plate Cs, thereby improving the stability of the display.
[0112] It should be noted that this setting method is not limited to... Figure 8 and Figure 9The case shown is the first direction being the X direction and the second direction being the Y direction. That is to say, even if the first direction is the X direction and the second direction is the Y direction, so that the data signal line is adjusted to extend vertically and the gate signal line is adjusted to extend horizontally, as long as the transfer signal line still transfers the data signal line, the film layer relationship is still satisfied.
[0113] Optionally, continue to refer to Figure 4 and Figure 5 As shown, the first electrode 205 and the common electrode line DVCOM are located on different layers, that is, they are not set on the same layer. The first electrode 205 is electrically connected to the common electrode line DVCOM through a via TK that passes through to the common electrode line DVCOM.
[0114] Optionally, if the first electrode and the common electrode line are disposed on the same layer, the first electrode can be directly electrically connected to the common electrode line without the need for a via.
[0115] For example, refer to Figure 8 and Figure 9 As shown, the first electrode 205 and the common electrode line DVCOM are both disposed in the source and drain metal layers, and are disposed in the same layer, so that they can be directly electrically connected together.
[0116] For example, refer to Figure 10 and Figure 11 As shown, the first electrode 205 and the common electrode line DVCOM are both disposed in the gate layer. Since they are disposed in the same layer, they can be directly electrically connected together.
[0117] It is worth mentioning that at this time, the capacitor plate Cs can be set with the help of the source and drain metal layers. That is, by increasing the pattern area between the source and drain electrodes and the via connecting the pixel electrode 209, the capacitor plate Cs can be formed, and the stability of the pixel electrode 209 can be improved by charging it.
[0118] In some alternative embodiments, refer to Figure 12 As shown, this embodiment is similar to Figure 4 The difference in the embodiment is that the array substrate further includes: a plurality of electrode lines Ly.
[0119] Optionally, multiple electrode lines extend along a second direction and are arranged along a first direction, and include multiple first electrode line groups that are arranged one-to-one with redundant signal lines. Each first electrode line group includes at least one electrode line, the number of first electrode lines in each first electrode line group is equal, and the electrode lines in the same first electrode line group are connected in parallel to the same redundant signal line.
[0120] This example shows that an electrode line Ly is added between each of the two adjacent columns of first electrodes 205. Electrode lines Ly1, Ly2, Ly3, and Ly4 are set in region A. The redundant signal line Dummy in the smallest repeating unit corresponding to region A and the electrode lines Ly1, Ly2, Ly3, and Ly4 can be regarded as a first electrode line group. The redundant signal line Dummy in the first electrode line group is connected in parallel with the electrode lines Ly1, Ly2, Ly3, and Ly4 to form a second loop coil. This can ensure the resistance matching of the human loop coil in the display area and improve the sensing uniformity.
[0121] Of course, this disclosure is not intended to limit the number and arrangement of electrode lines Ly in each first electrode line resistor. The specific arrangement depends on the wiring space and wiring uniformity of the array substrate, and will not be elaborated here.
[0122] Optionally, continue to combine Figure 2 , Figure 3 , Figures 13-16 As shown, the driving circuit layer further includes a wiring layer disposed on the side of the source / drain metal layer away from the substrate 100. (Refer to...) Figure 13-15 As shown, the routing layer includes: a first routing line YVCOM and a second routing line XVCOM surrounding the display area AA.
[0123] It is particularly important to note that, in the embodiments of this disclosure, because the common electrode line DVCOM needs to be multiplexed as the coil for EMR sensing, unlike related technologies, the common electrode line DVCOM cannot be electrically connected together using a common electrode bus to receive a common level signal when displaying an image. That is, optionally, one end of the multiple common electrode lines constituting different first loop coils is electrically connected together, while the other end is electrically isolated, or in other words, the other end is not electrically connected. Even when the common electrode line DVCOM constituting the first loop coil needs to be connected to the same drive signal during display driving or electromagnetic sensing driving, it must be connected to the drive signal separately and cannot be electrically connected together to ensure independent electromagnetic sensing can be performed via the other end.
[0124] Alternatively, for ease of setup, one end of all common electrode lines can be electrically connected together, while the other end of the common electrode lines constituting different first loop coils can be electrically isolated, as long as the first loop coil can achieve electromagnetic induction, this article does not impose any limitations.
[0125] Reference Figure 13 As shown, the common electrode line DVCOM is electrically connected to the first trace YVCOM via a via that passes through to the first trace YVCOM to form the first loop coil.
[0126] Reference Figure 14As shown, the redundant signal line Dummy is electrically connected to the second trace XVCOM via a via that passes through to the second trace XVCOM to form a second loop coil.
[0127] Reference Figure 14 and Figure 16 As shown, the redundant signal line Dummy can be electrically connected to the second trace XVCOM via the Dummy lead. In area D, which is not the display area NA, when it is necessary to lead out the signal lines located on the two metal layers through the fan-out lines respectively, the signal lines can be led out to the fan-out lines through the Dummy lead and the adapter lead located on the two metal layers respectively at different positions via vias, thereby avoiding signal interference.
[0128] Reference Figure 17 As shown, embodiments of this disclosure also provide a driving method for an array substrate applied to the above embodiments. The display process of one frame of image includes a scanning period T1 and a blanking period T2. The method includes:
[0129] During the scanning period T1: the common electrode line DVCOM is connected to a DC signal of the first level;
[0130] During the blanking period T2: a high-frequency AC signal is connected to the common electrode line DVCOM and the second loop coil for electromagnetic sensing.
[0131] Specifically, refer to Figure 17 The figure illustrates the display synchronization signal SYNC, the data signal Data, the scan signals G1-Gn, the common electrode signal of the common electrode line DVCOM (which does not form the first loop coil), and the signals of the first trace YVCOM and the second trace XVCOM, used to control the display time and mute time. Here, because this disclosure does not provide a unified signal to all common electrode lines via a common electrode bus, the common electrode line DVCOM (which does not form the first loop coil) refers to a common electrode line not used for electromagnetic sensing that does not require a separate common electrode signal. Of course, if all common electrode lines are used to form the first loop coil for electromagnetic sensing, then a separate common electrode signal is not required.
[0132] In this embodiment, the blanking period during which no data writing and scanning are performed during the display process is used as the EMR driving and detection period, thereby realizing time-division multiplexing of the common electrode line DVCOM, and thus realizing EMR sensing using the existing signal lines of the array substrate.
[0133] Optionally, during the scanning period T1, the data signal Data and the scanning signals G1-Gn are written to the corresponding signals normally based on the control of the synchronization signal SYNC. At the same time, the common electrode line DVCOM is connected to a first-level DC signal to ensure that the display panel is driven by the array substrate to perform normal image display.
[0134] During the blanking period T2, a high-frequency AC signal is connected to the common electrode line and the second loop coil. This high-frequency signal may or may not be limited to... Figure 17 The square wave signal shown can be a sinusoidal AC signal, a triangular wave signal, or a composite signal composed of various signals, to drive the first and second loop coils for electromagnetic sensing. It should be understood that in the timing diagram, DVCOM, Yn, and Xn represent the common bus located on the outermost edge of the array substrate, and the first and second loop coils in the horizontal and vertical directions, respectively.
[0135] Optionally, during the blanking period T2, both the first signal line and the switching signal line are connected to a high-frequency AC signal to avoid signal crosstalk, thereby reducing the coil load and improving sensing accuracy.
[0136] Optionally, during the blanking period T2, all signals except the ground signal GND are synchronously loaded with the aforementioned high-frequency AC signal to ensure good sensing performance.
[0137] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, which is based on the display substrate described above.
[0138] Since the array substrate included in the display panel provided in this embodiment is the same as the array substrate provided in the above embodiments, the usage method provided in this embodiment is also applicable to the previous embodiments, and will not be described in detail in this embodiment.
[0139] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which is the display panel described above.
[0140] In this embodiment, the display device can be any display product or component with electromagnetic touch function, such as a mobile phone, tablet computer, television, monitor, laptop computer, in-vehicle display, digital photo frame or navigator, especially various electronic paper display devices. By loading the above display panel, the display device can achieve thin and light electromagnetic touch at a lower cost, and can make the display device have good touch accuracy.
[0141] Obviously, the above embodiments of this disclosure are merely examples for clearly illustrating this disclosure, and are not intended to limit the implementation of this disclosure. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all implementation methods here. Any obvious variations or modifications derived from the technical solutions of this disclosure are still within the protection scope of this disclosure.
Claims
1. An array substrate, characterized by, The display panel comprises: a driving circuit layer formed on a substrate, the driving circuit layer comprising a plurality of thin film transistors, the driving circuit layer further comprising: a plurality of arrayed first electrodes; a plurality of common electrode lines extending in a first direction and arranged in a second direction, the common electrode lines being electrically connected with a row of the first electrodes, the first direction intersecting the second direction; and a plurality of redundant signal lines extending in the second direction and arranged in the first direction, the redundant signal lines being electrically isolated from the common electrode lines, one end of at least part of the plurality of common electrode lines being electrically connected together to form a plurality of first loop coils, one end of at least part of the plurality of redundant signal lines being electrically connected together to form a plurality of second loop coils, one of the common electrode lines and the redundant signal lines is arranged in the same layer as the source-drain electrode of the thin film transistor, and the other is arranged in the same layer as the gate electrode of the thin film transistor.
2. The array substrate of claim 1, wherein, The driving circuit layer further comprises: a plurality of first signal lines extending in the first direction and arranged in the second direction; a plurality of second signal lines extending in the second direction and arranged in the first direction; and a plurality of switching signal lines extending in the second direction and arranged in the first direction, the switching signal lines being electrically connected one-to-one with the first signal lines, the number of signal lines between two adjacent columns of the first electrodes is the same, the signal lines including at least two of the second signal lines, the switching signal lines and the redundant signal lines.
3. The array substrate of claim 2, wherein, The driving circuit layer comprises: N first signal lines and M second signal lines, When the number of the redundant signal lines is (n+1)M-N, When the number of the redundant signal lines is M-N, wherein N and M are integers greater than 1, n = 1, 2, 3, ….
4. The array substrate of claim 2, wherein, The driving circuit layer comprises: a gate layer and a source-drain metal layer which are sequentially stacked on the substrate, the source-drain electrode, the second signal lines, the switching signal lines and the redundant signal lines are arranged in the source-drain metal layer, and the gate electrode, the first signal lines and the common electrode lines are arranged in the gate layer.
5. The array substrate of claim 2, wherein, The driving circuit layer comprises: a gate layer and a source-drain metal layer which are sequentially stacked on the substrate, the source-drain electrode, the first signal lines and the common electrode lines are arranged in the source-drain metal layer, and the gate electrode, the second signal lines, the switching signal lines and the redundant signal lines are arranged in the gate layer.
6. The array substrate of claim 1, wherein, The driving circuit layer further comprises: a plurality of electrode lines, the plurality of electrode lines extend in the second direction and are arranged in the first direction, and comprise a plurality of first electrode line groups arranged one-to-one with the redundant signal lines, each first electrode line group comprising at least one electrode line, the number of first electrode lines in each first electrode line group is equal, and the electrode lines in the same first electrode line group are connected in parallel to the same redundant signal line.
7. The array substrate of claim 2, wherein, The display panel comprises a display area and a non-display area surrounding the display area, and the driving circuit layer comprises: a source-drain metal layer arranged on the substrate and a wiring layer arranged on the side of the source-drain metal layer away from the substrate, the wiring layer comprises a first wiring and a second wiring surrounding the display area, The common electrode line is electrically connected to the first trace via a via hole penetrating to the first trace to form the first loop coil, The redundant signal line is electrically connected to the second trace via a via hole penetrating to the second trace to form the second loop coil.
8. The array substrate of claim 1, wherein, The first electrode and the common electrode line are arranged in the same layer, and the first electrode and the common electrode line are directly electrically connected, or The first electrode and the common electrode line are arranged in different layers, and the first electrode is electrically connected to the common electrode line via a via hole penetrating to the common electrode line.
9. The array substrate of claim 1, wherein, One end of a plurality of common electrode lines constituting different first loop coils are electrically connected together, and the other end is electrically isolated.
10. A display panel, characterized by, An array substrate as claimed in any one of claims 1-9.
11. A display device, characterized by comprising: A display panel as claimed in claim 10.