Layout structure of bus transceiver
By rationally arranging the layout structure of the bus transceiver and adopting a centrally symmetrical transmission layout area and isolation band design, the problem of increased chip area was solved, achieving the effects of saving space and reducing costs, while ensuring the reliability and stability of the product.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2026-03-17
AI Technical Summary
The layout design of bus transceivers leads to an increase in chip area and manufacturing costs, and also has application limitations, mainly due to the isolation requirements between unequal potential wells, the design requirements of independent substrates, and the requirements of multiple power supplies and tri-state control functions.
The layout of multiple signal input, power supply, grounding and control module areas is rationally arranged. The transmission layout area is centrally symmetrically arranged. Areas with the same well voltage are set close together to reduce isolation structures. Unequal potential well isolation is achieved through isolation strips. Independent substrate devices are rationally arranged to reduce interconnects.
It effectively saves chip space, reduces interconnects, lowers costs, and at the same time ensures product performance and reliability, thus achieving chip miniaturization.
Smart Images
Figure CN224007005U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of integrated circuit design, and specifically to a layout structure of a bus transceiver. Background Technology
[0002] In electronic control systems, the main control chip typically has a low output voltage and weak driving capability, while the peripheral chips operate at higher voltages. In particular, when multiple external loads are connected simultaneously, the front-end stage needs to have a greater driving capability to ensure the reliability of signal transmission.
[0003] Therefore, a bus transceiver is needed between the main control chip and the peripheral chips to enable bidirectional communication and improve the front-end driving capability. Simultaneously, to achieve flexible signal control and bidirectional data transmission, as well as signal isolation between devices, the bus transceiver needs to use two tri-state output gates to control the input and output respectively, allowing the circuit to flexibly switch between input and output.
[0004] Furthermore, when a bus transceiver needs to connect to devices with different voltages, multiple independent power supplies are required to solve the data transmission compatibility problem. Therefore, the layout of the bus transceiver needs to include unequal potential wells, and isolation structures are required between unequal potential wells with different voltages.
[0005] In addition, to protect the chip from damage when the power supply is lost, the bus transceiver is required to have both cold and hot backup functions. This requires a special structural design for the bus transceiver layout, which usually requires a separate substrate.
[0006] The aforementioned requirements for isolation between unequal potential wells, the design requirements for independent substrates, and the functional requirements for multiple power supplies and three-state control are reflected in the layout design of the bus transceiver, leading to an increase in the area of the bus transceiver chip, which in turn increases manufacturing costs and limits applications. Utility Model Content
[0007] To address the aforementioned problems in the prior art, this application provides a layout structure for a bus transceiver. This layout structure specifically includes multiple signal input layout areas, multiple power supply layout areas, multiple ground layout areas, at least one control module layout area, and multiple sets of transmission layout areas arranged along a first direction. Each set of transmission layout areas includes two transmission layout areas arranged along a second direction and centrally symmetrical.
[0008] The transfer layout area includes a first transfer sub-layout area, a second transfer sub-layout area, and a third transfer sub-layout area arranged sequentially from the outer side to the inner side of the chip along the second direction, as well as transfer pads.
[0009] The third transmission sub-layout area is equipped with a transmission structure, which includes:
[0010] An independent substrate region is adjacent to and shares a substrate with the second transport sub-pattern region;
[0011] The first well region and the second well region are disposed at both ends of the third transmission sub-layout region along the first direction, and are respectively adjacent to the second well region and the first well region in the same group of transmission layout regions; wherein, in the same group of transmission layout regions, the adjacent first well region and the second well region are connected to the same power supply voltage.
[0012] In the aforementioned technical solution, devices with independent substrates are arranged together through a reasonable layout, thereby saving space and reducing interconnect lines.
[0013] In addition, the upper and lower transmission layout areas are arranged in a centrally symmetrical manner, which makes the well voltage of the adjacent areas (first and second well areas) of the upper and lower transmission layout areas the same. As a result, the upper and lower transmission layout areas can be arranged close together without leaving a gap or setting up an additional isolation structure, which also saves chip area.
[0014] Optionally, it may also include a safety barrier, which is set at least in one of the following locations:
[0015] The second transmission sub-pattern area is adjacent to the first or second well area;
[0016] Between the independent substrate region and the first well region or the second well region;
[0017] The first well region extends along both ends of the first direction;
[0018] The second well region extends along both ends of the first direction.
[0019] The isolation strip in the aforementioned optional solution can effectively isolate unequal potential wells within the same module or between adjacent modules, reducing interference and ensuring product performance. This avoids sacrificing product performance and reliability while compressing chip space as in other solutions.
[0020] Optionally, the independent substrate region is adjacent to the first well region or the second well region.
[0021] Optionally, the first transmission sub-layout area is provided with an output NMOS transistor and an ESD protection structure; the second transmission sub-layout area is provided with an output PMOS transistor; and the transmission pad covers at least a portion of the first and second transmission sub-layout areas.
[0022] The entire transmission layout area is elongated, with each sub-layout area and transmission pad arranged centered on the left and right. This makes the array of multiple transmission layout areas more regular, which is conducive to the compact arrangement of the array, thereby saving chip area and achieving miniaturization.
[0023] Optionally, one or more layout areas selected from multiple signal input layout areas, multiple power supply layout areas, and multiple ground layout areas, including:
[0024] ESD protection layout area and filled structure layout area;
[0025] Connecting pads cover at least a portion of the ESD protection layout area and the fill structure layout area.
[0026] The aforementioned structure facilitates chip planarization. The ESD protection layout area, the fill structure layout area, and the connection pads are all arranged centered horizontally. The connection pads cover the ESD protection layout area and the fill structure layout area without occupying separate space, which greatly reduces the chip area and saves costs.
[0027] Optionally, in the multiple power supply layout areas, a portion of the power supply layout area's connection pads are used to connect to the first power supply, and another portion of the power supply layout area's connection pads are used to connect to the second power supply.
[0028] In the same group of transmission layout areas, the first well area and the second well area located on one side and adjacent to each other are connected to the first power supply, and the first well area and the second well area located on the other side and adjacent to each other are connected to the second power supply.
[0029] Optionally, multiple power supply layout areas are disposed at one end of the chip along the first direction, including a first power supply layout area, a second power supply layout area, and a third power supply layout area;
[0030] Along the second direction, the first power supply layout area and the third power supply layout area are located on both sides of the chip, and the second power supply layout area is located in the middle of the chip;
[0031] The connection pads in the first power supply layout area and the second power supply layout area are used to connect the second power supply, and the connection pads in the third power supply layout area are used to connect the first power supply.
[0032] Optionally, the multiple signal input layout areas include those disposed on both sides of the chip along the second direction:
[0033] The enable signal input area is located between the first power supply area and the transmission area;
[0034] The direction signal input layout area is located between the third power supply layout area and the transmission layout area.
[0035] Optionally, multiple grounding layout areas are disposed at one end of the chip away from multiple power supply layout areas along a first direction, including a first grounding layout area, a second grounding layout area, and a third grounding layout area;
[0036] Along the second direction, the first grounding pattern area and the third grounding pattern area are located on both sides of the chip, and the second grounding pattern area is located in the middle of the chip.
[0037] Optionally, at least one control module layout area is located between the second power supply layout area and the transmission layout area, including an enable control module layout area and a direction control module layout area;
[0038] The enable control module layout area and the direction control module layout area are adjacent to each other and symmetrical about the first direction. The enable control module layout area is located near the enable signal input layout area, and the direction control module layout area is located near the direction signal input layout area.
[0039] The bus transceiver layout structure provided by the aforementioned technical solution, by centrally arranging the devices on independent substrates and by placing areas with the same well voltage close together in a centrally symmetrical arrangement, makes the product layout compact and reasonable, saves space, reduces the use of interconnects and isolation structures, and further ensures the reliability and stability of the device through isolation strips. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.
[0041] Figure 1 This is a schematic diagram of the logic framework of the bus transceiver provided in this application;
[0042] Figure 2 This is a schematic diagram of the layout structure of the bus transceiver provided in this application;
[0043] Figure 3 This is a schematic diagram of the specific structure of a portion of the map area in this application;
[0044] Figure 4 This is a schematic diagram of the specific structure of the transmission layout area in this application;
[0045] Figure 5 This is a schematic diagram of the common substrate portion and the unequal potential well in the transfer layout area of this application;
[0046] Figure 6 This is a schematic diagram of a set of transmission layout areas in this application. The diagram shows two transmission layout areas that are centrally symmetrical, and the sink voltage connection method of these two transmission layout areas.
[0047] The image is labeled as follows:
[0048] 100: Signal input layout area, 200: Power supply layout area, 300: Grounding layout area, 400: Control module layout area, 500: Transmission layout area;
[0049] 110: Enable signal input layout area; 120: Direction signal input layout area;
[0050] 210: First power supply layout area; 220: Second power supply layout area; 230: Third power supply layout area;
[0051] 310: First grounding area; 320: Second grounding area; 330: Third grounding area;
[0052] 410: Enable control module layout area; 420: Direction control module layout area;
[0053] 511, 512, 521, 522, 531, 532, 541, 542, 551, 552, 561, 562, 571, 572, 581, and 582 represent the respective transmission area.
[0054] 1100: ESD protection layout area, 1200: Fill structure layout area, 1300: Connector pads;
[0055] 5100: First transmission sub-layout area, 5200: Second transmission sub-layout area, 5300: Third transmission sub-layout area, 5400: Transmission pad;
[0056] 5310: Independent substrate region, 5320: First well region, 5330: Second well region, 5340: Isolation band. Detailed Implementation
[0057] This application will now be described more fully below with reference to the accompanying drawings. However, this application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided herein to make this application more detailed and complete. The same reference numerals denote the same objects throughout the drawings.
[0058] In the specification of this application, when a component / module / unit is referred to as being "connected to" other components / modules / units relative to them, such as "connected to" other components / modules / units, the component / module / unit can be directly connected to or directly coupled to other components / modules / units, or there may be an intervening third component / module / unit; in addition, in the embodiments of this application, "connection" mainly refers to electrical connection, and "adjacent" or "adjacent" means that two layout areas are connected to each other, or that two layout areas are directly close to each other (excluding a third layout area between them) and separated by a preset distance.
[0059] To more fully disclose this application, the working principle of the bus transceiver involved in the embodiments is explained below.
[0060] The bus transceiver provided in this embodiment is typically a directional controllable dual-power eight-channel tri-state output bus transceiver capable of connecting to two independent power supplies. Its internal level-shifting structure can convert high-voltage signals to low-voltage signals or vice versa, allowing it to connect devices with different voltages and ensuring data transmission compatibility. Furthermore, the aforementioned bus transceiver can provide sufficient current and power, thus it can be used as a driver to drive larger loads and long-distance transmissions.
[0061] Refer to the logic diagram of the dual-power eight-channel tri-state output bus transceiver: Figure 1 As shown, the bus transceiver includes a control module and multiple sets of bidirectional transmission modules. Furthermore, it has two control ports and eight pairs of bidirectional transmission ports, with the control ports being enable control ports. The system includes a direction control port DIR and eight pairs of bidirectional transmission ports, namely A1 and B1 to A8 and B8.
[0062] Each of the aforementioned bidirectional transmission ports can be used as either a data input port or a data output port. For the same pair of bidirectional transmission ports, if one of them is used as a data input port, then the other will be used as a data output port, and vice versa.
[0063] The control module in the bus transceiver provided in the embodiment further includes an enable control module and a direction control module, wherein the enable control module controls whether the chip works, and the direction control module controls the data transmission direction of the chip.
[0064] The control module receives external control signals, such as those from the enable control terminal or the direction control terminal. After logical processing, it generates enable control signals and direction control signals, respectively. The enable control signals and direction control signals are then sequentially transmitted to multiple sets of bidirectional transmission modules to control the operation of each set of bidirectional transmission modules.
[0065] As a tri-state output bus controller, it has tri-state output capability, which means that it can output a high level, a low level, or remain in a high-impedance state (i.e., not drive a signal). This allows multiple devices to share the same bus without interfering with each other.
[0066] Therefore, for the bidirectional transmission module, when the enable control signal is high, the module outputs a high-impedance state (i.e., no driving signal) regardless of the direction control signal's state. When the enable control signal is low, if the direction control signal is high, the data is transmitted from port An through the bidirectional transmission module to port Bn; if the direction control signal is low, the data is transmitted from port Bn through the bidirectional transmission module to port An.
[0067] Furthermore, since the bus transceiver in the embodiment is connected to two power supplies, it has multiple regions with different well voltages, especially the regions connected to the first power supply voltage and the second power supply voltage respectively, forming unequal potential wells. These regions must be isolated by an isolation structure, which inevitably increases the area of the chip.
[0068] Furthermore, the chip needs to have both cold and hot backup functions. Specifically, when both power supply voltages are zero simultaneously, the bus transceiver functions as a cold backup protection circuit; when one power supply is powered on and the other is zero, the bus transceiver functions as a hot backup protection circuit. Both cold and hot backup protection circuits provide electrical isolation and reduce power consumption, preventing damage to the chip due to power loss. Therefore, the bus transceiver chip requires an independent substrate structure.
[0069] Specifically, in cold or hot backup mode, when the circuit is completely or partially powered off, an independent substrate is needed to block the path from the interface to the power supply, so as to prevent the current of the interface signal from flowing back to the power supply pin, which could lead to signal loss, increased power consumption, or even chip damage.
[0070] However, using a separate substrate also wastes chip area, leading to increased manufacturing costs and application limitations.
[0071] In view of the aforementioned issues with bus transceivers, such as the need for an independent substrate to achieve both cold / hot backup functionality and the increased chip area caused by the isolation requirements between unequal potential wells for connecting multiple power supplies, embodiments of this application provide a layout structure for a bus transceiver, as follows: Figure 2 As shown, it includes:
[0072] The system includes multiple signal input layout areas 100, multiple power supply layout areas 200, multiple ground layout areas 300, at least one control module layout area 400, and multiple sets of transmission layout areas 500 arranged along a first direction, wherein each set of transmission layout areas includes two transmission layout areas arranged along a second direction and centrally symmetrical.
[0073] For example, Figure 2The transmission layout areas 511 and 512 shown are considered as one group of transmission layout areas. Similarly, transmission layout areas 521 and 522 are considered as another group of transmission layout areas. Figure 2 In the typical embodiment shown, there are 8 groups of 16 transmission layout areas.
[0074] It should be understood that the first direction and the second direction described in the embodiments are both Figure 2 The reference directions indicated in the diagram are typically the first and second directions, which are orthogonal to each other.
[0075] Specifically, such as Figure 2 As shown, the multiple transmission layout areas 500 include eight groups arranged along a first direction (lateral direction). Each group includes two transmission layout areas arranged vertically. These two transmission layout areas have the same structure and are centrally symmetrical, as shown below. Figure 6 As shown.
[0076] In a typical embodiment, multiple transmission layout areas 500 are arranged in a dense array of 2 rows and 8 columns. This facilitates the sequential transmission of control signals from the control module layout area 400 to each transmission layout area along the first direction (lateral direction), and the neat arrangement from left to right avoids area waste caused by different position heights and area occupation caused by excessively long signal transmission lines or too many bends.
[0077] like Figure 4 As shown, each transmission layout area includes a first transmission sub-layout area 5100, a second transmission sub-layout area 5200, and a third transmission sub-layout area 5300 arranged sequentially from the outer side to the inner side of the chip along the second direction, as well as a transmission pad 5400.
[0078] The entire transmission layout area is elongated, which makes the array of multiple transmission layout areas more regular, which is conducive to the compact arrangement of the array, thereby saving chip area and achieving miniaturization.
[0079] The first transmission sub-layout area 5100 and the second transmission sub-layout area 5200 are provided with switching devices (such as MOSFETs) or circuit structures to resist electrostatic interference. The third transmission sub-layout area 5300 is provided with a transmission structure, and further includes the following layout structure / region:
[0080] Independent substrate region 5310, such as Figure 5 As shown, the second transport sub-layout area 5200 is adjacent to and shares a substrate. In other words, the independent substrate structure existing in the third transport sub-layout area 5300 is concentrated in the independent substrate area 5310. The independent substrate area 5310 and the second transport sub-layout area 5200 have the same substrate. When laying out, the two are arranged close together, which can save space and reduce interconnects.
[0081] First well region 5320 and second well region 5330, as Figure 5 As shown, it is disposed at both ends of the third transmission sub-layout area 5300 along the first direction, that is, on the left and right sides of the sub-layout area, as follows. Figure 6 As shown, the first well region 5320 and the second well region 5330 in the same group of transmission layout areas are respectively adjacent to each other. In other words, since the two transmission layout areas in the same group are centrally symmetrical, the left and right positions of the first well region 5320 and the second well region 5330 in these two transmission layout areas are opposite, with the first well region 5320 in the upper transmission layout area closely adjacent to the second well region 5330 in the lower transmission layout area.
[0082] In a preferred embodiment, the widths (dimensions along the first direction) of the first well region 5320 and the second well region 5330 should be equal to ensure that the first well region 5320 and the second well region 5330 in the same group of two transmission layout regions can be accurately aligned.
[0083] Furthermore, within the same group of transmission layout areas, adjacent first and second well regions are connected to the same power supply voltage, i.e., as shown below. Figure 6 As shown, the second well region 5330 in the upper transmission layout area is adjacent to the first well region 5320 in the lower transmission layout area, and both have a well voltage of VCCB; similarly, the first well region 5320 in the upper transmission layout area is adjacent to the second well region 5330 in the lower transmission layout area, and both have a well voltage of VCCA; it can be seen that the well voltages of adjacent sub-regions in the upper and lower (same group) transmission layout areas are the same. In this way, the upper and lower (same group) transmission layout areas can be closely fitted, and there is no need to set an isolation structure between them, which effectively reduces the waste of chip vertical space.
[0084] It should be understood that the aforementioned VCCA and VCCB simply represent two different voltages.
[0085] The first well region 5320, the second well region 5330, and the independent substrate region 5310 all have different well voltages, forming three unequal potential wells. To save chip area, the devices should be arranged as closely as possible, which results in a small spacing between the unequal potential wells. Therefore, in a preferred embodiment, an isolation band 5340 (or isolation ring) is also included. The location of the isolation band 5340 is determined by… Figure 5 , Figure 6 The thick black line indicates that, specifically, it can be set in at least one of the following locations, or in all of the following locations, or in some of them:
[0086] The second transport sub-pattern area 5200 is adjacent to the first well area 5320 or the second well area 5330; the independent substrate area 5310 is between the first well area 5320 or the second well area 5330; the two ends of the first well area 5320 along the first direction; the two ends of the second well area 5330 along the first direction.
[0087] Given that the trap voltages of adjacent sub-regions in the upper and lower (same group) transmission layout areas are the same in the aforementioned technical solution, the isolation band 5340 does not need to be set between the two upper and lower (same group) transmission layout areas to reduce processes and save chip area.
[0088] In an embodiment, such as Figure 5 As shown, the independent substrate region 5310 is adjacent to either the first well region 5320 or the second well region 5330. Typically, the independent substrate region 5310 is rectangular, adjacent to the second transport sub-pattern region 5200 above and sharing the same substrate, and adjacent to the first well region 5320 below. Due to the different well voltages of the two regions, an isolation band 5340 is provided between the independent substrate region 5310 and the first well region 5320.
[0089] In an optional embodiment, the first transmission sub-layout area 5100 is provided with an output NMOS transistor and an ESD (Electrostatic Discharge) protection structure; the second transmission sub-layout area 5200 is provided with an output PMOS transistor; as shown Figure 4 As shown, the transfer pad 5400 covers at least a portion of the first transfer sub-layout area 5100 and the second transfer sub-layout area 5200, so that it does not occupy space alone and saves chip area.
[0090] In an optional embodiment, one or more of the plurality of signal input layout areas 100, the plurality of power supply layout areas 200, and the plurality of ground layout areas 300 include, for example: Figure 3 The structure shown includes an ESD protection layout area 1100 and a fill structure layout area 1200, with the fill structure layout area 1200 containing a dummy structure for chip planarization; and a connection pad 1300 covering at least a portion of the ESD protection layout area 1100 and the fill structure layout area 1200, without occupying separate space, thus greatly reducing the chip area and saving costs.
[0091] In the embodiments, the circuit structure or the ESD protection structure set in the aforementioned ESD protection layout area can be, for example, a diode (string), an SCR, a MOSFET-based structure, a TVS diode, etc., and this application does not make specific limitations.
[0092] Preferably, as a dual-power bus transceiver chip, in multiple power supply layout areas 200, a portion of the power supply layout area's connection pads are used to connect to the first power supply VCCA, and another portion of the power supply layout area's connection pads are used to connect to the second power supply VCCB; for example... Figure 6As shown, in the same group of transmission layout areas, the first well area and the second well area located on one side and adjacent to each other are connected to the first power supply VCCA, and the first well area and the second well area located on the other side and adjacent to each other are connected to the second power supply VCCB.
[0093] In a preferred embodiment, such as Figure 2 As shown, multiple sets of transmission layout areas 500 are concentrated in the middle area of the chip layout, and their bidirectional transmission ports (and corresponding pads PAD) A1~A8, B1~B8 are arranged on the upper and lower edges of the chip respectively; while the power layout area 200 and the ground layout area 300 are respectively located at both ends of the chip along the first direction (left and right).
[0094] Furthermore, the signal input layout area 100 is positioned on the same side as the power supply layout area 200, and the control module layout area 400 is positioned close to the signal input layout area 100 to facilitate wiring and shorten signal paths.
[0095] In a typical embodiment, such as Figure 2 As shown, multiple power supply layout areas 200 are disposed at one end (left end) of the chip along the first direction, including a first power supply layout area 210, a second power supply layout area 220 and a third power supply layout area 230;
[0096] Along the second direction, the first power supply layout area 210 and the third power supply layout area 230 are located on both sides (above and below) of the chip, and the second power supply layout area 220 is located in the middle of the chip.
[0097] The connection pads in the first power supply layout area 210 and the second power supply layout area 220 are used to connect the second power supply, and the connection pads in the third power supply layout area 230 are used to connect the first power supply.
[0098] Typically, the second power supply layout area 220 is located on the central symmetrical line of the chip's transverse direction. The second power supply layout area 220 is located at the left edge of the chip and contains pads for connecting the second power supply VCCB, which are also located on the left edge of the chip. The first power supply layout area 210 is spaced apart from the left edge of the chip and located at the top edge of the chip, where the pads for connecting the second power supply VCCB are located at the top edge of the chip. Similarly, the third power supply layout area 230 is spaced apart from the left edge of the chip and located at the bottom edge of the chip, where the pads for connecting the first power supply VCCA are located at the bottom edge of the chip. This arrangement allows the bonding wires connecting the three power supply layout areas to connect to the pads in the power supply layout areas from above, left, and bottom, respectively, maintaining sufficient distance from each other to avoid interference.
[0099] In a typical embodiment, such as Figure 2As shown, the multiple signal input layout areas 100 include: an enable signal input layout area 110 disposed along the second direction on both sides of the chip, disposed between the first power layout area 210 and the transmission layout area; and a direction signal input layout area 120 disposed between the third power layout area 230 and the transmission layout area.
[0100] The enable signal input layout area 110 is used to receive the enable signal, is located at the upper edge of the chip, and has pads for inputting the enable signal; the direction signal input layout area 120 is located at the lower edge of the chip and has pads for inputting the direction signal.
[0101] In alternative embodiments, such as Figure 2 As shown, multiple grounding layout areas 300 are disposed at one end (right end) of the chip away from multiple power supply layout areas 200 along a first direction, including a first grounding layout area 310, a second grounding layout area 320 and a third grounding layout area 330; along a second direction, the first grounding layout area 310 and the third grounding layout area 330 are disposed on both sides of the chip, and the second grounding layout area 320 is disposed in the middle of the chip.
[0102] Typically, multiple grounding layout areas 300 are arranged symmetrically with the power layout area 200. The second grounding layout area 320 is located on the central symmetry line of the chip's horizontal direction. The first grounding layout area 310 and the first power layout area 210, and the third grounding layout area 330 and the third power layout area 230 are arranged symmetrically on the left and right sides, respectively.
[0103] In a typical embodiment, such as Figure 2 The control module layout area 400 is disposed between the second power supply layout area 220 and the transmission layout area, and further includes an enable control module layout area 410 and a direction control module layout area 420.
[0104] The enable control module layout area 410 and the direction control module layout area 420 are adjacent to each other and symmetrical about the first direction. The enable control module layout area 410 is set close to the enable signal input layout area 110, and the direction control module layout area 420 is set close to the direction signal input layout area 120.
[0105] In summary, the aforementioned embodiments address the situation where there are independent substrates in the product. By rationally arranging all devices with the same independent substrate together, the aim is to save space and reduce interconnections. For the case of unequal potential wells in dual-power products, isolation is achieved by adding isolation bands. Furthermore, at least some adjacent well regions can be connected to the same voltage, thus eliminating the need for isolation. While ensuring the correctness, reliability, and stability of chip functions, the overall chip size is also minimized and miniaturized.
[0106] The above description is only a partial embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A layout structure of a bus transceiver, characterized by, The chip includes a plurality of signal input layout regions (100), a plurality of power supply layout regions (200), a plurality of ground layout regions (300), at least one control module layout region (400), and a plurality of groups of transmission layout regions (500) arranged along a first direction, any one group of transmission layout regions including two transmission layout regions arranged along a second direction and being center-symmetric; The transmission layout region includes, along the second direction, a first transmission sub-layout region (5100), a second transmission sub-layout region (5200), and a third transmission sub-layout region (5300) arranged in sequence from the outer side to the inner side of the chip, and a transmission pad (5400); The third transmission sub-layout region (5300) is provided with a transmission structure and includes: An independent substrate region (5310) adjacent to the second transmission sub-layout region (5200) and sharing a substrate; A first well region (5320) and a second well region (5330) arranged at both ends of the third transmission sub-layout region (5300) along the first direction and respectively adjacent to the second well region and the first well region in the same group of transmission layout regions; In the same group of transmission layout regions, the adjacent first well region and second well region are connected to the same power supply voltage.
2. The layout structure of claim 1, wherein, Further comprising an isolation belt (5340) arranged at at least one of: The adjacent place between the second transmission sub-layout region (5200) and the first well region (5320) or the second well region (5330); Between the independent substrate region (5310) and the first well region (5320) or the second well region (5330); Both ends of the first well region (5320) along the first direction; Both ends of the second well region (5330) along the first direction.
3. The layout structure according to claim 1 or 2, wherein, The independent substrate region (5310) is adjacent to the first well region (5320) or the second well region (5330).
4. The layout structure of claim 1 or 2, wherein, The first transmission sub-layout region (5100) is provided with an output NMOS tube and an ESD protection structure; the second transmission sub-layout region (5200) is provided with an output PMOS tube; and the transmission pad (5400) covers at least part of the first transmission sub-layout region (5100) and the second transmission sub-layout region (5200) above.
5. The layout structure of claim 1 or 2, wherein, One or more of the plurality of signal input layout regions (100), the plurality of power supply layout regions (200), and the plurality of ground layout regions (300) includes the following structure: An ESD protection layout region (1100) and a filling structure layout region (1200); A connection pad (1300) covering at least part of the ESD protection layout region (1100) and the filling structure layout region (1200) above.
6. The layout structure of claim 5, wherein, In the plurality of power supply layout regions (200), the connection pads of a part of the power supply layout regions are used to connect a first power supply, and the connection pads of another part of the power supply layout regions are used to connect a second power supply; In the same group of transmission layout regions, the first well region and the second well region adjacent to each other on one side are connected to the first power supply, and the first well region and the second well region adjacent to each other on the other side are connected to the second power supply.
7. The layout structure of claim 6, wherein, The plurality of power layout regions (200) are arranged at one end of the chip along a first direction, and include a first power layout region (210), a second power layout region (220), and a third power layout region (230); Along a second direction, the first power layout region (210) and the third power layout region (230) are arranged at two sides of the chip, and the second power layout region (220) is arranged at a middle part of the chip. The connection pads in the first power layout region (210) and the second power layout region (220) are used for connecting a second power, and the connection pads in the third power layout region (230) are used for connecting a first power.
8. The layout structure of claim 7, wherein, The plurality of signal input layout regions (100) include: An enable signal input layout region (110) arranged between the first power layout region (210) and the transmission layout region; A direction signal input layout region (120) arranged between the third power layout region (230) and the transmission layout region.
9. The layout structure of claim 7, wherein, The plurality of ground layout regions (300) are arranged at an end of the chip away from the plurality of power layout regions (200) along the first direction, and include a first ground layout region (310), a second ground layout region (320), and a third ground layout region (330); Along the second direction, the first ground layout region (310) and the third ground layout region (330) are arranged at two sides of the chip, and the second ground layout region (320) is arranged at a middle part of the chip.
10. The layout structure of claim 8, wherein, The at least one control module layout region (400) is arranged between the second power layout region (220) and the transmission layout region, and includes an enable control module layout region (410) and a direction control module layout region (420); The enable control module layout region (410) and the direction control module layout region (420) are adjacent to each other and are symmetric about the first direction, the enable control module layout region (410) is arranged close to the enable signal input layout region (110), and the direction control module layout region (420) is arranged close to the direction signal input layout region (120).