Switching power supply and average current sampling circuit thereof

Abstract

The utility model discloses a switching power supply and an average current sampling circuit thereof, and the circuit comprises a real-time current sampling circuit (1) which samples the real-time current flowing through an upper switch (NM1) / lower switch (NM2); a holding signal generation circuit (3) for generating the holding signal at more than half of the time of each conduction period of a first control signal / a second control signal on the basis of the first control signal of the upper switch (NM1) / the second control signal of the lower switch (NM2), the conduction period being a time period in which the control signal controls the corresponding switch to be conducted; the sampling and holding circuit (2) is used for receiving the holding signal and holding and outputting the current sampled by the real-time current sampling circuit (1) at the half conduction period moment; according to the utility model, the sampling current is enough for the establishment of a sampling circuit from the inductive current at the beginning of the sampling conduction period to the more than half time of the conduction period, thereby avoiding the error caused by the establishment time, and achieving the more accurate inductive average current sampling.

Description

Technical Field

[0001] This utility model relates to the field of switching power supplies, and in particular to a switching power supply and its average current sampling circuit. Background Technology

[0002] During the operation of a switching power supply, it is necessary to sample its output current. For a specific switching power supply architecture, such as a DC-DC-BUCK controller, the inductor current is the output current; sampling the average inductor current yields the output current. Taking a DC-DC-BUCK switching power supply controller as an example, its schematic circuit diagram is as follows: Figure 1 As shown. In T ON During phase T, K1 is closed, K2 is open, and the current in inductor L increases. OFF During this phase, K2 is closed and K1 is open, causing the current in inductor L to decrease. The operating state of the BUCK switching power supply controller is determined by the output current. From smallest to largest output current, the operating states are DCM, BCM, and CCM, respectively. A schematic diagram of the inductor current is shown below. Figure 2 As shown. In the DCM state, at T ON During this phase, K1 is closed and K2 is open, and the current in inductor L rises from 0 to I. L1 In T OFF During this phase, K2 is closed and K1 is open, and the current in inductor L flows from I... L1 Decreased to 0. T DCM During this phase, both K1 and K2 are open, and the current in inductor L remains zero. In the BCM state, at T... ON During this phase, K1 is closed and K2 is open, and the current in inductor L rises from 0 to I. L1 In T OFF During this phase, K2 is closed and K1 is open, and the current in inductor L flows from I... L1 Drop to 0, T DCM =0. In the CCM state, at T ON During this phase, K1 is closed and K2 is open, and the current in inductor L flows from I... L1 Start rising to I L2 In T OFF During this phase, K2 is closed and K1 is open, and the current in inductor L flows from I... L2 Drop to I L1 T DCM =0.

[0003] Currently, the commonly used method for sampling output current is to use an external current sensing resistor, such as... Figure 3 As shown, the output current (IO) is detected by sensing the voltage drop (VRs) across the resistor Rs. While this method can directly sample the output current, it requires an additional sensing resistor Rs and a separate sensing pin to detect the voltage VRs across Rs. This extra pin reduces the chip's versatility.

[0004] Another output current sample can be taken by sampling the inductor current at T ON and T OFF , respectively, and then summing them to get the average inductor current. For a BUCK switching power supply controller, the inductor current is the output current. In actual chip design, K1 will be replaced by a PMOS / NMOS, and K2 will be replaced by an NMOS. The difference between K1 and K2 and the design of the sampling circuit will inevitably cause a deviation in the sampling ratio, resulting in sampling error. At the same time, the sampling must be taken at T ON and T OFF , respectively, and there will inevitably be a setup time. The sampled current will further deviate, and the sampling schematic is shown in Figure 4 .

[0005] The above information disclosed in the background section is only included to enhance the understanding of the background of the present disclosure, and therefore can contain information that is not prior art known to those of ordinary skill in the art at the time of the present disclosure. Utility Model Content

[0006] The technical problem to be solved by the utility model is to provide a switching power supply and an average current sampling circuit thereof for the above defects of the prior art.

[0007] The utility model adopts the technical scheme in solving its technical problems:

[0008] On the one hand, a switching power supply average current sampling circuit is constructed, which comprises:

[0009] A real-time current sampling circuit, the input end of which is connected with the two ends of the upper switch / lower switch of the switching power supply, for sampling the real-time current flowing through the upper switch / lower switch;

[0010] A hold signal generation circuit, for generating the hold signal at more than half of the conduction period of the first control signal of the upper switch / second control signal of the lower switch based on the first control signal / second control signal, wherein the conduction period refers to the time period during which the control signal controls the conduction of the corresponding switch;

[0011] A sample-and-hold circuit, the control end of which is connected with the hold signal generation circuit, and the input end of which is connected with the output end of the real-time current sampling circuit, for receiving the current at the half conduction period of the upper switch / lower switch sampled by the real-time current sampling circuit, holding and outputting it.

[0012] Further, the switch power supply average current sampling circuit further comprises a mode detection circuit, an input end of the mode detection circuit is connected with an output end of the sampling holding circuit, the mode detection circuit is used for outputting a current held by the sampling holding circuit in a working time period of a switching cycle of the switch power supply, and outputting zero current in a non-working time period of the switching cycle of the switch power supply.

[0013] Further, the switch power supply average current sampling circuit further comprises a current-voltage conversion circuit, an input end of the current-voltage conversion circuit is connected with an output end of the mode detection circuit, the current-voltage conversion circuit is used for converting the current output by the mode detection circuit into a voltage and outputting the voltage to a controller of the switch power supply.

[0014] Further, the switch power supply average current sampling circuit further comprises a current-voltage conversion circuit, an input end of the current-voltage conversion circuit is connected with an output end of the mode detection circuit, the current-voltage conversion circuit is used for converting the current output by the mode detection circuit into a voltage and outputting the voltage to a controller of the switch power supply.

[0015] The positive and negative input ends of the sampling circuit are connected with two ends of the upper switch / lower switch of the switch power supply, the sampling circuit is used for sampling a voltage at the two ends of the upper switch / lower switch and converting the voltage into a current flowing through a control tube of the current mirror, and a mirror tube of the current mirror outputs a current to the sampling holding circuit.

[0016] Further, the switch power supply average current sampling circuit further comprises a current-voltage conversion circuit, an input end of the current-voltage conversion circuit is connected with an output end of the mode detection circuit, the current-voltage conversion circuit is used for converting the current output by the mode detection circuit into a voltage and outputting the voltage to a controller of the switch power supply.

[0017] The current input circuit is used for converting the current output by the real-time current sampling circuit into a first charging voltage to charge the first capacitor; the first switch control end receives a third control signal, and is used for controlling whether the first charging voltage charges the first capacitor based on the third control signal; the second switch control end receives a fourth control signal, and is used for controlling whether the first capacitor charges the second capacitor to realize energy transfer based on the fourth control signal; and the current output circuit is used for converting the voltage of the second capacitor into a current output.

[0018] Further, the switch power supply average current sampling circuit, the switch period of the first switch, the second switch, the upper switch and the lower switch is same, the starting moment of the conduction period of the first switch is synchronous with the starting moment of the conduction period of the upper switch / lower switch, the ending moment of the conduction period of the first switch corresponds to the half moment of the conduction period of the upper switch / lower switch, the starting moment of the conduction period of the second switch lags behind the ending moment of the conduction period of the first switch by a dead zone, and the ending moment of the conduction period of the second switch is synchronous with the ending moment of the conduction period of the upper switch / lower switch.

[0019] Correspondingly, the third control signal and the fourth control signal are same frequency with the first control signal and the second control signal;

[0020] The first level mutation edge of the third control signal is synchronous with the first level mutation edge of the first control signal / second control signal, and the second level mutation edge of the third control signal is half of the conduction period of the upper switch / lower switch ahead of the second level mutation edge of the first control signal / second control signal; the signal between the second level mutation edge of the third control signal and the next first level mutation edge is the holding signal;

[0021] The first level mutation edge of the fourth control signal lags behind the second level mutation edge of the third control signal by a dead zone, and the second level mutation edge of the fourth control signal is synchronous with the second level mutation edge of the first control signal / second control signal;

[0022] The first level mutation edge and the second level mutation edge appear at the starting moment and the ending moment of the conduction period of the corresponding switch respectively.

[0023] Further, the switch power supply average current sampling circuit, the current input circuit comprises a first NMOS tube, the source electrode thereof is grounded, the drain electrode thereof is connected with the current output by the real-time current sampling circuit, the drain electrode thereof is also connected with the gate electrode thereof, the gate electrode thereof is connected with the positive electrode of the first capacitor through the first switch, and the negative electrode of the first capacitor is grounded.

[0024] The current output circuit comprises a second NMOS tube, the source electrode of the second NMOS tube is grounded, the drain electrode of the second NMOS tube outputs current, the gate electrode of the second NMOS tube is connected with the positive electrode of the second capacitor, the negative electrode of the second capacitor is grounded, and the positive electrode of the second capacitor is also connected with the positive electrode of the first capacitor through the second switch.

[0025] Further, the mode detection circuit comprises a third switch and a fourth switch, one end of the third switch is connected to the current output by the sample-and-hold circuit, one end of the fourth switch is connected to zero current, and the other end of the third switch and the other end of the fourth switch are commonly connected as an output end of the mode detection circuit.

[0026] The switch periods of the third switch, the fourth switch, the upper switch and the lower switch are the same, the starting moment of the conduction period of the third switch is synchronized with the starting moment of the conduction period of the upper switch, and the ending moment of the conduction period of the third switch corresponds to the ending moment of the conduction period of the lower switch, and the switch state of the fourth switch is opposite to that of the third switch.

[0027] The third switch control end receives a fifth control signal, the fourth switch control end receives a sixth control signal, the fifth control signal and the sixth control signal are the same frequency as the first control signal and the second control signal, the first level mutation edge of the fifth control signal is synchronized with the first level mutation edge of the first control signal, the second level mutation edge of the fifth control signal is synchronized with the second level mutation edge of the second control signal, the first level mutation edge of the sixth control signal is synchronized with the second level mutation edge of the second control signal, and the second level mutation edge of the sixth control signal is synchronized with the first level mutation edge of the first control signal.

[0028] The first level mutation edge and the second level mutation edge appear at the starting moment and the ending moment of the conduction period of the corresponding switch, respectively.

[0029] Further, the current-voltage conversion circuit comprises a first resistor, a second resistor and a third capacitor, one end of the first resistor is connected to the current output by the mode detection circuit, and the positive electrode of the third capacitor is connected via the second resistor, the other end of the first resistor is grounded, the negative electrode of the third capacitor is grounded, and the positive electrode of the third capacitor outputs a voltage to the controller of the switching power supply.

[0030] In a second aspect, a switching power supply is constructed, which comprises an upper switch and a lower switch connected in series between the positive electrode and the negative electrode of an input voltage, and the average current sampling circuit as described in any one of the preceding aspects.

[0031] The switching power supply and its average current sampling circuit of this invention have the following advantages: This invention uses a real-time current sampling circuit to sample the real-time current flowing through the upper or lower switch of the switching power supply, and uses a sample-and-hold circuit to hold the current at the halfway point of each conduction cycle of the upper or lower switch. The current at this moment is equivalent to the average inductor current, thus realizing the sampling of the average inductor current of the system. The sampling current, from the inductor current at the beginning of the sampling conduction cycle to the halfway point of the conduction cycle, is sufficient for the sampling circuit to be established, avoiding errors caused by the setup time and achieving more accurate sampling of the average inductor current. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of the BUCK switching power supply controller;

[0034] Figure 2 This is a schematic diagram of the inductor current in different modes of the BUCK switching power supply controller;

[0035] Figure 3 This is a schematic diagram of a sampling scheme for the output current of a BUCK switching power supply controller;

[0036] Figure 4 This is a schematic diagram of current sampling during the ON and OFF phases of an alternative sampling scheme for the output current of a BUCK switching power supply controller.

[0037] Figure 5 This is a schematic diagram of the BUCK switching power supply controller;

[0038] Figure 6 This is a schematic diagram of the inductor current in the DCM of the BUCK switching power supply controller;

[0039] Figure 7 This is a schematic diagram of the inductor current in the BUCK switching power supply controller BCM.

[0040] Figure 8 This is a schematic diagram of the CCM inductor current of the BUCK switching power supply controller;

[0041] Figure 9 This is a circuit block diagram of a specific embodiment of the average current sampling circuit for a switching power supply of this utility model;

[0042] Figure 10 is a circuit structure of a real-time current sampling circuit and a functional schematic diagram thereof;

[0043] Figure 11 is a voltage waveform diagram of T OFF / 2 generated by a hold signal generation circuit;

[0044] Figure 12 is a circuit structure of a sample-and-hold circuit and a functional schematic diagram thereof;

[0045] Figure 13 is a circuit schematic diagram of a mode detection circuit and a functional schematic diagram thereof;

[0046] Figure 14 is a circuit schematic diagram of a current-voltage conversion circuit and a functional schematic diagram thereof. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The drawings show typical embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, and are not limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0048] Taking a BUCK switching power supply as an example. In an ideal state, the switching period of the BUCK switching power supply controller follows the following four formulas:

[0049] ……(1);

[0050] ……(2);

[0051] ……(3);

[0052] ……(4);

[0053] T represents the switching period of the switching power supply, which can also be called the working period, which is composed of a working time period and a non-working time period, T DCM , i.e. the non-working time period, T PWM , i.e. the working time period, T ON is the on period of the upper switch, T OFF is the on period of the lower switch, and the working time period is from T ON to T OFF . VIN is an input voltage, V OUT is an output voltage.

[0054] In determining T PWM , V OUT and V IN determine T ON and T OFF . The general idea of the utility model is: through sampling the real-time inductance current of T OFF stage (or T ON stage) and keeping the inductance current at T OFF / 2 (or T ON / 2 ) moment to equivalent average inductance current, the sampling of system inductance average current is realized. The inductance current at T OFF (or T ON ) moment is sampled, and the establishment of the sampling circuit at T OFF / 2 (or T ON / 2 ) moment is enough. The error caused by the establishment time is avoided. The more accurate inductance average current sampling is realized.

[0055] The switching power average current sampling circuit of the utility model takes a DCDC BUCK switching power controller as an example. The schematic circuit diagram is shown in Figure 1 . In actual chip design, K1 will be replaced by PMOS / NMOS. K2 will be replaced by NMOS. In the embodiment, K1 is replaced by NMOS NM1, and D1 is the parasitic substrate diode thereof. K2 is replaced by NMOS NM2, and D2 is the parasitic substrate diode thereof. The schematic diagram is shown in Figure 5 . The BUCK switching power controller is according to the load current I O from small to large, and sequentially DCM, BCM and CCM.

[0056] When working in DCM, the control signal of NM1 and NM2 and the inductance current I L waveform are shown in Figure 6 . In T ON stage, NM1 is opened, NM2 is closed, and the inductance current rises from 0 to I L1 . Generally, in order to avoid that NM1 and NM2 are simultaneously turned on, leading to large current from V IN to ground. When NM1 is closed, NM2 will not be opened immediately, but will be opened after the dead time T DE . In T DE stage, NM1 and NM2 are both closed, at this time, the inductance current flows through D2. Generally, the time length of T DE is far less than T ON / T OFF , and when analyzing, T DE=0. T OFF During this phase, NM1 is off, NM2 is on, and the current flows from I... L1 Drops to 0. In T OFF After the phase, the system will not immediately enter T. ON It's not about the stage, but about waiting for T. DCM Then proceed to the next T ON T DCM During this phase, both NM1 and NM2 remain off, and the inductor current is 0. DCM The length depends on the output current I O The magnitude of the output current I. O The smaller, T DCM The longer. The entire T PWM The average inductor current during the period is:

[0057] ... (5);

[0058] I L1 / 2 is T ON / 2 or T OFF The inductor current at time 2 / 2, from Figure 6 It can also be intuitively seen that the area of ​​the shaded region is 1. a =1 b ,2 a =2 b 1 a +2 a +1 c =1 b +2 b +1 c Therefore, by sampling T ON / 2 or T OFF The inductor current at time / 2 can be used to obtain T. PWM The average inductor current during this phase. The average inductor current over the entire operating cycle is:

[0059] ... (6);

[0060] As long as you get The relationship, through sampling T ON / 2 or T OFF The average inductor current I can be obtained from the inductor current at time / 2. L_AV .

[0061] Under BCM conditions, the control signals and inductor current waveforms of NM1 / NM2 are as follows: Figure 7 As shown. T ON During this phase, NM1 is turned on, NM2 is turned off, and the inductor current rises from 0 to I. L1 Generally, to avoid NM1 / NM2 being turned on simultaneously, causing V to... INA large current is generated to ground. When NM1 is turned off, NM2 does not turn on immediately, but waits for a dead time T. DE Then open NM2. In T DE During this phase, both NM1 and NM2 are off, and the inductor current freewheels through D2. OFF During this phase, NM1 is off, NM2 is on, and the current flows from I... L1 Reduced to 0. Similarly, to avoid NM1 / NM2 conducting simultaneously, it needs to pass through T. DE Then enter T ON Stage. Generally speaking, T DE The design time will be much shorter than T. ON / T OFF In the analysis, we can assume T. DE =0. According to the diagram. Figure 7 It can be intuitively seen that the entire T PWM The average inductor current during the period is:

[0062] ... (7);

[0063] I L1 / 2 is T ON / 2 or T OFF The inductor current at time 2 / 2, from Figure 7 It can also be intuitively seen that the area of ​​the shaded region is 1. a =1 b ,2 a =2 b 1 a +2 a +1 c =1 b +2 b +1 c Therefore, by sampling T ON / 2 or T OFF The inductor current at time / 2 can be used to obtain T. PWM The average inductor current during this phase. The average inductor current over the entire operating cycle is I. L1 / 2 Therefore, by sampling T ON / 2 or T OFF The inductor current at time / 2 can be used to obtain T. PWM The average inductor current during the phase, and the average inductor current I over the entire operating cycle. L_AV For I L1 / 2.

[0064] Under CCM conditions, the control signals and inductor current waveforms of NM1 / NM2 are as follows: Figure 8 As shown. T ON During this phase, NM1 is turned on, NM2 is turned off, and the inductor current changes from I... L1a Upgraded to IL2 Generally, to avoid NM1 / NM2 being turned on simultaneously, causing V to... IN A large current is generated to ground. When NM1 is turned off, NM2 does not turn on immediately, but waits for a dead time T. DE Then open NM2. In T DE During this phase, both NM1 and NM2 are off, and the inductor current freewheels through D2. OFF During this phase, NM1 is off, NM2 is on, and the current flows from I... L2 Down to I L1b Similarly, to prevent NM1 / NM2 from conducting simultaneously, it is necessary to pass through T. DE Then enter T ON Stage. Generally speaking, T DE The design time will be much shorter than T. ON / T OFF In the analysis, we can assume T. DE =0. When the circuit is operating stably, T ON Phase I L2 -I L1a The difference is equal to T OFF Phase I L2 -I L1b , that is I L1a =I L1b According to the diagram Figure 8 It can be intuitively seen that the entire T PWM The average inductor current during the period is:

[0065] ... (8);

[0066] ... (9);

[0067] and That is, T ON / 2 or T OFF The inductor current at time 2. Figure 8 It can be intuitively seen that the area of ​​the shaded region is 1. a =1 b ,2 a =2 b 1 a +2 a +1 c =1 b +2 b +1 c Therefore, by sampling T ON / 2 or T OFF The inductor current at time / 2 can be used to obtain T. PWM The average inductor current during the phase, and the average inductor current I over the entire operating cycle. L_AV for .

[0068] From the above analysis, for CCM and BCM, only the real-time current I ON / 2 or T OFF / 2 is needed to get the average inductor current I L . L_AV For DCM, only the relationship of I is needed to get the average inductor current I L_AV . ON , T OFF , T DCM are internal signals of the switching power supply controller, so they can be obtained by a simple circuit. .

[0069] Referring to Figure 9 , in one embodiment, to sample the average inductor current of the BUCK circuit shown in Figure 5 , the average current sampling circuit of the embodiment includes: a real-time current sampling circuit 1, a sample-and-hold circuit 2, a hold signal generating circuit 3, a mode detecting circuit 4, and a current-voltage converting circuit 5.

[0070] The real-time current sampling circuit 1 is connected to the two ends of the upper switch (NM1) and the lower switch (NM2) of the switching power supply, and is used to sample the real-time current flowing through the upper switch (NM1) or the lower switch (NM2).

[0071] The hold signal generating circuit 3 is used to generate the hold signal based on the first control signal (the PWM (NM1) signal in Figure 6-8 ) of the upper switch (NM1) / the second control signal (the PWM (NM2) signal in Figure 6-8 ) of the lower switch (NM2) at the moment of more than half of the on period of the first control signal / the second control signal (if the first control signal, the moment of more than half of the on period is T ON / 2; if the second control signal, the moment of more than half of the on period is T OFF / 2), wherein the on period refers to the time period during which the control signal controls the corresponding switch to be on; referring to Figure 6-8 , the on period of the first control signal is T ON , and the on period of the second control signal is T OFF .

[0072] Sample-and-hold circuit 2, whose control terminal is connected to the hold signal generation circuit 3, and whose input terminal is connected to the output terminal of the real-time current sampling circuit 1, is used to receive the hold signal and hold and output the current sampled by the real-time current sampling circuit 1 at half the conduction cycle of the upper switch NM1 / lower switch NM2. The switching cycles of the upper switch NM1 and the lower switch NM2 are the same as the length of the switching cycle of the switching power supply, and the conduction cycles of the upper switch NM1 and the lower switch NM2 are T. ON T OFF Conduction period T ON Starting from the most recent conduction period T OFF The on-time T is the end of the operating period of the switching power supply. OFF From the end of the current conduction cycle T to the nearest conduction cycle ON This marks the beginning of the non-operating period for the switching power supply.

[0073] The mode detection circuit 4 has its input terminal connected to the output terminal of the sample and hold circuit 2, and is used to hold the current output of the sample and hold circuit 2 during the working time period of the switching cycle of the switching power supply, and to output zero current during the non-working time period of the switching cycle of the switching power supply.

[0074] The current-to-voltage conversion circuit 5 has its input terminal connected to the output terminal of the mode detection circuit 4, and is used to convert the current output by the mode detection circuit 4 into a voltage output to the controller of the switching power supply.

[0075] With sampling T OFF Taking the inductor current at time / 2 as an example, Figure 9 In the middle, the inductor current I when NM2 is turned on is sampled by real-time current sampling circuit 1. L The signal generation circuit 3 controls the sampling and holding circuit 2 to sample and hold the signal. OFF I at time / 2 L The current is output. The sample-and-hold circuit 2 holds the T value through the mode detection circuit 4 at the CCM and BCM. OFF At time / 2, the current is directly output, at T in DCM. ON +T OFF The stage will hold T by the sample-and-hold circuit 2 OFF At time / 2, the current is directly output, and at T... DCM The output current is 0 at this stage. Finally, the average sampled current is converted into a voltage output through the current-to-voltage conversion circuit 5. It should be noted that this invention is applicable to no specifically designated circuits; it is suitable for any circuit that requires sampling the average inductor current or output current. Here, a DC-DC BUCK switching power supply controller is used as an example for ease of description. For T... ON / 2、T OFF / 2 detection is equivalent; here we only consider T. OFF Take / 2 detection as an example.

[0076] The circuits are described below.

[0077] Specifically, refer to Figure 10 Figure (a) shows the circuit structure diagram, and (b) shows the related waveform schematic. The real-time current sampling circuit 1 includes a sampling circuit and a current mirror. The function of the sampling circuit is to sample NM2 at T OFF Inductor current I during the stage L_TOFF K*I is obtained through sampling L_TOFF Where K < 1. L_TOFF To K*I L_TOFF This function can be achieved through various sampling circuit structures, or similar functions. This is a mature current sampling technology, which will not be described in detail here. The positive and negative input terminals of the sampling circuit are connected to the two ends of the lower switch NM2 of the switching power supply (if sampling T is required). ON At time / 2, the current is changed to be connected to both ends of the upper switch NM1, the voltage across the lower switch NM2 is sampled and converted into the current flowing through the control tube PM1 of the current mirror, and the mirror tube PM2 of the current mirror outputs the current to the sample and hold circuit 2.

[0078] Specifically, refer to Figure 11 The main function of the signal generation circuit 3 is to generate T. OFF The voltage waveform of / 2, T OFF The / 2 waveform is used for the control of sample-and-hold circuit 2. This T... OFF The / 2 waveform is obtained based on the second control signal (i.e., the control signal PWM (NM2) for NM2). Specifically, the duty cycle of PWM (NM2) is halved while keeping the start time of the conduction period unchanged. This waveform transformation can be implemented using various existing circuit structures, so it will not be explained in detail. In other embodiments, if it is necessary to sample the T of NM1... ON At time / 2, if the current is such that the signal generation circuit 3 needs to generate T based on the first control signal PWM (NM1), then... ON / 2 voltage waveform.

[0079] Specifically, refer to Figure 12 The main function of sample-and-hold circuit 2 is to hold T. OFF / 2 of the current. Figure 12 (a) is a circuit structure diagram, and (b) is a related waveform schematic diagram. The sample-and-hold circuit 2 includes a current input circuit composed of a first NMOS transistor NM3, a first switch S1, a first capacitor C1, a second switch S2, a second capacitor C2, and a current output circuit composed of a second NMOS transistor NM4.

[0080] NM3 connects the real-time current sampling circuit 1 and the first capacitor C1, specifically, the source of NM3 is grounded, the drain of NM3 is connected to the output current of the real-time current sampling circuit 1, the drain of NM3 is also connected to its gate, the gate of NM3 is connected to the positive pole of the first capacitor C1 via the first switch S1, and the negative pole of the first capacitor C1 is grounded. The source of NM4 is grounded, the drain of NM4 outputs current, the gate of NM4 is connected to the positive pole of the second capacitor C2, the negative pole of the second capacitor C2 is grounded, and the positive pole of the second capacitor C2 is also connected to the positive pole of the first capacitor C1 via the second switch S2.

[0081] NM3 is used to convert the current output by the real-time current sampling circuit 1 into a first charging voltage to charge the first capacitor C1, and Figure 10 the current is converted into the gate voltage of NM3 by the current mirror of PM1 and PM2, which is the first charging voltage. The control end of the first switch S1 receives a third control signal PWM(S1) for controlling whether the first capacitor C1 is charged by the first charging voltage based on the third control signal PWM(S1); the control end of the second switch S2 receives a fourth control signal PWM(S2) for controlling whether the first capacitor C1 charges the second capacitor C2 based on the fourth control signal PWM(S2), so as to transfer the energy of the first capacitor C1 to the second capacitor C2. NM4 is used to convert the voltage of the second capacitor C2 into current output.

[0082] The switching periods of the first switch S1, the second switch S2, the upper switch NM1 and the lower switch NM2 are the same, the starting time of the conduction period of the first switch S1 is synchronized with the starting time of the conduction period of the upper switch NM1 / lower switch NM2, the ending time of the conduction period of the first switch S1 corresponds to the half time of the conduction period of the upper switch NM1 / lower switch NM2, and the starting time of the conduction period of the second switch S2 lags behind the ending time of the conduction period of the first switch S1 by a dead zone, and the ending time of the conduction period of the second switch S2 is synchronized with the ending time of the conduction period of the upper switch NM1 / lower switch NM2. It can also be understood that the first switch S1 is turned on in the first half of the conduction period of the lower switch NM2, and the second switch S2 is turned on in the second half of the conduction period of the lower switch NM2.

[0083] The waveform of PWM(S1) is as shown in Figure 12 , which is also Figure 11 T OFF / 2 voltage waveform, which is the same frequency as the second control signal PWM(NM2), and the first level mutation edge of the third control signal PWM(S1) is synchronized with the first level mutation edge of the second control signal PWM(NM2) (if T ON / 2, the second level transition edge of the third control signal PWM (S1) needs to be adjusted to be ahead of the second level transition edge of the first control signal PWM (NM1) by half of the on period T OFF / 2, the second level transition edge of the third control signal PWM (S1) needs to be adjusted to be ahead of the second level transition edge of the first control signal PWM (NM1) by half of the on period T ON / 2, the second level transition edge of the third control signal PWM (S1) needs to be adjusted to be ahead of the second level transition edge of the first control signal PWM (NM1) by half of the on period T ON )。

[0084] The first level transition edge and the second level transition edge occur at the start and end of the on period of the corresponding switch, respectively. In this embodiment, the first level transition edge is a rising edge and the second level transition edge is a falling edge. It can be understood that the first level transition edge of the control signal of different switches can be different according to the type of the switch, for example, for NMOS, the first level transition edge of the control signal is a rising edge, while for PMOS, the first level transition edge of the control signal is a falling edge.

[0085] The signal between the second level transition edge of the third control signal PWM (S1) and the next first level transition edge is the holding signal, during which the first switch S1 is off and the capacitor C1 is no longer charged.

[0086] The fourth control signal is shown in the PWM (S2) waveform in Figure 12 , which is the same frequency as the third control signal PWM (S1). The first level transition edge of the fourth control signal PWM (S2) lags behind the second level transition edge of the third control signal PWM (S1) by a dead zone, and the second level transition edge of the fourth control signal PWM (S2) is synchronized with the second level transition edge of the second control signal PWM (NM2) (if T ON / 2 is the current to be sampled, the second level transition edge of PWM (S2) is synchronized with the second level transition edge of the first control signal PWM (NM1)).

[0087] As shown in Figure 12 , the sample and hold circuit 2 samples and holds the current at T OFF / 2, and the current flowing through NM3 is K*I L_TOFF , and the gate voltage of NM3 directly reflects the size of the sampled current. When T OFF starts, S1 is on and S2 is off. When the time comes to T OFFAt time / 2, switches S1 and S2 are closed. At this time, the voltage across capacitor C1 is NM3 at time T. OFF The gate voltage at time / 2. This voltage directly reflects T. OFF K*I at time / 2 L_TOFF After a short dead zone T DES Then, S1 is closed and S2 is opened, transferring the voltage V across C1. SAM Transfer to C2. OFF When the falling edge arrives, S1 and S2 are turned off. After several cycle transitions, V... SAM =V HOLD V HOLD Control NM4, at this time NM4 outputs T. OFF The inductor sampling current at time / 2. If the output current I O Changes will occur after multiple cycles, V HOLD Only then will it be updated to the latest output current I O The corresponding inductor current value at that time. Therefore, V SAM It can reflect the current T in real time OFF The periodic inductor current. And V HOLD Multiple cycles of conversion are required to output the corresponding value. This ensures the stability of the sampled value and prevents large fluctuations. The function of the sample-and-hold circuit can be implemented through various circuit structures and is not limited to these. Figure 12 The circuit shown.

[0088] Specifically, the mode detection circuit 4 refers to Figure 13 , Figure 13 (a) is the circuit schematic, and (b) is the related waveform schematic. The mode detection circuit 4 includes a third switch S3 and a fourth switch S4. One end of the third switch S3 is connected to the drain output current of the NM4 of the sample-and-hold circuit 2, and one end of the fourth switch S4 is connected to zero current. The other ends of the third switch S3 and the other ends of the fourth switch S4 are connected together as the output terminal of the mode detection circuit 4. The switching periods of the third switch S3, the fourth switch S4, the upper switch NM1, and the lower switch NM2 are the same. The start time of the conduction period of the third switch S3 is synchronized with the start time of the conduction period of the upper switch NM1, and the end time corresponds to the end time of the conduction period of the lower switch NM2. The switching state of the fourth switch S4 is opposite to the switching state of the third switch S3.

[0089] The third switch S3 control end receives the fifth control signal PWM(S3), the fourth switch S4 control end receives the sixth control signal PWM(S4), the fifth control signal PWM(S3) and the sixth control signal PWM(S4) are same frequency with the first control signal PWM(NM1) and the second control signal PWM(NM2). The first level mutation direction of the fifth control signal PWM(S3) is synchronous with the first level mutation direction of the first control signal PWM(NM1), the second level mutation direction of the fifth control signal PWM(S3) is synchronous with the second level mutation direction of the second control signal PWM(NM2), the first level mutation direction of the sixth control signal PWM(S4) is synchronous with the second level mutation direction of the second control signal PWM(NM2), the second level mutation direction of the sixth control signal PWM(S4) is synchronous with the first level mutation direction of the first control signal PWM(NM1). In the embodiment, because the third switch S3 and the fourth switch S4 are same type, the fifth control signal PWM(S3) and the sixth control signal PWM(S4) are complementary.

[0090] As Figure 13 , the mode detection circuit 4 functions to open S3, close S4 in the T ON and T OFF phases to output the inductor sampling current output of the T OFF / 2 moment of the sampling holding circuit 2, and in the T DCM phase, close S3, open S4 to output 0 current. For the BCM and CCM, since T DCM =0, the T OFF / 2 moment inductor sampling current output is directly output. For the DCM, the T ON / 2 moment inductor sampling current output in the T OFF and T OFF phases, and 0 current output in the T DCM phase. Since T ON , T OFF , T DCM can be directly obtained in the actual chip circuit. Only simple combination logic is needed to realize this function.

[0091] Specifically, the current-voltage conversion circuit 5 refers to Figure 14 , Figure 14 , (a) is a circuit schematic diagram, and (b) is a related waveform schematic diagram. The current-voltage conversion circuit 5 includes a first resistor R SAM , a second resistor R LPF , and a third capacitor C LPF , one end of the first resistor R SAM is connected to the current output by the mode detection circuit 4, and the third capacitor C LPF is connected through the second resistor RLPF positive electrode of the first resistor R SAM ground, the third capacitor C LPF ground, the third capacitor C LPF positive electrode of the first resistor R AV to the controller of the switching power supply, which represents the sampling result of the final average current.

[0092] As Figure 14 , the function of the current-voltage conversion circuit 5 is to convert the converted current I SAM through R SAM into voltage V AV . For BCM and CCM, the voltage converted by I SAM through R SAM is a DC voltage, which does not need to be filtered. But for DCM, the voltage converted by I SAM through R SAM is a pulse voltage, which must be filtered by R LPF and C LPF to obtain the average value. The larger the time constant of R LPF and C LPF is, the smaller the ripple is, and the output is closer to the average value. But when the output current I O changes, more time is needed to stabilize. The actual circuit design will select a reasonable time constant according to the application requirements. A compromise is made between the ripple and the response time.

[0093] It should be noted that the current at T OFF / 2 in the embodiment is sampled, and the current at T ON / 2 can also be sampled in other embodiments, which needs to be selected according to the actual chip application requirements. The embodiment is only a specific circuit requirement, and the current needs to be converted into voltage. In other embodiments, circuits can be added or removed according to requirements to achieve other purposes, such as dcdc controlled by average current mode, calculation of output power by sampling average current, etc.

[0094] In summary, the switching power supply and the average current sampling circuit thereof have the following beneficial effects: the real-time current sampling circuit is used to sample the real-time current flowing through the upper switch or the lower switch of the switching power supply, the sampling and holding circuit is used to hold the current of the real-time current sampling circuit at the moment when the upper switch or the lower switch is turned on for more than half of each period, the current at this moment is equivalent to the average inductance current, the sampling of the system inductance average current is realized, the inductance current at the beginning of the sampling conduction period is sampled to the moment when the conduction period is more than half, which is enough for the establishment of the sampling circuit, the error caused by the establishment time is avoided, and more accurate inductance average current sampling is realized.

[0095] It should be noted that the switch herein includes various equivalent switch electronic devices, and is not limited to MOS tubes or triodes and the like. The "connection" or "connection" includes not only the direct connection of two entities, but also the indirect connection through other entities with beneficial improvement effect.

[0096] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification of the present application herein is for the purpose of describing specific embodiments only and is not intended to be limiting of the present application.

[0097] The terms including ordinal numbers used in the specification of the present application can be used to explain various constituent elements, but the constituent elements are not limited by the terms. The purpose of using the terms is only to distinguish one constituent element from other constituent elements. For example, the first constituent element can be named as the second constituent element without departing from the scope of the rights of the present application, and similarly, the second constituent element can be named as the first constituent element.

[0098] In the specification provided herein, a large number of specific details are explained. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the present specification.

[0099] Similarly, it should be appreciated that, for the sake of brevity, the description of the exemplary embodiments of the present application herein sometimes omits various features of the present application known to those skilled in the art. In other instances, the description of the exemplary embodiments of the present application has sometimes been state in a way considered to be expedient to facilitate understanding of one or more of the various aspects of the present application. Each claim, by itself, can be considered a separate embodiment of the present application.

[0100] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and the person skilled in the art can design alternative embodiments without departing from the scope of the appended claims. The word "one" or "an" before an element does not exclude the presence of multiple such elements. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

[0101] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments, and the above specific embodiments are only illustrative and not restrictive. The person skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A switching power supply average current sampling circuit, characterized in that, include: The real-time current sampling circuit (1) has its input terminal connected to both ends of the upper switch NM1 / lower switch NM2 of the switching power supply, and is used to sample the real-time current flowing through the upper switch NM1 / lower switch NM2. The holding signal generation circuit (3) is used to generate the holding signal at half time of each conduction cycle of the first control signal / second control signal based on the first control signal of the upper switch NM1 / the second control signal of the lower switch NM2. The conduction cycle refers to the time period during which the control signal controls the corresponding switch to conduct. The sample-and-hold circuit (2) has its control terminal connected to the hold signal generation circuit (3) and its input terminal connected to the output terminal of the real-time current sampling circuit (1). It is used to receive the hold signal to hold and output the current of the upper switch NM1 / lower switch NM2 sampled by the real-time current sampling circuit (1) during half a conduction cycle.

2. The average current sampling circuit for a switching power supply according to claim 1, characterized in that, It also includes a mode detection circuit (4), whose input terminal is connected to the output terminal of the sample and hold circuit (2), for holding the current output of the sample and hold circuit (2) during the working time period of the switching cycle of the power supply, and for outputting zero current during the non-working time period of the switching cycle of the power supply.

3. The average current sampling circuit for a switching power supply according to claim 2, characterized in that, It also includes a current-to-voltage conversion circuit (5), whose input terminal is connected to the output terminal of the mode detection circuit (4), for converting the current output by the mode detection circuit (4) into a voltage output to the controller of the switching power supply.

4. The average current sampling circuit for a switching power supply according to claim 1, characterized in that, The real-time current sampling circuit (1) includes a sampling circuit and a current mirror; The positive and negative input terminals of the sampling circuit are connected to the two ends of the upper switch NM1 / lower switch NM2 of the switching power supply, and are used to sample the voltage across the upper switch NM1 / lower switch NM2 and convert it into the current flowing through the control transistor PM1 of the current mirror. The mirror transistor PM2 of the current mirror outputs the current to the sample and hold circuit (2).

5. The average current sampling circuit for a switching power supply according to claim 1, characterized in that, The sample-and-hold circuit (2) includes a current input circuit, a first switch S1 that is turned on during the first half of the conduction cycle of the upper switch NM1 / lower switch NM2, a first capacitor C1, a second switch S2 that is turned on during the second half of the conduction cycle of the upper switch NM1 / lower switch NM2, a second capacitor C2, and a current output circuit connected in sequence. The current input circuit is used to convert the current output by the real-time current sampling circuit (1) into a first charging voltage to charge the first capacitor C1; the first switch S1 controls whether the first charging voltage charges the first capacitor C1; the second switch S2 controls whether the first capacitor C1 transfers energy to the second capacitor C2; the current output circuit is used to convert the voltage of the second capacitor C2 into a current output.

6. The average current sampling circuit for a switching power supply according to claim 5, characterized in that, The current input circuit includes a first NMOS transistor NM3, whose source is grounded and whose drain is connected to the current output by the real-time current sampling circuit (1). Its drain is also connected to its gate, and its gate is connected to the positive terminal of the first capacitor C1 via the first switch S1. The negative terminal of the first capacitor C1 is grounded. The current output circuit includes a second NMOS transistor NM4, whose source is grounded, whose drain outputs current, whose gate is connected to the positive terminal of the second capacitor C2, whose negative terminal is grounded, and whose positive terminal is also connected to the positive terminal of the first capacitor C1 via the second switch S2.

7. The average current sampling circuit for a switching power supply according to claim 2, characterized in that, The pattern detection circuit (4) includes a third switch S3 and a fourth switch S4. The switching state of the fourth switch S4 is opposite to that of the third switch S3. One end of the third switch S3 is connected to the current output by the sample and hold circuit (2), and one end of the fourth switch S4 is connected to zero current. The other ends of the third switch S3 and the other ends of the fourth switch S4 are connected together as the output terminal of the pattern detection circuit (4).

8. The average current sampling circuit for a switching power supply according to claim 3, characterized in that, The current-to-voltage conversion circuit (5) includes a first resistor R. SAM Second resistor R LPF and the third capacitor C LPF The first resistor R SAM One end is connected to the current output by the mode detection circuit (4), and the current is connected via the second resistor R. LPF Connect the third capacitor C LPF The positive terminal, the first resistor R SAM The other end is grounded, and the third capacitor C LPF The negative terminal is grounded, and the third capacitor C LPF The positive output voltage is supplied to the controller of the switching power supply.

9. A switching power supply, characterized in that, It includes an upper switch NM1 and a lower switch NM2 connected in series between the positive and negative terminals of the input voltage, and an average current sampling circuit as described in any one of claims 1-8.

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