High-voltage-resistant field plate terminal plane gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)

Abstract

The utility model provides a high voltage resistant field plate terminal plane gate silicon carbide VDMOS. A drift layer is connected to a silicon carbide substrate; a lug boss is arranged on the drift layer; the P-type well region is connected to the drift layer and the lug boss; an N-type source region is arranged on the P-type well region; the P-type region is connected to the drift layer, and the P-type region is connected to the P-type well region; the first N-type region is connected to the drift layer, and the first N-type region is connected to the P-type region; the second N-type region is connected to the drift layer, and the second N-type region is connected to the first N-type region; the insulating dielectric layer is connected with the first N-type region, the second N-type region and the P-type region; the gate dielectric layer is connected to the lug boss, the P-type well region and the N-type source region; the field plate metal layer is connected to the insulating dielectric layer; the gate metal layer is connected to the gate dielectric layer; the source electrode metal layer is respectively connected with the P-type well region, the N-type source region, the P-type region and the field plate metal layer; and the drain metal layer is connected to the silicon carbide substrate, so that the terminal voltage endurance capability of the device is improved on the basis of not influencing the conduction characteristic of the device.

Description

TECHNICAL FIELD

[0001] The utility model relates to a kind of high voltage field plate terminal plane gate carbonized silicon VDMOS. BACKGROUND

[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements of device are different in different fields, but the general requirements are higher withstand voltage, lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, short-circuit reliability, etc.), lower body diode conduction loss. And, on the basis that the thickness of device meets the withstand voltage of device, the problem of insufficient withstand voltage often occurs on the terminal of device. SUMMARY

[0003] The technical problem to be solved by the utility model is to provide a kind of high voltage field plate terminal plane gate carbonized silicon VDMOS, by setting field plate metal layer, P type area, first N type area and second N type area, improve the terminal withstand voltage of device on the basis of not affecting the on-state characteristic of device.

[0004] In the first aspect, the utility model provides a kind of high voltage field plate terminal plane gate carbonized silicon VDMOS, comprising:

[0005] Silicon carbide substrate;

[0006] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;The upper side of the drift layer is provided with protruding part;

[0007] P type trap area, the lower side of the P type trap area is connected to the upper side of the drift layer, and the inner side of the P type trap area is connected to the outer side of the protruding part;N type source area is provided on the P type trap area;

[0008] P type area, the lower side of the P type area is connected to the upper side of the drift layer, and the inner side of the P type area is connected to the outer side of the P type trap area;

[0009] First N type area, the lower side of the first N type area is connected to the upper side of the drift layer, and the inner side of the first N type area is connected to the outer side of the P type area;

[0010] Second N type area, the lower side of the second N type area is connected to the upper side of the drift layer, and the inner side of the second N type area is connected to the outer side of the first N type area;

[0011] Insulating dielectric layer, the lower side of the insulating dielectric layer is connected the first N type area, second N type area and P type area;

[0012] A gate dielectric layer, a lower side of which is connected to an upper side of the protruding part, an upper side of the P-type well region and an upper side of the N-type source region;

[0013] A field plate metal layer, a lower side of which is connected to an upper side of the insulating dielectric layer;

[0014] A gate metal layer, a lower side of which is connected to the gate dielectric layer;

[0015] A source metal layer, which is connected to the P-type well region, the N-type source region, the P-type region and the field plate metal layer respectively;

[0016] And a drain metal layer, which is connected to a lower side of the silicon carbide substrate.

[0017] The utility model has the advantages that:

[0018] First, the utility model constructs the structure of the P-type well region, the P-type region, the first N-type region and the second N-type region, the doping concentration of the P-type region and the first N region is low, and the electric field intensity is low, so that when the device bears high voltage at the drain, the electric field concentrated at the corner of the P-type well region is diffused to the left and right sides, the electric field intensity is gradually reduced, a slowly varying electric field is formed, and breakdown caused by electric field concentration is avoided, and the terminal withstand voltage capacity is improved;

[0019] Second, the utility model constructs the field plate metal layer, which is connected with the source metal layer, when the drain bears high voltage, the field plate metal layer is low voltage relative to the drain, positive charges are formed below the field plate metal layer, the electric field at the edge of the P-type well region is expanded outward, the electric field intensity at the edge of the P-type well region is reduced, and the terminal withstand voltage capacity of the device is improved;

[0020] Third, the utility model is provided with the insulating dielectric layer, the withstand voltage capacity of the field plate metal layer is improved, the breakdown channel of the drain metal layer and the source metal layer formed by the drain voltage in the second N-type region and the P-type region is avoided, and the reliability of the device structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0021] The utility model will be further described in connection with the embodiments and with reference to the drawings.

[0022] Figure 1 It is a schematic diagram of the utility model of a high-voltage field plate terminal planar gate silicon carbide VDMOS.

[0023] Figure 2 It is a process cross section of the utility model of a high-voltage field plate terminal planar gate silicon carbide VDMOS. Figure One .

[0024] Figure 3The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Two .

[0025] Figure 4 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Three .

[0026] Figure 5 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Four .

[0027] Figure 6 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Five .

[0028] Figure 7 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Six .

[0029] Figure 8 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Seven .

[0030] Figure 9 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Eight .

[0031] Figure 10 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Nine .

[0032] Figure 11 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Ten .

[0033] Figure 12 The utility model discloses a high voltage field plate terminal plane gate silicon carbide VDMOS's process section view Figure Ten One. Specific implementation

[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The drawings show embodiments of the present application. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0036] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0037] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction, and the spatially relative terms used herein can be interpreted accordingly. The terms "first", "second" and the like, as used herein do not necessarily have any

[0038] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "comprises" as used herein is not intended to exclude other features, integers, steps, operations, elements, components or groups thereof, or combinations thereof. Also, the term "comprising" as used herein is intended to mean "including", "consisting of", "consisting essentially of" or "composed of".

[0039] As Figure 1 shown in the figure, the embodiment of the application provides a high-voltage field plate terminal planar gate silicon carbide VDMOS, which comprises:

[0040] a silicon carbide substrate 101;

[0041] a drift layer 102, a lower side of the drift layer 102 being connected to an upper side of the silicon carbide substrate 101; and a protruding part 1021 being arranged on an upper side of the drift layer 102;

[0042] a P-type well region 103, a lower side of the P-type well region 103 being connected to an upper side of the drift layer 102, and an inner side of the P-type well region 103 being connected to an outer side of the protruding part 1021; and an N-type source region 1031 being arranged on an upper side of the P-type well region 103;

[0043] a P-type region 104, a lower side of the P-type region 104 being connected to an upper side of the drift layer 102, and an inner side of the P-type region 104 being connected to an outer side of the P-type well region 103;

[0044] a first N-type region 105, a lower side of the first N-type region 105 being connected to an upper side of the drift layer 102, and an inner side of the first N-type region 105 being connected to an outer side of the P-type region 104;

[0045] a second N-type region 106, a lower side of the second N-type region 106 being connected to an upper side of the drift layer 102, and an inner side of the second N-type region 106 being connected to an outer side of the first N-type region 105;

[0046] an insulating medium layer 107, a lower side of the insulating medium layer 107 being connected to the first N-type region 105, the second N-type region 106, and the P-type region 104;

[0047] a gate medium layer 108, a lower side of the gate medium layer 108 being connected to an upper side of the protruding part 1021, an upper side of the P-type well region 103, and an upper side of the N-type source region 1031;

[0048] a field plate metal layer 109, a lower side of the field plate metal layer 109 being connected to an upper side of the insulating medium layer 107;

[0049] a gate metal layer 110, a lower side of the gate metal layer 110 being connected to the gate medium layer 108;

[0050] a source metal layer 111, the source metal layer 111 being connected to the P-type well region 103, the N-type source region 1031, the P-type region 104, and the field plate metal layer 109, respectively;

[0051] and a drain metal layer 112, the drain metal layer 112 being connected to a lower side of the silicon carbide substrate 101.

[0052] In this embodiment, preferably, the widths of the first N-type region 105, the P-type region 104, and the second N-type region 106 are all equal.

[0053] In this embodiment, preferably, the thickness of the field plate metal layer 109 is less than the thickness of the source metal layer 111.

[0054] In this embodiment, preferably, the doping concentration of the first N-type region 105 is less than the doping concentration of the drift layer 102.

[0055] In this embodiment, preferably, the doping concentration of the drift layer 102 is less than the doping concentration of the second N-type region 106.

[0056] like Figures 1 to 12 As shown, the above-mentioned method for fabricating silicon carbide VDMOS includes the following steps:

[0057] Step 1: Deposit metal on the lower side of silicon carbide substrate 101 to form drain metal layer 112; epitaxially grow on the upper side of silicon carbide substrate 101 to form drift layer 102;

[0058] Step 2: Form a barrier layer 113 above the drift layer 102, etch the barrier layer 113 to form a via, and perform ion implantation into the drift layer 102 to form a P-type region 104.

[0059] Step 3: Remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, and perform ion implantation into the drift layer 102 to form the first N-type region 105.

[0060] Step 4: Remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, and perform ion implantation into the drift layer 102 to form the second N-type region 106.

[0061] Step 5: Remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, and implant ions into the drift layer 102 to form a P-type well region 103.

[0062] Step 6: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a via, and implant ions into the P-type well region 103 to form the N-type source region 1031.

[0063] Step 7: Remove the original barrier layer 113, reform the barrier layer 113, etch the barrier layer 113 to form a via, and deposit to form the gate dielectric layer 108.

[0064] Step 8, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, deposit metal to form the gate metal layer 110;

[0065] Step 9, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, deposit metal to form the source metal layer 111;

[0066] Step 10, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, deposit to form the insulating medium layer 107;

[0067] Step 11, remove the original barrier layer 113, re-form the barrier layer 113, etch the barrier layer 113 to form a via, deposit metal to form the field plate metal layer 109; remove the barrier layer 113, complete the preparation.

[0068] In another embodiment of the present application, the doping concentration of the N-type silicon carbide substrate 101 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 102 is 6-10e16cm -3 , the doping concentration of the P-type well region 103 is 6-10e17cm -3 , the doping concentration of the P-type region 104 is 6-10e16cm -3 , the doping concentration of the first N-type region 105 is 1-5e16cm -3 , the doping concentration of the second N-type region 106 is 1-5e17cm -3 , the material of the insulating medium layer 107 and the gate medium layer 108 can be silicon dioxide, and the doping concentration of the N-type source region 1031 is 2-8e18cm -3The doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of low resistance ohmic contact with the drain metal layer 112, and to reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 102 is a compromise between the reverse voltage withstand and the on-resistance of the device; the P-type region 104, the first N-type region 105, and the second N-type region 106 are to form a P-type well region 103-P-type region 104-first N-type region 105-second N-type region 106 structure in the terminal, to realize the transition from the P-type well region 103 to the low-doped region, so that when the device drain withstands high voltage, the electric field does not concentrate on the edge of the P-type well 103, and the electric field is gradually reduced to improve the reliability of the terminal; the insulating medium layer 107 and the field plate metal layer 109 are to form a P-type region 104 under the insulating medium layer 107 when the device drain is connected to high voltage, and the field plate metal layer 109 is at a low level relative to the drain, to expand the positive charge region to the edge based on the P-type well region 103-P-type region 104 structure existing in the device structure itself; the field plate metal layer 109 is connected to the source metal layer 111, and when the body diode of the device is in continuous current, the field plate metal layer 109-insulating medium layer 107 structure of the device does not affect the body diode characteristics, thereby ensuring the body diode continuous current capability of the device; the doping concentration of the N-type source region 1031 is to reduce the source contact resistance of the device and reduce the on-resistance of the device;

[0069] The thickness of the N-type silicon carbide substrate 101 of the device is 1 μm, which is to form a low resistance ohmic contact with the drain metal layer 112 and reduce the on-resistance of the device; the thickness of the N-type drift layer 102 is 50-100 μm, which is adjusted within the above range according to different requirements for the voltage withstand characteristics of the device; the width of the P-type well region 103 of the device is 30% of the width of the drift layer 102, and the widths of the P-type region 104, the first N-type region 105, and the second N-type region 106 are all equal to 5% of the width of the drift layer 102, which is to ensure the low resistance characteristics of the device and the compromise of the voltage withstand terminal of the device, to realize the combination of high voltage withstand and low resistance characteristics of the device; the thickness of the P-type well region 103 is 300 nm, the thickness of the N-type source region 1031 is 200 nm, the thicknesses of the P-type region 104, the first N-type region 105, and the second N-type region 106 are all 500 nm, and the thickness of the insulating medium layer 107 is 200 nm, which is to ensure that there is no breakdown problem from the drain to the field plate metal when the drain withstands high voltage;

[0070] The utility model discloses a device structure of P type well area 103-P type area 104-first N type area 105-second N type area 106, and the electric field intensity of P type area 104 and first N type area 105 structure is low due to the low doping concentration, thereby the electric field concentrated at the corner of P type well 103 diffuses to left and right sides when the device bears high voltage at the drain, and the electric field intensity gradually reduces, and the slowly varying electric field is formed, thereby the breakdown caused by the electric field concentration is avoided, and the terminal withstand voltage is improved, the field plate metal layer 109 is constructed, the field plate metal layer 109 is connected with source metal layer 111, and when the drain bears high voltage, the field plate metal layer 109 is low voltage relative to the drain, and the positive charge will be formed below the field plate metal layer 109, thereby the electric field of the edge of P type well area 103 is expanded outward, and the electric field intensity of the edge of P type well area 103 is reduced, and the terminal withstand voltage of the device is improved, the thickness of the insulating medium layer 107 of the device is 200nm, and this is to improve the withstand voltage of the field plate metal layer 109, avoid the breakdown channel of the drain metal layer 112 and source metal layer 111 formed by the drain voltage in second N type area 105 and P type area 104, and improve the reliability of the device structure.

[0071] Although the specific embodiments of the utility model are described above, the skilled in the art should understand that the specific examples that we described are only illustrative, and are not used to limit the scope of the utility model, and the equivalent modification and change made by the skilled in the art according to the spirit of the utility model should be covered in the scope of protection of the claims of the utility model.

Claims

1. A high-voltage field-plate terminated planar gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate; A drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; the drift layer is provided with protrusions; A P-type well region is provided, wherein the lower side of the P-type well region is connected to the upper side of the drift layer, and the inner side of the P-type well region is connected to the outer side of the protrusion; an N-type source region is provided on the P-type well region. The lower side of the P-type region is connected to the upper side of the drift layer, and the inner side of the P-type region is connected to the outer side of the P-type well region. A first N-type region, the lower side of the first N-type region is connected to the upper side of the drift layer, and the inner side of the first N-type region is connected to the outer side of the P-type region; The second N-type region has its lower side connected to the upper side of the drift layer, and its inner side connected to the outer side of the first N-type region. An insulating dielectric layer, the lower side of which is connected to the first N-type region, the second N-type region and the P-type region; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the protrusion, the upper side of the P-type well region, and the upper side of the N-type source region; A field plate metal layer, wherein the lower side of the field plate metal layer is connected to the upper side of the insulating dielectric layer; A gate metal layer, the lower side of which is connected to the gate dielectric layer; A source metal layer, wherein the source metal layer is connected to the P-type well region, the N-type source region, the P-type region and the field plate metal layer respectively; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.

2. The high-voltage field-plate terminated planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The widths of the first N-type region, the P-type region, and the second N-type region are all equal.

3. The high-voltage field-plate terminated planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the field plate metal layer is less than the thickness of the source metal layer.

4. The high-voltage field-plate terminated planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the first N-type region is less than the doping concentration of the drift layer.

5. The high-voltage field-plate terminal planar gate silicon carbide VDMOS as described in claim 1, characterized in that: The doping concentration of the drift layer is less than the doping concentration of the second N-type region.

Images