Fast switch shielding trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor)
By introducing a fast-switching shielded trench gate structure into silicon carbide VDMOS devices and utilizing the charge effect of the polysilicon layer to form an NPN-type shielded gate, the on-resistance and switching speed problems of the devices in the 650-900V range are solved, achieving low capacitance and high speed characteristics of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2026-03-20
AI Technical Summary
Existing silicon carbide VDMOS devices have difficulty simultaneously reducing on-resistance and increasing switching speed in the 650-900V range.
The device employs a fast-switching shielded trench gate structure, comprising a gate metal layer, a first N-type polysilicon layer, a P-type polysilicon layer, and a second N-type polysilicon layer. Through the charge effect, the polysilicon region is gradually turned on to form an NPN shielded gate, suppressing the gate leakage capacitance and constructing the device's low-resistance body diode freewheeling capability.
It effectively reduces the gate-drain capacitance of the device, improves the switching speed and reverse withstand voltage capability of the device, and achieves a balance between low on-resistance and high switching speed.
Smart Images
Figure CN224022146U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model relates to a kind of quick switch shielding trench gate silicon carbide VDMOS. BACKGROUND
[0002] Silicon carbide VDMOS is the typical representative of silicon carbide power device, and has wide application in electric vehicle, aerospace, power conversion and other fields. For silicon carbide power VDMOS, the performance requirements of device are different in different fields, and for the range of 650-900V, it is urgent to provide a silicon carbide VDMOS device to reduce on-resistance and improve switching speed. SUMMARY
[0003] The technical problem to be solved by the utility model is to provide a kind of quick switch shielding trench gate silicon carbide VDMOS, which reduces the gate leakage capacitance of device and improves the switching speed of device.
[0004] In the first aspect, the utility model provides a kind of quick switch shielding trench gate silicon carbide VDMOS, comprising:
[0005] Silicon carbide substrate;
[0006] Drift layer, the lower side of the drift layer is connected to the upper side of the silicon carbide substrate;The recess and the raised portion are provided on the drift layer;
[0007] Low resistance zone, the lower side of the low resistance zone is connected to the upper side of the raised portion;
[0008] P-type well region, the lower side of the P-type well region is connected to the drift layer, and the outer side of the P-type well region is connected to the inner side of the raised portion and the inner side of the low resistance zone;N-type source region and P-type source region are provided on the P-type well region;The outer side of the P-type source region is connected to the P-type well region, and the inner side of the P-type well region is connected to the outer side of the N-type source region;
[0009] Insulating medium layer, the lower part of the insulating medium layer is located in the recess, and the outer side of the insulating medium layer is connected to the inner side of the P-type well region and the inner side of the N-type source region respectively;The insulating medium layer is provided with polysilicon region and groove, and the groove is located directly above the polysilicon region;
[0010] Gate metal layer, the gate metal layer is located in the groove;
[0011] Source metal layer, the source metal layer is connected to the low resistance zone, P-type well region, P-type source region and N-type source region respectively;
[0012] And, drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate.
[0013] The utility model discloses a quick switching shield trench gate silicon carbide VDMOS has the advantages of:
[0014] I, the utility model discloses a grid structure includes gate metal layer, first N type polycrystalline silicon layer, P type polycrystalline silicon layer and second N type polycrystalline silicon layer, when gate metal layer adds positive voltage, generates positive charge through charge effect in the first N type polycrystalline silicon layer close to gate metal layer, and the positive charge is gradually conducted from top to bottom in polycrystalline silicon area, and effectively inhibits the grid drain capacitance of device;
[0015] II, the utility model forms the positive pn junction of upper portion and the reverse pn junction of bottom portion in the first N type polycrystalline silicon layer, P type polycrystalline silicon layer and second N type polycrystalline silicon layer when grid adds positive charge, compared with traditional separate polycrystalline silicon, this structure constructs device NPN type shield grid on the basis of not influencing to device P type well area reverse type, improves the shielding effect of device grid drain capacitance;
[0016] III, the utility model low resistance area can guarantee device parasitic body schottky diode characteristic, realizes device low resistance body diode freewheeling, and P type source area can improve N type source area area reverse withstand voltage and guarantees body diode freewheeling capability. BRIEF DESCRIPTION OF DRAWINGS
[0017] The utility model will be further described in connection with the embodiments with reference to the drawings.
[0018] Figure 1 It is the schematic diagram of the utility model quick switching shield trench gate silicon carbide VDMOS.
[0019] Figure 2 It is the process section view of the utility model quick switching shield trench gate silicon carbide VDMOS Figure 1 .
[0020] Figure 3 It is the process section view of the utility model quick switching shield trench gate silicon carbide VDMOS Figure 2 .
[0021] Figure 4 It is the process section view of the utility model quick switching shield trench gate silicon carbide VDMOS Figure 3 .
[0022] Figure 5 It is the process section view of the utility model quick switching shield trench gate silicon carbide VDMOS Figure 4 .
[0023] Figure 6 It is the process section view of the utility model quick switching shield trench gate silicon carbide VDMOS Figure 5 .
[0024] Figure 7The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 6 .
[0025] Figure 8 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 7 .
[0026] Figure 9 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 8 .
[0027] Figure 10 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 9 .
[0028] Figure 11 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 .
[0029] Figure 12 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 One.
[0030] Figure 13 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 Two.
[0031] Figure 14 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 Three.
[0032] Figure 15 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 Four.
[0033] Figure 16 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 Five.
[0034] Figure 17 The utility model discloses a quick switch shielding trench gate silicon carbide VDMOS's process section view Figure 10 Six. Specific embodiment
[0035] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0037] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "in contact with," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of this utility model, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion.
[0038] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as “below,” “under,” or “below” other elements or features would be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein are interpreted accordingly.
[0039] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0040] like Figure 1 As shown, this application embodiment provides a fast-switching shielded trench-gate silicon carbide VDMOS, comprising:
[0041] Silicon carbide substrate 1;
[0042] A drift layer 2, the lower side of which is connected to the upper side of the silicon carbide substrate 1; the drift layer 2 is provided with a groove 21 and a protrusion 22;
[0043] Low-resistance region 3, the lower side of which is connected to the upper side of the protrusion 22;
[0044] P-type well region 4, the lower side of which is connected to the drift layer 2, the outer side of which is connected to the inner side of the protrusion 22 and the inner side of the low-resistivity region 3; N-type source region 41 and P-type source region 42 are provided on the P-type well region 4; the outer side of the P-type source region 42 is connected to the P-type well region 4, and the inner side of the P-type well region 4 is connected to the outer side of the N-type source region 41;
[0045] An insulating dielectric layer 5 is provided at its lower part within the groove 21. The outer side of the insulating dielectric layer 5 is connected to the inner side of the P-type well region 4 and the inner side of the N-type source region 41, respectively. A polysilicon region 51 and a trench 52 are provided within the insulating dielectric layer 5, with the trench 52 located directly above the polysilicon region.
[0046] A gate metal layer 6 is disposed within the trench 52;
[0047] Source metal layer 7, which is connected to the low-resistivity region 3, P-type well region 4, P-type source region 42 and N-type source region 41 respectively;
[0048] And a drain metal layer 8, which is connected to the lower side of the silicon carbide substrate 1.
[0049] In this embodiment, preferably, the polysilicon region 51 comprises a first N-type polysilicon layer 511, a P-type polysilicon layer 512, and a second N-type polysilicon layer 513, the lower side of the first N-type polysilicon layer 511 is connected to the upper side of the P-type polysilicon layer 512, and the lower side of the P-type polysilicon layer 512 is connected to the upper side of the second N-type polysilicon layer 513.
[0050] In this embodiment, preferably, the doping concentration of the first N-type polysilicon layer 511 is greater than the doping concentration of the P-type polysilicon layer 512, and the doping concentration of the P-type polysilicon layer 512 is greater than the doping concentration of the second N-type polysilicon layer 513.
[0051] In this embodiment, preferably, the doping concentration of the polysilicon region 51 is greater than or equal to 1e20 cm -3 .
[0052] In this embodiment, preferably, the silicon carbide substrate 1, the drift layer 2, and the low resistance region 3 are all N-type.
[0053] In this embodiment, preferably, the thickness L1 of the side insulating medium layer 5 of the polysilicon region 51 is greater than the thickness L2 of the side insulating medium layer 5 of the gate metal layer 6.
[0054] In this embodiment, preferably, the distance between the gate metal layer 6 and the upper side of the polysilicon region 51 is less than the distance between the lower side of the polysilicon region 51 and the bottom surface of the groove 21.
[0055] As shown in Figures 1 to 17 the preparation method of the above-mentioned silicon carbide VDMOS, comprising the following steps:
[0056] Step 1, depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 8, and epitaxially growing on the upper side of the silicon carbide substrate 1 to form a drift layer 2;
[0057] Step 2, forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and ion implantation to form a P-type well region 4;
[0058] Step 3, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form an N-type source region 41;
[0059] Step 4, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a P-type source region 42;
[0060] Step 5, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and ion implantation to form a low resistance region 3;
[0061] Step 6, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, etch the drift layer 2 to form a groove 21, deposit, and form an insulating medium layer 5;
[0062] Step 7, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, etch the insulating medium layer 5, deposit polysilicon to form a polysilicon region 51, and then deposit an insulating medium;
[0063] Step 8, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, etch the insulating medium layer 5 to form a trench 52, and deposit metal to form a gate metal layer 6;
[0064] Step 9, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a via, and etch the low resistance region 3, the P-type well region 4, the P-type source region 42, and the N-type source region 41, deposit metal to form a source metal layer 7, remove the barrier layer 9, and complete the preparation.
[0065] In another embodiment of the utility model, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 5-9e17cm -3 , the doping concentration of the N-type low resistance region 3 is 6-9e17cm -3 , the doping concentration of the P-type well region 4 is 1-5e16cm -3 , the doping concentration of the P-type source region 42 is 1-5e19cm -3 , the doping concentration of the N-type source region 41 is 2-8e18cm -3 , and the material of the insulating medium layer 5 can be silicon dioxide; the doping concentration of the N-type silicon carbide substrate 1 is to ensure the formation of low resistance ohmic contact with the drain metal layer 8 and reduce the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse voltage resistance and the on-resistance of the device; the doping concentration of the P-type well region 4 is to realize the voltage resistance of the pn junction structure of the device when the device drain withstands high voltage, and reducing the doping concentration can reduce the gate switching charge and increasing the concentration can improve the reverse voltage resistance of the device; the doping concentration is a compromise between the switching charge and the voltage resistance; the doping concentration of the P-type source region 42 is to form ohmic contact with the source metal layer 7, thereby constructing the low resistance parasitic pn junction body diode of the device source metal layer 7-P-type source region 42 (ohmic contact)-P-type well region 4-N-type drift layer 2 (pn junction); the doping concentration of the N-type low resistance region 3 is to form a Schottky contact with the intermediate source metal layer 7 of the device, reduce the on-voltage drop of the body diode of the device, and ensure the reverse voltage resistance; the first N-type polysilicon layer 511-P-type polysilicon layer 512-second N-type polysilicon layer 513 structure improves the shielding effect of the shielding gate on the gate leakage capacitor through N-P-N type charge, and reduces the switching charge of the device;
[0066] The thickness of the N-type silicon carbide substrate 1 of the device is 300 nm, which is to form a low-resistance ohmic contact with the drain metal layer 8 to reduce the on-resistance of the device; the thickness of the N-type drift layer 2 is 30-60 μm, which is adjusted within the above range according to different requirements for the voltage withstand characteristics of the device, and the voltage withstand range of the device is 650-900 V; the total depth of the gate structure of the device is 1.8 μm, the thickness of the gate metal layer 6 is 0.9 μm, the thicknesses of the first N-type polysilicon layer 511, the P-type polysilicon layer 512 and the second N-type polysilicon layer 513 are all 200 nm, the thickness of the insulating medium between the first N-type polysilicon layer 511 and the gate metal layer 6 is 100 nm, the distance from the bottom of the second N-type polysilicon layer 513 to the bottom of the insulating medium layer 5 is 200 nm, and the width of the insulating medium on both sides of the gate metal layer 6 is 50 nm, which is to ensure the trade-off between the gate control capability and the reliability of the gate of the device; the width of the insulating medium on both sides of the polysilicon region 51 is 100 nm, which is to ensure the reliability of the insulating medium layer 5 under the condition of deep trench, the thickness of the source metal layer 7 is 200 nm, the thicknesses of the P-type source region 42 and the N-type source region 41 are both 200 nm, the thickness of the N-type low-resistance region 3 is 200 nm, the thickness of the P-type well region 4 is 600 nm, the width of the N-type low-resistance region 3 is 100-500 nm, the width of the P-type well region 4 is 1 μm-3 μm, the widths of the P-type source region 42 and the N-type source region 41 are both 300-1000 nm, and the width of the insulating medium layer 5 is 1 μm-1.5 μm, which is to ensure the width of the deepest etching;
[0067] The gate structure of the device includes the gate metal layer 6, the first N-type polysilicon layer 511, the P-type polysilicon layer 512 and the second N-type polysilicon layer 513. When the gate metal layer 6 is applied with a positive voltage, a positive charge is generated in the first N-type polysilicon layer 511 close to the gate metal layer 6 through the charge effect, and the positive charge is gradually turned on from top to bottom in the polysilicon region 51. The first N-type polysilicon layer close to the gate metal layer 6 is heavily doped, and the doping concentration is 1-5e21cm-3. The P-type polysilicon layer is doped with a doping concentration of 5-8e20cm-3. The second N-type polysilicon layer is doped with a doping concentration of 1-5e20cm-3. The doping concentration of the polysilicon region 51 gradually decreases from top to bottom, which can effectively suppress the gate-drain capacitance of the device. -3 -3 -3
[0068] When the gate is applied with a positive charge, a positive pn junction at the top and a reverse pn junction at the bottom are formed in the first N-type polysilicon layer 511, the P-type polysilicon layer 512 and the second N-type polysilicon layer 513. Compared with the traditional single polysilicon, this structure builds a device NPN-type shield gate without affecting the reverse type of the P-type well region 4 of the device, and improves the shielding effect of the gate-drain capacitance of the device.
[0069] The N-type low resistance region 3 can ensure the parasitic body Schottky diode characteristics of the device, and realize the low resistance body diode freewheeling of the device.
[0070] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application, and equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.
Claims
1. A fast-switching shielded trench-gate silicon carbide VDMOS, characterized in that: include: silicon carbide substrate; A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate; The drift layer is provided with grooves and protrusions; A low-resistance region, the lower side of which is connected to the upper side of the protrusion; A P-type well region is provided, the lower side of which is connected to the drift layer, and the outer side of which is connected to the inner side of the protrusion and the inner side of the low-resistivity region; an N-type source region and a P-type source region are provided on the P-type well region; the outer side of the P-type source region is connected to the P-type well region, and the inner side of the P-type well region is connected to the outer side of the N-type source region. An insulating dielectric layer is provided at its lower part within the groove, and the outer side of the insulating dielectric layer is respectively connected to the inner side of the P-type well region and the inner side of the N-type source region; a polysilicon region and a trench are provided within the insulating dielectric layer, and the trench is located directly above the polysilicon region; A gate metal layer is disposed within the trench; A source metal layer, wherein the source metal layer is respectively connected to the low-resistivity region, the P-type well region, the P-type source region and the N-type source region; And a drain metal layer, which is connected to the lower side of the silicon carbide substrate.
2. The fast-switching shielded trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The polycrystalline silicon region includes a first N-type polycrystalline silicon layer, a P-type polycrystalline silicon layer, and a second N-type polycrystalline silicon layer. The lower side of the first N-type polycrystalline silicon layer is connected to the upper side of the P-type polycrystalline silicon layer, and the lower side of the P-type polycrystalline silicon layer is connected to the upper side of the second N-type polycrystalline silicon layer.
3. The fast-switching shielded trench gate silicon carbide VDMOS as described in claim 2, characterized in that: The doping concentration of the first N-type polysilicon layer is greater than that of the P-type polysilicon layer, and the doping concentration of the P-type polysilicon layer is greater than that of the second N-type polysilicon layer.
4. The fast-switching shielded trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The silicon carbide substrate, drift layer, and low-resistivity region are all N-type.
5. The fast-switching shielded trench-gate silicon carbide VDMOS as described in claim 1, characterized in that: The thickness of the insulating dielectric layer on the side of the polysilicon region is greater than the thickness of the insulating dielectric layer on the side of the gate metal layer.
6. The fast-switching shielded trench gate silicon carbide VDMOS as described in claim 1, characterized in that: The distance between the gate metal layer and the upper side of the polysilicon region is less than the distance between the lower side of the polysilicon region and the bottom of the groove.