Voltage conversion system

Abstract

The utility model provides a voltage conversion system. The voltage conversion system includes a multi-phase voltage converter and a controller. The multi-phase voltage converter is coupled to a load and comprises a plurality of phase circuits, the plurality of phase circuits are coupled to the load, and at least one of the plurality of phase circuits is in an active state, so that the multi-phase voltage converter provides load current to the load. The controller is coupled to the multi-phase voltage converter, and is used for enabling at least one of the plurality of phase circuits to be in an active state according to the load current and the working item sequence of the plurality of phase circuits, and is used for responding to the fact that the enabling number of the plurality of phase circuits becomes 1. The work item order is adjusted to adjust the first one of the plurality of phase circuits from the second syn-order work item to the highest priority work item. The working item sequence of the plurality of phase circuits is redefined through the controller in response to the fact that the enabling number of the plurality of phase circuits becomes 1, and the voltage conversion system can achieve the technical effects of effectively improving the efficiency and the reliability of the voltage conversion system.

Description

TECHNICAL FIELD

[0001] The utility model relates to a voltage conversion system, in particular to a voltage conversion system capable of auto phase shedding. BACKGROUND

[0002] With the progress of technology, various integrated circuits have been developed. For example, a voltage converter can provide current to power a load. Some related technologies use a multiphase voltage converter. A multiphase voltage converter includes multiple sets of power switches to adaptively power a load. However, how to improve the efficiency and reliability of the multiphase voltage converter is one of the important issues in the field. SUMMARY

[0003] One aspect of the utility model is a voltage conversion system. The voltage conversion system includes a multiphase voltage converter and a controller. The multiphase voltage converter is coupled to a load and includes multiple phase circuits, wherein the multiple phase circuits are coupled to the load, and at least one of the multiple phase circuits is in an active state to cause the multiphase voltage converter to provide a load current to the load. The controller is coupled to the multiphase voltage converter to enable at least one of the multiple phase circuits to be in the active state according to the load current and a working item sequence of the multiple phase circuits, and to adjust the working item sequence to adjust a first one of the multiple phase circuits from a second order working item to a highest priority working item in response to the number of enabled ones of the multiple phase circuits becoming one.

[0004] In some embodiments, when the first one of the multiple phase circuits is adjusted from the second order working item to the highest priority working item, a second one of the multiple phase circuits is adjusted from the highest priority working item to a last priority working item.

[0005] In some embodiments, when the number of the multiple phase circuits becomes one, the second one of the multiple phase circuits is in the active state, and the remaining ones of the multiple phase circuits have a high impedance state.

[0006] In some embodiments, when the number of the multiple phase circuits changes from one to two, the first one and the second one of the multiple phase circuits are in the active state, and the remaining ones of the multiple phase circuits have a high impedance state.

[0007] In some embodiments, when the first one of the plurality of phase circuits is the highest priority active item, the controller is configured to switch at least the first one of the plurality of phase circuits from a high impedance state to the active state in accordance with the active item order starting from the first one of the plurality of phase circuits in response to the enabled number of the plurality of phase circuits changing from one to a number greater than one.

[0008] In some embodiments, when the first one of the plurality of phase circuits is the highest priority active item, the controller is configured to adjust the active item order to adjust a third one of the plurality of phase circuits from the second order active item to the highest priority active item in response to the enabled number of the plurality of phase circuits changing to one.

[0009] In some embodiments, when the third one of the plurality of phase circuits is adjusted from the second order active item to the highest priority active item, the first one of the plurality of phase circuits is adjusted from the highest priority active item to the last priority active item.

[0010] In some embodiments, when the third one of the plurality of phase circuits is the highest priority active item, the controller is configured to switch at least the third one of the plurality of phase circuits from a high impedance state to the active state in accordance with the active item order starting from the third one of the plurality of phase circuits in response to the enabled number of the plurality of phase circuits changing from one to a number greater than one.

[0011] In some embodiments, the multiphase voltage converter further comprises a plurality of drive circuits coupled to the plurality of phase circuits and the controller and configured to drive the plurality of phase circuits in accordance with a plurality of drive signals outputted by the controller.

[0012] In some embodiments, the controller comprises a feedback signal circuit, a phase management circuit, and a pulse width modulation circuit. The feedback signal circuit is configured to output a control signal in accordance with the load current, wherein the control signal is configured to indicate the enabled number of the plurality of phase circuits. The phase management circuit is coupled to the feedback signal circuit and configured to output a plurality of enable signals in accordance with the control signal and to adjust the active item order of the plurality of phase circuits in response to the enabled number of the plurality of phase circuits changing to one. The pulse width modulation circuit is coupled to the phase management circuit and the multiphase voltage converter and configured to output the plurality of drive signals to the multiphase voltage converter in accordance with the plurality of enable signals.

[0013] In summary, the voltage conversion system of the present application can average the duty cycle of the plurality of phase circuits in the multiphase voltage converter by redefining the sequence of the work items of the plurality of phase circuits in response to the number of enabled phase circuits becoming one, so as to effectively improve the efficiency and reliability of the voltage conversion system. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 A circuit block diagram of a voltage conversion system according to some embodiments of the present application.

[0015] Figure 2 A schematic diagram of a plurality of voltage levels of a drive signal according to some embodiments of the present application.

[0016] Figure 3 A circuit block diagram of a controller according to some embodiments of the present application.

[0017] Figure 4 A flowchart of a control method according to some embodiments of the present application.

[0018] Figure 5 Signal timing diagrams of a plurality of enable signals in a scenario of a load according to some embodiments of the present application.

[0019] Figure 6 Signal timing diagrams of a plurality of enable signals in a scenario of a load according to some embodiments of the present application.

[0020] Figure 7 Signal timing diagrams of a plurality of enable signals in a scenario of a load according to some embodiments of the present application.

[0021] Figure 8 Signal timing diagrams of a plurality of enable signals in a scenario of a load according to some embodiments of the present application.

[0022] Figure 9 Signal timing diagrams of a plurality of enable signals in a scenario of a load according to some embodiments of the present application.

[0023] Figure 10 Signal timing diagrams of a plurality of enable signals in a scenario of a load according to some embodiments of the present application. DETAILED DESCRIPTION

[0024] The following embodiments are described in detail with reference to the accompanying drawings. The specific embodiments described are merely illustrative and are not intended to limit the present application, and the description of the structure and operation is not intended to limit the order of execution. Any structure obtained by recombining elements, resulting in a device with equivalent functionality, is within the scope of the present application.

[0025] As used throughout this document and in the claims, the words "terms" are generally given their ordinary meaning in the field, in the context of the disclosure, and in the special context in which they are used.

[0026] As used herein, "coupled" or "connected" can refer to two or more elements being in direct physical or electrical contact with each other, or can refer to two or more elements being in indirect contact with each other where a

[0027] Please refer to Figure 1 , Figure 1 A circuit block diagram of a voltage conversion system 100 according to some embodiments of the present application is shown. As shown in Figure 1 , the voltage conversion system 100 includes a multiphase voltage converter 110, a controller 120, and a detection circuit 130. The multiphase voltage converter 110 is coupled between an input voltage VIN, the controller 120, and a load LD, and the detection circuit 130 is coupled between the multiphase voltage converter 110 and the controller 120. Specifically, the multiphase voltage converter 110 can be implemented by a voltage converter such as a multiphase buck converter.

[0028] In some embodiments, the multiphase voltage converter 110 includes a plurality of drive circuits D1-D8 and a plurality of phase circuits 111-118. The plurality of drive circuits D1-D8 is coupled to the controller 120 and is respectively coupled to the plurality of phase circuits 111-118. The plurality of phase circuits 111-118 is further coupled to the load LD.

[0029] Specifically, each phase circuit 111-118 includes an upper bridge switch HS, a lower bridge switch LS, an inductor L, and a capacitor CO. The circuit architecture of each phase circuit 111-118 is described by taking the phase circuit 111 as an example. The first end of the upper bridge switch HS is coupled to the input voltage VIN. The second end of the upper bridge switch HS is coupled to the first end of the lower bridge switch LS and the first end of the inductor L. The second end of the lower bridge switch LS is coupled to a ground terminal. The control terminal of the upper bridge switch HS and the control terminal of the lower bridge switch LS are coupled to the drive circuit D1. The second end of the inductor L is coupled to the first end of the capacitor CO and the load LD. The second end of the capacitor CO is coupled to the ground terminal. Since the remaining phase circuits 112-118 have similar circuit architectures to the phase circuit 111, the description of the remaining phase circuits 112-118 is omitted here.

[0030] In some embodiments, multiple drive circuits D1 to D8 are used to drive multiple phase circuits 111 to 118 according to multiple drive signals PWM1 to PWM8 output by the controller 120. Taking drive circuit D1 as an example... Figure 2 Explain the operation of each drive circuit D1 to D8. Figure 2 This is a schematic diagram illustrating multiple voltage levels of the drive signal PWMX according to some embodiments of the present invention. Figure 2 Multiple voltage levels of the drive signal PWMX are suitable for Figure 1 Any one of the multiple drive signals PWM1 to PWM8, where X is an integer from 1 to 8.

[0031] As described above, the drive circuit D1 is used to control the phase circuit 111 to be in an active state according to the drive signal PWM1, so as to turn on or off the upper bridge switch HS and the lower bridge switch LS in the phase circuit 111. For example, when the drive signal PWM1 has the following characteristics... Figure 2 When the enable level VH is shown (e.g., the voltage level corresponding to logic 1), the drive circuit D1 turns on the upper bridge switch HS in phase circuit 111 and turns off the lower bridge switch LS in phase circuit 111 to control phase circuit 111 to have a charging state in the active state. When the drive signal PWM1 has the following characteristics... Figure 2 When the disabled level VL (e.g., the voltage level corresponding to logic 0) is shown, the drive circuit D1 turns off the upper bridge switch HS in phase circuit 111 and turns on the lower bridge switch LS in phase circuit 111 to control phase circuit 111 to have a discharge state in the active state. When the drive signal PWM1 has the following characteristics... Figure 2 When the high impedance level VHIZ is shown (e.g., the voltage level corresponding to non-logic 1 and non-logic 0), the drive circuit D1 turns off the upper bridge switch HS and the lower bridge switch LS in the phase circuit 111 to control the phase circuit 111 to be in a high impedance state (or a closed state). Since the remaining drive circuits D2 to D8 have similar circuit operation to drive circuit D1, the description of the remaining drive circuits D2 to D8 is omitted here.

[0032] By having the drive signal PWM1 alternately have an enable level VH and a disable level VL (for example, the drive signal PWMX in such a way as...), Figure 2 The change in P1 during the period shown) allows the drive circuit D1 to drive the phase circuit 111 to output current (not shown in the figure). Furthermore, by maintaining the drive signal PWM1 at a high impedance level VHIZ (for example, the drive signal PWMX at such a high impedance level VHIZ), the drive circuit D1 can drive the phase circuit 111 to output current (not shown in the figure). Figure 2As shown, the driving circuit D1 can drive the phase circuit 111 to not output the aforementioned current. In short, by driving the plurality of phase circuits 111-118 respectively via the plurality of driving circuits D1-D8 in cooperation (e.g., driving at least one of the plurality of phase circuits 111-118 to be active), as shown in the following table, the multi-phase voltage converter 110 can provide the load current IOTT to the load LD. Figure 1 As shown, the multi-phase voltage converter 110 can provide the load current IOTT to the load LD.

[0033] In some embodiments, the detecting circuit 130 is configured to detect the load current IOTT and configured to transmit the load current IOTT to the controller 120. Further, the controller 120 receives the load current IOTT to determine the number of enabled phase circuits NPH (shown in the following table) of the plurality of phase circuits 111-118, i.e., the number of phase circuits of the plurality of phase circuits 111-118 that are enabled and active. After determining the number of enabled phase circuits NPH of the plurality of phase circuits 111-118, the controller 120 further outputs the plurality of driving signals PWM1-PWM8 to the plurality of driving circuits D1-D8 respectively according to the order of the plurality of phase circuits 111-118 to control the plurality of driving circuits D1-D8 to drive the plurality of phase circuits 111-118 respectively via the plurality of driving signals PWM1-PWM8. Therefore, in some embodiments, the controller 120 is configured to control the plurality of phase circuits 111-118 of the multi-phase voltage converter 110 according to the load current IOTT and the order of the plurality of phase circuits 111-118. Figures 5-10

[0034] As mentioned above, in some embodiments, the controller 120 is further configured to redefine or adjust the order of the plurality of phase circuits 111-118 in response to a triggering event. For example, the triggering event can be that the number of enabled phase circuits NPH of the plurality of phase circuits 111-118 becomes 1. When the triggering event occurs, the controller 120 can redefine the highest priority phase circuit in the order of the plurality of phase circuits 111-118. Assuming that the plurality of phase circuits 111-118 are the first to eighth priority phase circuits respectively, when the triggering event occurs, the controller 120 can redefine or adjust the order of the plurality of phase circuits 111-118 to adjust the phase circuit 111 from the first priority phase circuit (i.e., the highest priority phase circuit) to the eighth priority phase circuit (i.e., the last priority phase circuit in the order of the plurality of phase circuits 111-118), and can adjust the remaining phase circuits 112-118 from the second to eighth priority phase circuits respectively to the first to seventh priority phase circuits, i.e., the highest priority phase circuit is updated to the phase circuit 112.

[0035] ​As described above, among the multiple phase circuits 111 to 118, the one considered the highest priority operating item will be preferentially enabled by the controller 120 from a high-impedance state to an active state when the enable quantity NPH increases from 1 to greater than 1, causing the corresponding one of the multiple drive signals PWM1 to PWM8 to switch between the enable level VH and the disable level VL. When the enable quantity NPH decreases to 1, the highest priority operating item is updated to another phase circuit, and the phase circuit that was the previous highest priority operating item is adjusted to the last priority operating item. For example, when phase circuit 112 is the highest priority operating item, when the enable quantity NPH increases from 1 to greater than 1, the controller 120 preferentially enables phase circuit 112 to be in an active state. When the enable quantity NPH decreases to 1, the highest priority operating item is updated from phase circuit 112 to phase circuit 113, and the phase circuit 112 that was the previous highest priority operating item is adjusted to the last priority operating item. The number of enable signals (NPH) for the multiple phase circuits 111-118 determines the number of drive signals that will switch between the enable level VH and the disable level VL (i.e., the number of phase circuits that will be active). Furthermore, the total number of phase circuits 111-118 minus the number of enable signals (NPH) results in the number of drive signals that will remain at the high impedance level VHIZ (i.e., the number of phase circuits that will remain in a high impedance state). Assuming an enable signal (NPH) of 3, three of the multiple phase circuits 111-118 are enabled and in an active state, while the remaining five are disabled and in a high impedance state.

[0036] It should be understood that the voltage conversion system 100 of this utility model is not limited to... Figure 1 The circuit architecture is shown. For example, the number of phases in the multiphase voltage converter 110 can be less than or greater than 8 (i.e., Figure 1 (The number of multiple drive circuits D1 to D8 or multiple phase circuits 111 to 118). In another example, the detection circuit 130 may be located inside the controller 120, that is, the voltage conversion system 100 may only include the multiphase voltage converter 110 and the controller 120, and the controller 120 may be able to detect the load current IOTT and realize the operation of the above circuit.

[0037] In the above embodiments, the controller 120 can be implemented using an application-specific integrated circuit (ASIC). Each drive signal PWM1 to PWM8 can be a pulse width modulation (PWM) signal. Each drive circuit D1 to D8 can be implemented using a gate driver. The detection circuit 130 can be implemented using a current sensor.

[0038] Next, pair Figure 3The circuit architecture of the controller 120 of this utility model will be further explained. Figure 3 The diagram illustrates a circuit block diagram of a controller 120 according to some embodiments of the present invention. In some embodiments, the controller 120 includes a feedback signal circuit 121, a phase management circuit 123, and a pulse width modulation circuit 125. The feedback signal circuit 121 is coupled to... Figure 1 The detection circuit 130 and the phase management circuit 123 are included. The phase management circuit 123 is coupled to the pulse width modulation circuit 125. Furthermore, the pulse width modulation circuit 125 is coupled to... Figure 1 The multiphase voltage converter 110 contains multiple drive circuits D1 to D8. For example... Figure 3 As shown, the feedback signal circuit 121 can generate a control signal CS based on the load current IOTT. The phase management circuit 123 can generate multiple enable signals EN1 to EN8 based on the control signal CS. The pulse width modulation circuit 125 can generate multiple drive signals PWM1 to PWM8 based on the multiple enable signals EN1 to EN8 respectively.

[0039] Next, pair Figure 4 The control method 400 shown and Figures 5-10 The circuit operation of controller 120 is illustrated using multiple scenarios of load LD. Figure 4 The flowchart illustrates a control method 400 according to some embodiments of the present invention. Figures 5-10 These are timing diagrams illustrating multiple enable signals EN1 to EN8 under various scenarios with a load LD, based on some embodiments of the present invention. In some embodiments, such as... Figure 4 As shown, the control method 400 includes multiple operations S401 to S402. However, the present invention is not limited thereto.

[0040] In operation S401, the controller 120 controls multiple phase circuits 111 to 118 in the multiphase voltage converter 110 according to the load current IOTT and the order of operation.

[0041] In some embodiments, in Figure 5 During the time period before time point TA1, the highest priority work item among the work items of multiple phase circuits 111 to 118 is set as phase circuit 111 by phase management circuit 123. That is, phase circuit 111 is the first priority work item, phase circuit 112 is the second priority work item, and so on.

[0042] During the time period before the time point TA1, the feedback signal circuit 121 determines the load state LST of the load LD according to the current level of the load current IOTT, and outputs a control signal CS to the phase management circuit 123 according to the load state LST. For example, the control signal CS can indicate that the number of enabled phase circuits NPH of the plurality of phase circuits 111-118 is 8. In this case, the phase management circuit 123 outputs a plurality of enable signals EN1-EN8 all of which are at a voltage level corresponding to logic 1 according to the control signal CS. The pulse width modulation circuit 125 outputs a plurality of drive signals PWM1-PWM8 each of which can have at least one pulse (e.g., the pulse PLS1) according to the corresponding one of the enable signals EN1-EN8. In other words, each of the drive signals PWM1-PWM8 can be switched from the disabled level VL to the enabled level VH, and then switched back from the enabled level VH to the disabled level VL. Also, each of the plurality of phase circuits 111-118 is in the active state, and is switched from the discharging state to the charging state, and then switched back from the charging state to the discharging state. Further, when the enable signals EN1-EN8 are all at the voltage level corresponding to logic 1, each of the drive signals PWM1-PWM8 has the at least one pulse, and the rising edges of the at least one pulse of each of two adjacent ones of the drive signals PWM1-PWM8 are different from each other by a predetermined time. Figure 2

[0043] In another example, the number of enabled phase circuits NPH of the plurality of phase circuits 111-118 is changed to 7 in response to a change in the load state LST. In this case, since the last priority operating item in the current operating item sequence is the phase circuit 118, the controller 120 will preferentially disable the phase circuit 118, i.e., the phase circuit 118 is preferentially switched from the active state to the high impedance state. Accordingly, the phase management circuit 123 outputs a plurality of enable signals EN1-EN7 all of which are at a voltage level corresponding to logic 1 according to the control signal CS, and the phase management circuit 123 outputs an enable signal EN8 at a voltage level corresponding to logic 0 according to the control signal CS. Also, each of the drive signals PWM1-PWM7 corresponding to the enable signals EN1-EN7 can have at least one pulse (e.g., the pulse PLS1), and the drive signal PWM8 corresponding to the enable signal EN8 does not have a pulse (i.e., remains at the high impedance level VHIZ). Also, each of the phase circuits 111-117 is in the active state, and is switched from the discharging state to the charging state, and then switched back from the charging state to the discharging state, and the phase circuit 118 remains at the high impedance state. The circuit operations of the phase management circuit 123 and the pulse width modulation circuit 125 when the number of enabled phase circuits NPH is any one of 2 to 6 during the time period before the time point TA1 can be similarly explained according to the above example, and thus will not be described here. Figure 2

[0044] ​​In operation S402, controller 120, in response to the trigger event, redefines the order of work items. In some embodiments, in Figure 5 At time TA1, the feedback signal circuit 121 determines, based on the load state LST, the enable quantity NPH of multiple phase circuits 111-118 to be adjusted to 1 (trigger event occurs), and outputs a control signal CS to the phase management circuit 123 accordingly. The phase management circuit 123 receives the control signal CS and switches the enable signal EN2 from the voltage level corresponding to logic 1 to the voltage level corresponding to logic 0, so that only phase circuit 111 (which is still the highest priority work item in the current work item sequence) in the multiphase voltage converter 110 is continuously enabled and in an active state. Furthermore, since the control signal CS instructs the enable quantity NPH of multiple phase circuits 111-118 to be adjusted to 1, the phase management circuit 123 redefines or adjusts the order of operation items, so as to adjust phase circuit 111 from the first priority operation item (i.e., the highest priority operation item) to the eighth priority operation item (i.e., the last priority operation item), and adjust the remaining phase circuits 112-118 from the second to the eighth priority operation items to the first to the seventh priority operation items respectively. Thus, it can be seen that the controller 120, in response to the enable quantity NPH of multiple phase circuits 111-118 becoming 1, adjusts phase circuit 112 from the second priority operation item to the highest priority operation item.

[0045] As described above, when the enable count NPH of multiple phase circuits 111 to 118 becomes 1, the controller 120 still enables phase circuit 111 according to the order of operations during the time period before time point TA1 (i.e., multiple phase circuits 111 to 118 are the first to eighth priority operations, respectively). At this time, if the controller 120 switches from enabling phase circuit 111 to enabling phase circuit 112 without increasing the enable count NPH of multiple phase circuits 111 to 118 to a number greater than 1, the operating efficiency of the voltage conversion system 100 will actually decrease. Therefore, during the time period when the highest priority operation is phase circuit 112 and the enable count NPH of multiple phase circuits 111 to 118 is 1 (i.e., the time period between time point TA1 and time point TA2), even though phase circuit 111 is no longer the highest priority operation, the controller 120 still enables phase circuit 111 instead of phase circuit 112.

[0046] exist Figure 5At time TA2, the feedback signal circuit 121 determines the enable quantity NPH of multiple phase circuits 111-118 to be 2 based on the load state LST, and outputs a control signal CS to the phase management circuit 123 accordingly. The phase management circuit 123 receives the control signal CS, and because the highest priority operation item is phase circuit 112, it prioritizes switching the enable signal EN2 from the voltage level corresponding to logic 0 to the voltage level corresponding to logic 1, so that phase circuits 112 and 111 are both in an active state after time TA2.

[0047] exist Figure 5 At time TA3, the feedback signal circuit 121 determines the enable quantity NPH of multiple phase circuits 111 to 118 to be 1 based on the load state LST, and outputs a control signal CS to the phase management circuit 123 accordingly. The phase management circuit 123 receives the control signal CS and switches the enable signal EN1 of the corresponding phase circuit 111 (the last priority work item in the current work item sequence) from the voltage level of the corresponding logic 1 to the voltage level of the corresponding logic 0, so that only phase circuit 112 (which is still the highest priority work item in the current work item sequence) in the multiphase voltage converter 110 is continuously enabled and in an active state. Furthermore, since the control signal CS instructs the enable count NPH of multiple phase circuits 111-118 to be adjusted to 1, the phase management circuit 123 redefines or adjusts the order of operations again, adjusting phase circuit 112 from the first priority operation to the eighth priority operation, adjusting the remaining phase circuits 113-118 from the second to the seventh priority operation to the first to the sixth priority operation respectively, and adjusting phase circuit 111 from the eighth priority operation to the seventh priority operation. Thus, it can be seen that the controller 120, in response to the enable count NPH of multiple phase circuits 111-118 becoming 1 (i.e., in response to a trigger event), adjusts phase circuit 113 from the second priority operation to the highest priority operation. Furthermore, similar to the above description, during the time period when the highest priority operation is phase circuit 113 and the enable count NPH of multiple phase circuits 111-118 is 1 (i.e., the time period between time point TA3 and time point TA4), the controller 120 still maintains the enable of phase circuit 112 but not phase circuit 113.

[0048] exist Figure 5At the time point TA4, the feedback signal circuit 121 determines to adjust the enabled number NPH of the plurality of phase circuits 111-118 to 2 according to the load state LST, and outputs a control signal CS to the phase management circuit 123 accordingly. The phase management circuit 123 receives the control signal CS, and preferentially switches the enable signal EN3 from a voltage level corresponding to logic 0 to a voltage level corresponding to logic 1 because the highest priority working item is the phase circuit 113, so that both the phase circuits 113 and 112 are in the active state after the time point TA4. The circuit operations of the phase management circuit 123 and the pulse width modulation circuit 125 when the enabled number NPH is any one of 3 to 6 after the time point TA4 can be analogized according to the above description to make the phase circuits 114-117 enter the active state in sequence, so the description is omitted here.

[0049] In the embodiment of Figure 6 , the circuit operations of the feedback signal circuit 121, the phase management circuit 123 and the pulse width modulation circuit 125 in the controller 120 in the time period before the time point TB1 or the time point TB2 are similar to the circuit operations of the feedback signal circuit 121, the phase management circuit 123 and the pulse width modulation circuit 125 in the controller 120 in the time period before the time point TA1 or the time point TA2, so the description is omitted here. Figure 5

[0050] In the embodiment of Figure 6 , the circuit operations of the feedback signal circuit 121, the phase management circuit 123 and the pulse width modulation circuit 125 in the controller 120 in the time period before the time point TB1 or the time point TB2 are similar to the circuit operations of the feedback signal circuit 121, the phase management circuit 123 and the pulse width modulation circuit 125 in the controller 120 in the time period before the time point TA1 or the time point TA2, so the description is omitted here.

[0051] In the embodiment of Figure 6 ​At the time point TB3, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 3 to 2 based on the load status LST, and to disable (i.e., switch to a high impedance state) the phase circuit 111, which is the last priority operating item, via the phase management circuit 123 and the pulse width modulation circuit 125. Thus, the phase circuits 112 and 113 are in the active state.

[0052] At Figure 6 At the time point TB4, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 2 to 1 based on the load status LST, and to disable (i.e., switch to a high impedance state) the phase circuit 113, which is the second priority operating item in the multiphase voltage converter 110, via the phase management circuit 123 and the pulse width modulation circuit 125, i.e., to control the multiphase voltage converter 110 such that only the phase circuit 112 is in the active state (because the phase circuit 112 was the highest priority operating item before the time point TB4). Also, in response to the number of enabled phases NPH of the plurality of phase circuits 111-118 becoming 1, the controller 120 redefines or adjusts the operating item order via the phase management circuit 123 to adjust the phase circuit 113 from the second priority operating item to the highest priority operating item. At the same time, the phase circuit 112 is adjusted from the highest priority operating item to the last priority operating item. It should be understood that the plurality of phase circuits 114-118 are adjusted to the second to sixth priority operating items, respectively, and the phase circuit 111 is adjusted to the seventh priority operating item.

[0053] At Figure 6 During the time period after the time point TB5, the controller 120 determines, via the feedback signal circuit 121, to gradually adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 1 to 4 based on the load status LST, and to sequentially enable the plurality of phase circuits 113-115 via the phase management circuit 123 and the pulse width modulation circuit 125. During the time period after the time point TB5, the first to third priority operating items are the plurality of phase circuits 113-115, respectively, and the last priority operating item is the phase circuit 112. Thus, the phase circuits 113, 114, 115, and 112 are in the active state. In short, when the phase circuit 113 is the highest priority operating item, the controller 120 is configured to respond to the number of enabled phases NPH of the plurality of phase circuits 111-118 changing from 1 to a number greater than 1 (e.g., 4) by switching at least the phase circuit 113 (e.g., the plurality of phase circuits 113-115) from the high impedance state to the active state based on the current operating item order starting from the phase circuit 113.

[0054] At Figure 7In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period before the time point TC1, the time point TC2, the time point TC3, or the time point TC4 similar to their operation in the time period before the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 6 The feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period after the time point TB1, the time point TB2, the time point TB3, or the time point TB4 similar to their operation in a time period after the time point TB1, the time point TB2, the time point TB3, or the time point TB4 of the embodiment shown in FIG. 8, and thus the description thereof is omitted herein.

[0055] In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period before the time point TC1, the time point TC2, the time point TC3, or the time point TC4 similar to their operation in the time period before the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 7 At the time point TC4 shown in FIG. 10, the phase circuit 112 is the highest priority active item, the phase circuits 113-118 are the second to seventh priority active items, respectively, and the phase circuit 111 is the last priority active item. In addition, the phase circuits 112 and 113 are in the active state, and the phase circuit 111 and the remaining phase circuits 114-118 are in the high impedance state.

[0056] In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period before the time point TC1, the time point TC2, the time point TC3, or the time point TC4 similar to their operation in the time period before the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 7 At the time point TC4 shown in FIG. 10, the phase circuit 112 is the highest priority active item, the phase circuits 113-118 are the second to seventh priority active items, respectively, and the phase circuit 111 is the last priority active item. In addition, the phase circuits 112 and 113 are in the active state, and the phase circuit 111 and the remaining phase circuits 114-118 are in the high impedance state.

[0057] In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period before the time point TC1, the time point TC2, the time point TC3, or the time point TC4 similar to their operation in the time period before the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 8 At the time point TD1 shown in FIG. 10, the phase circuit 111 is the first priority active item, the phase circuit 112 is the second priority active item, and the phase circuits 113-118 are the third to eighth priority active items, respectively. In addition, the phase circuits 111 and 112 are in the active state, and the remaining phase circuits 113-118 are in the high impedance state.

[0058] In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period before the time point TC1, the time point TC2, the time point TC3, or the time point TC4 similar to their operation in the time period before the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 8 The feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period after the time point TD1, the time point TD2, the time point TD3, or the time point TD4 similar to their operation in a time period after the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 5 The feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period after the time point TD1, the time point TD2, the time point TD3, or the time point TD4 similar to their operation in a time period after the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein.

[0059] In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate in a time period before the time point TC1, the time point TC2, the time point TC3, or the time point TC4 similar to their operation in the time period before the time point TA1, the time point TA2, the time point TA3, or the time point TA4 of the embodiment shown in FIG. 9, and thus the description thereof is omitted herein. Figure 8The period between the time point TD4 and the time point TD5, the controller 120 determines to adjust the enabled number NPH of the plurality of phase circuits 111-118 from 1 to 2 and then directly from 2 to 7 according to the load state LST through the feedback signal circuit 121, and enables the phase circuit 113 and then simultaneously enables the plurality of phase circuits 114-118 through the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the plurality of phase circuits 112-118 are all in the active state, and the phase circuit 111 is in the high impedance state.

[0060] At Figure 8 The time point TD5, the controller 120 determines to adjust the enabled number NPH of the plurality of phase circuits 111-118 from 7 to 6 according to the load state LST through the feedback signal circuit 121, and outputs the control signal CS to the phase management circuit 123 accordingly. At this time, the phase circuit 113 is the highest priority working item, the plurality of phase circuits 114-118 are the second to sixth order working items respectively, the phase circuit 111 is the seventh order working item, and the phase circuit 112 is the last priority working item. According to the control signal CS, the phase circuit 112 (before the time point TD5, the phase circuit 112 is the one with the lowest working order (the last priority working item) among all the enabled phase circuits 112-118) is disabled (i.e., the phase circuit 112 is switched to the high impedance state) through the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the plurality of phase circuits 113-118 are all in the active state, and the phase circuits 111 and 112 are in the high impedance state.

[0061] At Figure 9 The period before the time point TE1, the controller 120 determines to adjust the enabled number NPH of the plurality of phase circuits 111-118 from 8 to 7 and then from 7 to 6 according to the load state LST through the feedback signal circuit 121. Since the first to eighth order working items are the plurality of phase circuits 111-118 respectively at this time, the controller 120 disables the phase circuit 118 and then the phase circuit 117 through the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the plurality of phase circuits 111-116 are all in the active state, and the phase circuits 117 and 118 are both in the high impedance state.

[0062] At Figure 9At the time point TE1, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 directly from 6 to 1 according to the load state LST, and disables the phase circuits 112-116 in the multiphase voltage converter 110 via the phase management circuit 123 and the pulse width modulation circuit 125, that is, only the phase circuit 111 in the multiphase voltage converter 110 has the charging state (because the highest priority work item is the phase circuit 111 before the time point TE1). In response to the number of enabled phases NPH of the plurality of phase circuits 111-118 being 1, the controller 120 redefines or adjusts the work item order via the phase management circuit 123 to adjust the phase circuit 112 from the second order work item to the highest priority work item. Meanwhile, the phase circuit 111 is adjusted from the highest priority work item to the last priority work item. It should be understood that the plurality of phase circuits 113-118 are adjusted to the second to seventh order work items, respectively.

[0063] At the time point TE2, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 directly from 1 to 3 according to the load state LST. Since the phase circuits 112 and 113 are the first and second order work items, respectively, the controller 120 enables the phase circuits 112 and 113 via the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the phase circuits 112, 113, and 111 are in the active state, and the remaining plurality of phase circuits 114-118 are in the high impedance state. Figure 9 At the time point TE3, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 3 to 2 according to the load state LST. Since the phase circuit 111 is the last priority work item, the controller 120 disables the phase circuit 111 via the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the phase circuits 112 and 113 are in the active state, and the remaining plurality of phase circuits 114-118 and the phase circuit 111 are in the high impedance state.

[0064] Figure 9 At the time point TE4, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 2 to 1 according to the load state LST. Since the phase circuit 112 is the highest priority work item, the controller 120 enables the phase circuit 112 via the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the phase circuit 112 is in the active state, and the remaining plurality of phase circuits 113-118 are in the high impedance state.

[0065] At the time point TE5, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 1 to 2 according to the load state LST. Since the phase circuits 112 and 113 are the first and second order work items, respectively, the controller 120 enables the phase circuits 112 and 113 via the phase management circuit 123 and the pulse width modulation circuit 125. Therefore, the phase circuits 112, 113, and 111 are in the active state, and the remaining plurality of phase circuits 114-118 are in the high impedance state. Figure 9 ​At the time point TE4, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 2 to 1 in accordance with the load state LST, and disables the phase circuit 113 via the phase management circuit 123 and the pulse width modulation circuit 125, i.e., controls the multi-phase voltage converter 110 such that only the phase circuit 112 has the charging state (because the highest priority active item is the phase circuit 112 before the time point TE4). Also, in response to the number of enabled phases NPH of the plurality of phase circuits 111-118 becoming 1, the controller 120 redefines or adjusts the active item order via the phase management circuit 123 to adjust the phase circuit 113 from the second order active item to the highest priority active item. Meanwhile, the phase circuit 112 is adjusted from the highest priority active item to the last priority active item. It should be understood that the plurality of phase circuits 114-118 are adjusted to the second to sixth order active items, respectively, and the phase circuit 111 is adjusted to the seventh order active item.

[0066] At the time point TE5, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 directly from 1 to 7 in accordance with the load state LST. Since the plurality of phase circuits 113-118 are the first to sixth order active items, respectively, the controller 120 enables the plurality of phase circuits 113-118 via the phase management circuit 123 and the pulse width modulation circuit 125. Thus, the plurality of phase circuits 113-118 and the phase circuit 112 are in the active state, and the phase circuit 111 is in the high impedance state. Figure 9 At the time point TE6, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 directly from 7 to 1 in accordance with the load state LST, and disables the phase circuits 112 and 114-118 via the phase management circuit 123 and the pulse width modulation circuit 125, i.e., controls the multi-phase voltage converter 110 such that only the phase circuit 113 has the charging state (because the highest priority active item is the phase circuit 113 before the time point TE6). Also, in response to the number of enabled phases NPH of the plurality of phase circuits 111-118 becoming 1, the controller 120 redefines or adjusts the active item order via the phase management circuit 123 to adjust the phase circuit 114 from the second order active item to the highest priority active item. Meanwhile, the phase circuit 113 is adjusted from the highest priority active item to the last priority active item. It should be understood that the plurality of phase circuits 115-118 are adjusted to the second to fifth order active items, respectively, the phase circuit 111 is adjusted to the sixth order active item, and the phase circuit 112 is adjusted to the seventh order active item.

[0067] Figure 9 At the time point TE7, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 directly from 1 to 7 in accordance with the load state LST. Since the plurality of phase circuits 115-118 are the second to sixth order active items, respectively, the controller 120 enables the plurality of phase circuits 115-118 via the phase management circuit 123 and the pulse width modulation circuit 125. Thus, the plurality of phase circuits 115-118 and the phase circuit 111 are in the active state, and the phase circuits 112 and 113 are in the high impedance state.

[0068] At the time point TE8, the controller 120 determines, via the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 directly from 7 to 1 in accordance with the load state LST, and disables the phase circuits 115-118 via the phase management circuit 123 and the pulse width modulation circuit 125, i.e., controls the multi-phase voltage converter 110 such that only the phase circuit 116 has the charging state (because the highest priority active item is the phase circuit 116 before the time point TE8). Also, in response to the number of enabled phases NPH of the plurality of phase circuits 111-118 becoming 1, the controller 120 redefines or adjusts the active item order via the phase management circuit 123 to adjust the phase circuit 116 from the second order active item to the highest priority active item. Meanwhile, the phase circuit 115 is adjusted from the highest priority active item to the last priority active item. It should be understood that the plurality of phase circuits 111-114 and 117-118 are adjusted to the second to sixth order active items, respectively, and the phase circuit 112 is adjusted to the seventh order active item. Figure 10 ​In the embodiment shown in FIG. 10, the feedback signal circuit 121, the phase management circuit 123, and the pulse width modulation circuit 125 in the controller 120 operate similarly to their operations in the time period before the time point TA1 or the time point TA2, and thus the description thereof is omitted. Figure 5

[0069] In the time period between the time point TF2 and the time point TF3 shown in FIG. 9, the controller 120 determines, through the feedback signal circuit 121, to gradually adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 1 to 8 according to the load state LST, and sequentially enables the plurality of phase circuits 112-118 through the phase management circuit 123 and the pulse width modulation circuit 125. Thus, the plurality of phase circuits 112-118 and 111 are all in the active state. Figure 10

[0070] In the time period between the time point TF3 and the time point TF4 shown in FIG. 9, the controller 120 determines, through the feedback signal circuit 121, to gradually adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 8 to 2 according to the load state LST, and sequentially disables the plurality of phase circuits 111, 118, 117, 116, 115, and 114 (which are the eighth, seventh, sixth, fifth, fourth, and third order working items, respectively) through the phase management circuit 123 and the pulse width modulation circuit 125. Thus, the plurality of phase circuits 112 and 113 are both in the active state, and the plurality of phase circuits 114-118 and 111 are in the high impedance state. Figure 10

[0071] At the time point TF4 shown in FIG. 9, the controller 120 determines, through the feedback signal circuit 121, to adjust the number of enabled phases NPH of the plurality of phase circuits 111-118 from 2 to 1 according to the load state LST, and disables the phase circuit 113 through the phase management circuit 123 and the pulse width modulation circuit 125, that is, controls only the phase circuit 112 in the multiphase voltage converter 110 to have the charging state (because the highest priority working item is the phase circuit 112 before the time point TF4). In response to the number of enabled phases NPH of the plurality of phase circuits 111-118 becoming 1, the controller 120 redefines or adjusts the working item order through the phase management circuit 123 to adjust the phase circuit 113 from the second order working item to the highest priority working item. At the same time, the phase circuit 112 is also adjusted from the highest priority working item to the last priority working item. It should be understood that the plurality of phase circuits 114-118 are adjusted to the second to sixth order working items, respectively, and the phase circuit 111 is adjusted to the seventh order working item. Figure 10

[0072] ​​​​In the above embodiments, when the enabled number NPH of the plurality of phase circuits 111-118 becomes 1, the controller 120 redefines or adjusts the working item sequence of the plurality of phase circuits 111-118 through the phase management circuit 123, but the present application is not limited thereto. For example, in some embodiments, the controller 120 can adjust the working item sequence of the plurality of phase circuits 111-118 through the feedback signal circuit 121 or an additional circuit (not shown), and the feedback signal circuit 121 or the aforementioned additional circuit transmits the adjusted working item sequence to the phase management circuit 123.

[0073] As can be seen from the above embodiments of the present application, by redefining or adjusting the working item sequence of the plurality of phase circuits 111-118 in response to the enabled number NPH of the plurality of phase circuits 111-118 becoming 1 (i.e. in response to the triggering event) through the controller 120, the voltage conversion system 100 of the present application can average the working periods of the plurality of phase circuits 111-118 in the multiphase voltage converter 110, thereby achieving the technical effect of effectively improving the efficiency and reliability of the voltage conversion system 100.

[0074] Although the present application has been disclosed with embodiments as above, it is not intended to limit the present application, and those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application, and therefore the protection scope of the present application shall be defined by the appended claims.

[0075]

Symbol Description

[0076] 100: voltage conversion system

[0077] 110: multiphase voltage converter

[0078] 111-118: phase circuit

[0079] 120: controller

[0080] 121: feedback signal circuit

[0081] 123: phase management circuit

[0082] 125: pulse width modulation circuit

[0083] 130: detection circuit

[0084] 400: control method

[0085] CO: capacitor

[0086] CS: control signal

[0087] D1-D8: drive circuit

[0088] EN1-EN8: enable signal

[0089] HS: upper bridge switch

[0090] IOTT: load current

[0091] L: inductance

[0092] LD: load

[0093] LS: lower bridge switch

[0094] LST: load state

[0095] NPH: number of enablement

[0096] P1, P2: period

[0097] PLS1: pulse

[0098] PWMX, PWM1-PWM8: drive signal

[0099] S401, S402: operation

[0100] TA1, TA2, TA3, TA4, TB1, TB2, TB3, TB4, TB5, TC1, TC2, TC3, TC4, TD1, TD2, TD3, TD4, TD5, TE1, TE2, TE3, TE4, TE5, TE6, TF1, TF2, TF3, TF4: time point

[0101] VH: enablement level

[0102] VHIZ: high impedance level

[0103] VIN: input voltage

[0104] VL: disablement level.

Claims

1. A voltage conversion system, characterized in that, Include: A multiphase voltage converter coupled to a load and comprising a plurality of phase circuits, wherein the plurality of phase circuits are coupled to the load and at least one of the plurality of phase circuits is active to enable the multiphase voltage converter to provide load current to the load; as well as A controller, coupled to the multiphase voltage converter, is configured to enable at least one of the multiple phase circuits to be in the active state according to the load current and the operating item sequence of the multiple phase circuits, and to adjust the operating item sequence in response to the enable number of the multiple phase circuits becoming 1, so as to adjust the first of the multiple phase circuits from the second priority operating item to the highest priority operating item.

2. The voltage conversion system according to claim 1, characterized in that, When the first of the plurality of phase circuits is adjusted from the second priority operation item to the highest priority operation item, the second of the plurality of phase circuits is adjusted from the highest priority operation item to the lowest priority operation item.

3. The voltage conversion system according to claim 2, characterized in that, When the enable number of the plurality of phase circuits becomes 1, the second of the plurality of phase circuits is in the active state, while the others of the plurality of phase circuits are in a high impedance state.

4. The voltage conversion system according to claim 2, characterized in that, When the number of enabled phase circuits changes from 1 to 2, the first and second phase circuits are in the active state, while the remaining phase circuits are in a high-impedance state.

5. The voltage conversion system according to claim 2, characterized in that, When the first of the plurality of phase circuits is the highest priority work item, the controller is configured to, in response to the enable number of the plurality of phase circuits changing from 1 to a number greater than 1, switch at least the first of the plurality of phase circuits from a high impedance state to the active state, starting with the first of the plurality of phase circuits, according to the work item order.

6. The voltage conversion system according to claim 5, characterized in that, When the first of the plurality of phase circuits is the highest priority work item, the controller adjusts the work item order in response to the enable number of the plurality of phase circuits becoming 1, so as to adjust the third of the plurality of phase circuits from the second priority work item to the highest priority work item.

7. The voltage conversion system according to claim 6, characterized in that, When the third of the plurality of phase circuits is adjusted from the second priority operation item to the highest priority operation item, the first of the plurality of phase circuits is adjusted from the highest priority operation item to the last priority operation item.

8. The voltage conversion system according to claim 7, characterized in that, When the third party in the plurality of phase circuits is the highest priority working item, the controller is configured to, in response to the enable number of the plurality of phase circuits changing from 1 to a number greater than 1, switch at least the third party in the plurality of phase circuits from the high impedance state to the active state, starting with the third party in the plurality of phase circuits, according to the working item order.

9. The voltage conversion system according to claim 1, characterized in that, The multiphase voltage converter further includes: Multiple drive circuits are coupled to the multiple phase circuits and the controller, and are used to drive the multiple phase circuits according to multiple drive signals output by the controller.

10. The voltage conversion system according to claim 9, characterized in that, The controller includes: A feedback signal circuit is used to output a control signal based on the load current, wherein the control signal is used to indicate the number of enabled phase circuits; A phase management circuit, coupled to the feedback signal circuit, is used to output multiple enable signals according to the control signal, and to adjust the working order of the multiple phase circuits in response to the enable number of the multiple phase circuits becoming 1. as well as A pulse width modulation circuit is coupled to the phase management circuit and the multiphase voltage converter, and is used to output the multiple drive signals to the multiphase voltage converter according to the multiple enable signals.

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