Display device and electronic apparatus

Abstract

The utility model discloses a display device and electronic equipment. The display device includes: a display panel including a panel test pad portion; the printed circuit board comprises a PCB test bonding pad part and a test terminal; and a flexible circuit board including a first transfer pad portion electrically connected to the panel test pad portion and a second transfer pad portion electrically connected to the PCB test pad portion, in which the panel test pad portion includes first to third panel pads, the PCB test pad portion includes a first PCB pad electrically connected to the first panel pad, a second PCB pad and a third PCB pad electrically connected to the second panel pad, and a fourth PCB pad electrically connected to the third panel pad, the test terminal includes a first input terminal electrically connected to the first PCB pad, a second input terminal, and first to third measurement terminals electrically connected to the second to fourth PCB pads, respectively.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0033322, filed on March 8, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments disclosed herein relate to display devices, and more specifically, to display devices that facilitate inspection of the bonding state between a display panel and a flexible circuit board, as well as the bonding state between the flexible circuit board and a printed circuit board. Background Technology

[0004] A display device may include a display panel, a flexible circuit board (PCB), and a printed circuit board (PCB), with the PCB electrically connected to the display panel via the PCB. For this purpose, pads on the PCB can be bonded to pads on the display panel, and another pad on the PCB can be bonded to a pad on the PCB. As the resolution of display devices increases, the size and spacing of these pads decrease, and the bonding of the PCB, PCB, and display panel may require more precise positioning. The bonding quality between the PCB and the display panel, and between the PCB and the PCB, can significantly affect the accurate transmission of electrical signals to the display panel. Therefore, it may be necessary to test the bonding quality between the PCB and the display panel, and between the PCB and the PCB. Utility Model Content

[0005] One or more embodiments disclosed herein may include a display device that facilitates inspection of the bonding state between a flexible circuit board and a display panel, and between a flexible circuit board and a printed circuit board. Additional aspects are set forth in part in the following description and will be apparent in part from the description, or may be learned by practice of the embodiments presented in this disclosure. The embodiments set forth herein are merely examples, and embodiments of this disclosure are not limited to these examples.

[0006] According to one or more embodiments, a display device includes a display panel including a panel test pad portion, a printed circuit board including a printed circuit board (PCB) test pad portion and a test terminal, and a flexible circuit board including a first transfer pad portion electrically connected to the panel test pad portion and a second transfer pad portion electrically connected to the PCB test pad portion, wherein the panel test pad portion includes a first panel pad, a second panel pad, and a third panel pad, the PCB test pad portion includes a first PCB pad electrically connected to the first panel pad, a second PCB pad electrically connected to the second panel pad, a third PCB pad electrically connected to the second panel pad, and a fourth PCB pad electrically connected to the third panel pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad, a second input terminal, a first measurement terminal electrically connected to the second PCB pad, a second measurement terminal electrically connected to the third PCB pad, and a third measurement terminal electrically connected to the fourth PCB pad.

[0007] The second input terminal can be electrically connected to the second PCB pad, and when a test current is applied to the first input terminal, the test current can flow through a current path including the first PCB pad, the first panel pad, the second panel pad, and the second PCB pad.

[0008] The first transfer pad portion can include a 1-1 transfer pad overlapping the first panel pad, a 1-2 transfer pad overlapping the second panel pad, and a 1-3 transfer pad overlapping the third panel pad, and the second transfer pad portion can include a 2-1 transfer pad overlapping the first PCB pad, a 2-2 transfer pad overlapping the second PCB pad, a 2-3 transfer pad overlapping the third PCB pad, and a 2-4 transfer pad overlapping the fourth PCB pad, wherein the 2-1 transfer pad can be electrically connected to the 1-1 transfer pad through a first wiring, the 2-2 transfer pad can be electrically connected to the 1-2 transfer pad through a second wiring, the 2-3 transfer pad can be electrically connected to the 1-2 transfer pad through the second wiring and a sub-wiring connected to the second wiring, and the 2-4 transfer pad can be electrically connected to the 1-3 transfer pad through a third wiring.

[0009] The display device can further include an integrated circuit (IC) chip including an IC test pad portion, wherein the display panel can further include an IC transfer pad portion electrically connected to the IC test pad portion, and the IC test pad portion can include a first IC test pad, a second IC test pad, and a third IC test pad, wherein the first IC test pad can be electrically connected to the first panel pad, and the second IC test pad can be electrically connected to the second panel pad.

[0010] The second input terminal can be electrically connected to the second PCB pad, and when a test current is applied to the first input terminal, the test current can flow through a current path including the first PCB pad, the first panel pad, the first IC test pad, the second IC test pad, the second panel pad, and the second PCB pad.

[0011] The IC transmission pad portion can include a first IC transmission pad overlapping the first IC test pad, a second IC transmission pad overlapping the second IC test pad, and a third IC transmission pad overlapping the third IC test pad, and the panel test pad portion can further include a fourth panel pad and a fifth panel pad, wherein the first panel pad can be electrically connected to the first IC transmission pad through a first panel wiring, the second panel pad can be electrically connected to the second IC transmission pad through a second panel wiring, the third panel pad can be electrically connected to the second IC transmission pad through the second panel pad and a third panel wiring electrically connecting the second panel pad to the third panel pad, the fourth panel pad can be electrically connected to the second IC transmission pad through a fourth panel wiring, and the fifth panel pad can be electrically connected to the third IC transmission pad through a fifth panel wiring.

[0012] The PCB test pad portion can further include a fifth PCB pad electrically connected to the fourth panel pad and a sixth PCB pad electrically connected to the fifth panel pad, and the test terminal can further include a fourth measurement terminal electrically connected to the fifth PCB pad and a fifth measurement terminal electrically connected to the sixth PCB pad.

[0013] A plurality of panel test pad portions can be provided, a plurality of PCB test pad portions can be provided, and a plurality of flexible circuit boards can be provided, wherein the plurality of flexible circuit boards can be respectively positioned to correspond to the plurality of panel test pad portions and to correspond to the plurality of PCB test pad portions.

[0014] The first input terminal can be electrically connected to the first PCB pad of the first PCB pad group of the first PCB test pad portion among the plurality of PCB test pad portions through a first PCB wiring, and the second input terminal can be electrically connected to the first PCB pad of the second PCB pad group of the second PCB test pad portion among the plurality of PCB test pad portions through a second PCB wiring.

[0015] A plurality of first measurement terminals, a plurality of second measurement terminals, and a plurality of third measurement terminals electrically connected to the plurality of PCB test pad portions, respectively, can be provided.

[0016] According to one or more embodiments, a display device includes a display panel including a panel test pad portion, a printed circuit board including a printed circuit board (PCB) test pad portion and a test terminal, and a flexible circuit board including a first transfer pad portion electrically connected to the panel test pad portion and a second transfer pad portion electrically connected to the PCB test pad portion, wherein the panel test pad portion includes a first panel pad and a second panel pad, the first transfer pad portion includes a 1-1 transfer pad overlapping the first panel pad and a 1-2 transfer pad overlapping the second panel pad, the second transfer pad portion includes a 2-1 transfer pad electrically connected to the 1-1 transfer pad through a first wiring, a 2-2 transfer pad electrically connected to the 1-2 transfer pad through a second wiring, and a 2-3 transfer pad electrically connected to the 1-2 transfer pad through the second wiring and a sub wiring connected to the second wiring, the PCB test pad portion includes a first PCB pad overlapping the 2-1 transfer pad, a second PCB pad overlapping the 2-2 transfer pad, and a third PCB pad overlapping the 2-3 transfer pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad, a second input terminal electrically connected to the second PCB pad, a first measurement terminal electrically connected to the second PCB pad, and a second measurement terminal electrically connected to the third PCB pad.

[0017] When a test current is applied to the first input terminal, the test current can flow through a current path including the first PCB pad, the first panel pad, the second panel pad, and the second PCB pad.

[0018] The panel test pad portion can further include a third panel pad electrically connected to the first panel pad and the second panel pad, the PCB test pad portion can further include a fourth PCB pad electrically connected to the third panel pad, and the test terminal can further include a third measurement terminal electrically connected to the fourth PCB pad.

[0019] According to one or more embodiments, a display apparatus includes a display panel including a first panel test pad portion and a second panel test pad portion, a printed circuit board including a first PCB test pad portion, a second PCB test pad portion, and a test terminal, and a first flexible circuit board and a second flexible circuit board, the first flexible circuit board having one end connected to the first panel test pad portion and an opposite end connected to the first PCB test pad portion, the second flexible circuit board having one end connected to the second panel test pad portion and an opposite end connected to the second PCB test pad portion, wherein each of the first PCB test pad portion and the second PCB test pad portion includes a first PCB pad group and a second PCB pad group, each of the first PCB pad group and the second PCB pad group includes a first PCB pad, a second PCB pad, a third PCB pad, and a fourth PCB pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad of the first PCB pad group of the first PCB test pad portion, a second input terminal electrically connected to the first PCB pad of the first PCB pad group of the second PCB test pad portion, a first measurement terminal portion electrically connected to the second PCB pad of the first PCB pad group of the first PCB test pad portion, and a second measurement terminal portion electrically connected to the second PCB pad of the second PCB pad group of the second PCB test pad portion, wherein each of the first measurement terminal portion and the second measurement terminal portion includes a 1-1 measurement terminal electrically connected to the second PCB pad of the first PCB pad group, a 2-1 measurement terminal electrically connected to the third PCB pad of the first PCB pad group, a 3-1 measurement terminal electrically connected to the fourth PCB pad of the first PCB pad group, a 1-2 measurement terminal electrically connected to the second PCB pad of the second PCB pad group, a 2-2 measurement terminal electrically connected to the third PCB pad of the second PCB pad group, and a 3-2 measurement terminal electrically connected to the fourth PCB pad of the second PCB pad group.

[0020] The second PCB pad of the first PCB pad group of the first PCB test pad portion can be electrically connected to the second PCB pad of the second PCB pad group of the first PCB test pad portion, the first PCB pad of the first PCB pad group of the second PCB test pad portion can be electrically connected to the first PCB pad of the second PCB pad group of the first PCB test pad portion, and the second PCB pad of the first PCB pad group of the second PCB test pad portion can be electrically connected to the second PCB pad of the second PCB pad group of the second PCB test pad portion.

[0021] The first panel test pad portion can include a first panel pad, a second panel pad, and a third panel pad, the first PCB pad of the first PCB pad group of the first PCB test pad portion can be electrically connected to the first panel pad, the second PCB pad of the first PCB pad group of the first PCB test pad portion can be electrically connected to the second panel pad, the third PCB pad of the first PCB pad group of the first PCB test pad portion can be electrically connected to the second panel pad, and the fourth PCB pad of the first PCB pad group of the first PCB test pad portion can be electrically connected to the third panel pad.

[0022] When the test current is applied to the first input terminal, the test current can flow through a current path including the first PCB pad of the first PCB pad group of the first PCB test pad portion, the first panel pad, the second panel pad, and the second PCB pad of the first PCB pad group of the first PCB test pad portion.

[0023] The first flexible circuit board can include a first transfer pad portion connected to the first panel test pad portion and a second transfer pad portion connected to the first PCB test pad portion, wherein the first transfer pad portion can include a 1-1 transfer pad overlapping the first panel pad, a 1-2 transfer pad overlapping the second panel pad, and a 1-3 transfer pad overlapping the third panel pad, and the second transfer pad portion can include a 2-1 transfer pad, a 2-2 transfer pad, a 2-3 transfer pad, and a 2-4 transfer pad overlapping the first PCB pad, the second PCB pad, the third PCB pad, and the fourth PCB pad of the first PCB pad group of the first PCB test pad portion, respectively, wherein the 1-1 transfer pad and the 2-1 transfer pad can be electrically connected to each other by a first wiring, the 1-2 transfer pad and the 2-2 transfer pad can be electrically connected to each other by a second wiring, the 1-2 transfer pad and the 2-3 transfer pad can be electrically connected to each other by the second wiring and a sub-wiring connected to the second wiring, and the 1-3 transfer pad and the 2-4 transfer pad can be electrically connected to each other by a third wiring.

[0024] The display apparatus can further include an integrated circuit chip including an IC test pad portion, wherein the display panel can further include an IC transfer pad portion electrically connected to the IC test pad portion, and the IC test pad portion can include a first IC test pad, a second IC test pad, and a third IC test pad, wherein the first IC test pad can be electrically connected to the first panel pad, and the second IC test pad can be electrically connected to the second panel pad.

[0025] When a test current is applied to the first input terminal, the test current can flow through the current path of the first PCB pad of the first PCB pad group, which includes the first PCB test pad portion, the first panel pad, the first IC test pad, the second IC test pad, the second panel pad, and the second PCB pad of the first PCB pad group of the first PCB test pad portion.

[0026] According to one or more embodiments, an electronic device includes a display device and a housing accommodating the display device, wherein the display device may include: a display panel including a panel test pad portion; a printed circuit board including a printed circuit board (PCB) test pad portion and test terminals; and a flexible circuit board including a first transmission pad portion electrically connected to the panel test pad portion and a second transmission pad portion electrically connected to the PCB test pad portion, wherein the panel test pad portion may include a first panel pad, a second panel pad, and a third panel pad, the PCB test pad portion may include a first PCB pad electrically connected to the first panel pad, a second PCB pad electrically connected to the second panel pad, a third PCB pad electrically connected to the second panel pad, and a fourth PCB pad electrically connected to the third panel pad, and the test terminals may include a first input terminal electrically connected to the first PCB pad, a second input terminal electrically connected to the second PCB pad, a first measurement terminal electrically connected to the second PCB pad, a second measurement terminal electrically connected to the third PCB pad, and a third measurement terminal electrically connected to the fourth PCB pad. Attached Figure Description

[0027] The above and other aspects, features, and advantages of certain embodiments of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0028] FIG. 1A This is a schematic plan view of a display device according to an embodiment;

[0029] FIG. 1B This is a schematic plan view of a display device according to an embodiment;

[0030] FIG. 2 According to the embodiments FIG. 1A A magnified view of region "A";

[0031] FIG. 3 According to the embodiments, it does not include flexible circuit boards and integrated circuit chips. FIG. 1A A magnified view of region "A";

[0032] FIG. 4 The diagram is based on FIG. 2 and FIG. 3 A perspective view of the structure in the current path used during connection resistance measurement in an embodiment;

[0033] FIG. 5 is an enlarged view of the area "A" of FIG. 1A

[0034] FIG. 6 is an enlarged view of the area "A" of FIG. 1A

[0035] FIG. 7 is a perspective view illustrating a structure in a current path used during connection resistance measurement according to an embodiment of FIG. 5 and FIG. 6

[0036] FIG. 8 is an enlarged view of the area "B" of FIG. 1B

[0037] FIG. 9 is an enlarged view of an area corresponding to the first flexible circuit board and the second flexible circuit board in FIG. 8

[0038] FIG. 10 is an enlarged view of FIG. 9

[0039] FIG. 11 is a perspective view illustrating a structure in a current path used during connection resistance measurement according to an embodiment of FIG. 8 to FIG. 10

[0040] FIG. 12 is an enlarged view of the area "B" of FIG. 1B

[0041] FIG. 13 is an enlarged view of an area corresponding to the first flexible circuit board and the second flexible circuit board in FIG. 12

[0042] FIG. 14 is an enlarged view of FIG. 13

[0043] FIG. 15 is a perspective view illustrating a structure in a current path used during connection resistance measurement according to an embodiment of FIG. 12 to FIG. 14

[0044] FIG. 16 is a schematic cross-sectional view within a display area of a display panel included in a display device according to an embodiment. DETAILED DESCRIPTION

[0045] ​​​​​​​​​​​Reference will now be made in detail to embodiments of the application, examples of which are illustrated in the accompanying drawings. In this regard, the embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are described below, by referring to the drawings, only, to explain aspects of the present description.

[0046] The present disclosure can include various embodiments and modifications, and embodiments of the present disclosure will be illustrated in the accompanying drawings and will be described in detail in the present document. The effects and features of the present disclosure and its accompanying methods will become apparent from the following description of the embodiments in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments described below and can be embodied in various modes.

[0047] In the present specification, the terms "first", "second", and the like can be used to describe various elements, but the elements should not be limited by the terms. The terms are used only to distinguish one component from another component.

[0048] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] In the present specification, the terms "include", "comprise", "have", and / or "contain" specify the presence of stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0050] In the present specification, expressions such as "A and / or B" mean A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, expressions such as "at least one of A and B" mean A, B, or A and B. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0051] In the present specification, an element such as a film, a layer, a region, or a plate referred to as "on" or "formed on" another element can be directly or indirectly on or formed on the other element. That is, for example, there can be an intervening film, layer, region, or plate.

[0052] In the present specification, a layer, a region, or an element referred to as "connected" means that the layer, region, or element can be directly connected, or can be indirectly connected with an intervening layer, region, or element therebetween. For example, a layer, a region, or an element referred to as "electrically connected to" or "electrically coupled to" another layer, region, or element can be directly or indirectly electrically connected or coupled to the other layer, region, or element. That is, for example, there can be an intervening layer, region, or element therebetween.

[0053] In the present specification, the x-axis, the y-axis, and the z-axis are not limited to three axes in an orthogonal coordinate system, and can be interpreted in a broad sense including these axes. For example, the x-axis, the y-axis, and the z-axis can represent different directions orthogonal to each other, or can represent different directions not orthogonal to each other.

[0054] In the present specification, a specific embodiment of a process can be described and related, but embodiments of the present disclosure can not be limited to a specific process sequence and can be performed in a different order from that described. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to that described.

[0055] In the present specification, "in a plan view" refers to viewing a main body portion from above. That is, in the present specification, "in a plan view" can refer to "when viewed in a direction perpendicular to a display panel."

[0056] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same reference numerals will be given to the same or corresponding components. The sizes of the elements in the drawings can be exaggerated or reduced for the convenience of description. In other words, since the sizes and thicknesses of the elements in the drawings are illustrated for the convenience of description, the following embodiments are not limited thereto.

[0057] FIG. 1A and FIG. 1B is a schematic plan view of a display device 1.

[0058] Referring to FIG. 1A and FIG. 1B , the display device 1 can include a display panel 10, a flexible circuit board 20, and a printed circuit board 30. The display device 1 can further include an integrated circuit chip 40.

[0059] The display panel 10 can include a display area DA and a non-display area NDA. The display area DA can be an area in which a plurality of pixels PX display an image. Signal lines such as scan lines SL and / or data lines DL can be arranged in the display area DA. Each of the pixels PX can include sub-pixels, and the sub-pixels can emit light having a specific color by using a light emitting diode as a display element. For example, each light emitting diode can emit red light, green light, or blue light. Each light emitting diode can be connected to a pixel circuit including a thin film transistor and a storage capacitor.

[0060] The non-display area NDA can be an area in which an image is not provided. The non-display area NDA can surround the display area DA.

[0061] The driver for providing an electric signal to the pixel PX and / or the power line for providing electric power can be located in the non-display area NDA. For example, a scan driver for providing a scan signal to each pixel PX through the scan line SL and / or a data driver for providing a data signal to each pixel PX through the data line DL can be located in the non-display area NDA. In an embodiment, the data driver can have the same form as the integrated circuit chip 40.

[0062] The display panel 10 can include a first pad area PADA1 including a plurality of pads. The first pad area PADA1 can be located in the non-display area NDA. The first pad area PADA1 can be an area including a plurality of pads electrically connecting the display panel 10 to the flexible circuit board 20. One end portion of the flexible circuit board 20 can be located on the first pad area PADA1 of the display panel 10. For example, a plurality of pads provided at one end portion of the flexible circuit board 20 can respectively overlap a plurality of pads in the first pad area PADA1 of the display panel 10. For example, in the first pad area PADA1, the display panel 10 can include a panel test pad portion AP (see FIG. 3 ) and a first panel signal transmission pad SA (see FIG. 3 ). For example, the flexible circuit board 20 can include a first transmission pad portion FAP (see FIG. 2 ) and a first signal transmission pad FSA (see FIG. 2 ) overlapping the first pad area PADA1 of the display panel 10.

[0063] The printed circuit board 30 can include a second pad area PADA2 including a plurality of pads. The second pad area PADA2 can be an area including pads electrically connecting the flexible circuit board 20 to the printed circuit board 30. One end portion of the flexible circuit board 20 can be disposed on the first pad area PADA1 of the display panel 10, and the other end portion can be disposed on the second pad area PADA2 of the printed circuit board 30. For example, a plurality of pads disposed on the end portion of the flexible circuit board 20 opposite the first pad area PADA1 can overlap a plurality of pads in the second pad area PADA2 of the printed circuit board 30. As further described below, the printed circuit board 30 can include a printed circuit board (PCB) test pad portion BP (see FIG. 3 ) and a PCB output signal pad SB (see FIG. 3 ) in the second pad area PADA2. The flexible circuit board 20 can include a second transmission pad portion FBP (see FIG. 2 ) and a second signal transmission pad FSB (see FIG. 2 ) overlapping the second pad area PADA2 of the printed circuit board 30.

[0064] One end of the flexible circuit board 20 can overlap the display panel 10, and the other end of the flexible circuit board 20 can overlap the printed circuit board 30. One end of the flexible circuit board 20 can be connected to the display panel 10, and the other end of the flexible circuit board 20 can be connected to the printed circuit board 30.

[0065] In an embodiment, the display device 1 can include one flexible circuit board 20, as shown in FIG. 1A. In this case, the display panel 10 can include one panel test pad portion AP (see FIG. 1A) corresponding to a first transfer pad portion FAP of the flexible circuit board 20. In addition, the printed circuit board 30 can include one PCB test pad portion BP (see FIG. 1A) corresponding to a second transfer pad portion FBP of the flexible circuit board 20. FIG. 1A FIG. 3 ) of the display panel 10. In addition, the printed circuit board 30 can include one PCB test pad portion BP (see FIG. 3 ) corresponding to the second transfer pad portion FBP of the flexible circuit board 20.

[0066] In an embodiment, the display device 1 can include a plurality of flexible circuit boards 20, as shown in FIG. 1B. In this case, the display panel 10 can include a plurality of panel test pad portions AP (see FIG. 1B), and the printed circuit board 30 can include a plurality of PCB test pad portions BP (see FIG. 1B). The plurality of panel test pad portions AP (see FIG. 1B) and the plurality of PCB test pad portions BP (see FIG. 1B) can be electrically connected to each other through the plurality of flexible circuit boards 20. When the display device 1 includes the plurality of flexible circuit boards 20, a plurality of integrated circuit chips 40 can be provided. FIG. 1B FIG. 3 FIG. 3 FIG. 3 FIG. 3

[0067] A processor and / or a memory, etc. can be located on the printed circuit board 30. For example, when the display device 1 is applied to a mobile communication terminal, the processor can be an application processor including a central processing unit, a graphic processing unit, and / or a modem. The flexible circuit board 20 can be bent, and thus the printed circuit board 30 can be located on the back surface of the display panel 10.

[0068] FIG. 1A FIG. 1B FIGS. 1A and 1B show examples in which the integrated circuit chip 40 is mounted on the non-display area NDA of the display panel 10. The integrated circuit chip 40 can be mounted on the non-display area NDA of the display panel 10 as a chip on glass (COG) type, or can be mounted on the flexible circuit board 20 as a chip on film (COF) type. Hereinafter, for convenience of description, the following description will focus on the integrated circuit chip 40 mounted on the display panel 10. However, the present disclosure is not limited thereto. For example, the integrated circuit chip 40 can be mounted on the flexible circuit board 20.

[0069] ​​​​​​​The signals output from the integrated circuit chip 40 can be transmitted to the display panel 10 through an integrated circuit (IC) output signal pad ISD (see FIG. 2 ) of the integrated circuit chip 40 and an IC input signal pad SD (see FIG. 3 ) of the display panel 10. In an embodiment, the integrated circuit chip 40 can receive signals from the printed circuit board 30 and can use the signals (e.g., image data and signals related thereto or power) as a basis for generating data signals. The signals from the printed circuit board 30 can be transmitted to the PCB input signal pad ISC (see FIG. 2 ) of the integrated circuit chip 40 through the PCB output signal pad SB of the printed circuit board 30, the first and second signal transmission pads FSA and FSB of the flexible circuit board 20, and the first and second panel signal transmission pads SA and SC (see FIG. 3 ) of the display panel 10.

[0070] The electronic device can include the display apparatus 1. For example, the electronic device can include a portable electronic device such as a mobile phone, a laptop computer, a tablet personal computer (PC), a smart phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, or an ultra-mobile PC (UMPC). For example, the electronic device can include a television, a monitor, a billboard, an electronic device for the Internet of Things (IoT), or a wearable electronic device such as a smart watch, a watch phone, a glasses-type display, or a head-mounted display (HMD). For example, the electronic device can include a display panel of a vehicle, a central information display (CID) arranged on a center panel or an instrument panel of a vehicle, a rearview mirror display that replaces a side mirror of a vehicle, or an electronic device for display arranged on a rear surface of a front seat as an entertainment facility of a rear seat of a vehicle. For example, the electronic device can include a flat panel display, a curved display, a computer monitor, a medical monitor, a television, a billboard, indoor or outdoor lighting, a signal light, a head-up display, a fully or partially transparent display, a flexible display (e.g., a rollable display, a foldable display, a stretchable display), a laser printer, a phone (e.g., a mobile phone), a tablet, a phablet, a personal digital assistant (PDA), a wearable device, a laptop computer, a digital camera, a camcorder, a viewfinder, a micro display, a 3D display, a virtual reality or augmented reality display, a vehicle, a video wall including a plurality of displays tiled, a theater or stadium screen, a light therapy device, or a sign. According to an embodiment, the electronic device including the display apparatus 1 of FIG. 1A or FIG. 1B may include a lower cover disposed under the display apparatus 1. According to an embodiment, the electronic device can further include a cover window disposed on the display apparatus 1. For example, the lower cover and the cover window can be combined and form an appearance of the electronic device.

[0071] FIG. 2 is according to an embodiment FIG. 1A is an enlarged view of area "A" of FIG. 3 is an embodiment of FIG. 1A is an enlarged view of area "A" of

[0072] Referring to FIG. 2 and FIG. 3 , the display panel 10 can include a panel test pad portion AP. The printed circuit board 30 can include a PCB test pad portion BP and a test terminal TP.

[0073] A first transfer pad portion FAP disposed at one end of the flexible circuit board 20 can be electrically connected to the panel test pad portion AP, and a second transfer pad portion FBP disposed at the other end of the flexible circuit board 20 can be electrically connected to the PCB test pad portion BP. The first transfer pad portion FAP can overlap the panel test pad portion AP, and the second transfer pad portion FBP can overlap the PCB test pad portion BP. As shown in FIG. 4 , anisotropic conductive film ACF can electrically connect transfer pads of the first transfer pad portion FAP to panel pads of the panel test pad portion AP. Likewise, anisotropic conductive film ACF can electrically connect transfer pads of the second transfer pad portion FBP to PCB pads of the PCB test pad portion BP.

[0074] The panel test pad portion AP can include a first panel pad group ALG and a second panel pad group ARG each including a plurality of panel pads. The first panel pad group ALG and the second panel pad group ARG can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the first panel pad group ALG and the second panel pad group ARG can each include a first panel pad A1, a second panel pad A2, and a third panel pad A3. The first panel pad A1, the second panel pad A2, and the third panel pad A3 can be connected (e.g., electrically connected) to each other. The panel pads of the panel test pad portion AP can be test pads that can be used to measure connection resistance between the display panel 10 and the flexible circuit board 20.

[0075] The PCB test pad portion BP can include a first PCB pad group BLG and a second PCB pad group BRG each including a plurality of PCB pads. The first PCB pad group BLG and the second PCB pad group BRG can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the first PCB pad group BLG and the second PCB pad group BRG can each include a first PCB pad B1, a second PCB pad B2, a third PCB pad B3, and a fourth PCB pad B4. The PCB pads of the PCB test pad portion BP can be test pads that can be used to measure a connection resistance between the flexible circuit board 20 and the printed circuit board 30.

[0076] The test terminals TP can include a first test terminal group TPG1 and a second test terminal group TPG2. The first test terminal group TPG1 and the second test terminal group TPG2 can be mirror-symmetrical to each other with respect to the y-axis. The first test terminal group TPG1 can be electrically connected to the first PCB pad group BLG, and the second test terminal group TPG2 can be electrically connected to the second PCB pad group BRG. The first test terminal group TPG1 and the second test terminal group TPG2 can each include a first input terminal IT, a second input terminal OT, a first measurement terminal MT1, a second measurement terminal MT2, and a third measurement terminal MT3. The first input terminal IT can be electrically connected to the first PCB pad B1. The second input terminal OT and the first measurement terminal MT1 can be electrically connected to the second PCB pad B2. The second measurement terminal MT2 can be electrically connected to the third PCB pad B3. The third measurement terminal MT3 can be electrically connected to the fourth PCB pad B4.

[0077] The first transfer pad portion FAP can include a first-1 transfer pad group FALG and a first-2 transfer pad group FARG each including a plurality of transfer pads. The first-1 transfer pad group FALG and the first-2 transfer pad group FARG can be mirror-symmetrical to each other with respect to the y-axis. The first-1 transfer pad group FALG and the first-2 transfer pad group FARG can each include a first-1 transfer pad FA1, a first-2 transfer pad FA2, and a first-3 transfer pad FA3. The first-1 transfer pad FA1 can overlap the first panel pad A1, the first-2 transfer pad FA2 can overlap the second panel pad A2, and the first-3 transfer pad FA3 can overlap the third panel pad A3. The transfer pads of the first transfer pad portion FAP can be test pads for measuring a connection resistance between the display panel 10 and the flexible circuit board 20.

[0078] The second transmission pad portion FBP can include a 2-1 transmission pad group FBLG and a 2-2 transmission pad group FBRG each including a plurality of transmission pads. The 2-1 transmission pad group FBLG and the 2-2 transmission pad group FBRG can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the 2-1 transmission pad group FBLG and the 2-2 transmission pad group FBRG can each include a 2-1 transmission pad FB1, a 2-2 transmission pad FB2, a 2-3 transmission pad FB3, and a 2-4 transmission pad FB4. The 2-1 transmission pad FB1 can overlap the first PCB pad B1, the 2-2 transmission pad FB2 can overlap the second PCB pad B2, the 2-3 transmission pad FB3 can overlap the third PCB pad B3, and the 2-4 transmission pad FB4 can overlap the fourth PCB pad B4. The transmission pads of the second transmission pad portion FBP can be test pads for measuring connection resistance between the flexible circuit board 20 and the printed circuit board 30.

[0079] The 2-1 transmission pad FB1 can be electrically connected to the 1-1 transmission pad FA1 through a first wiring FWL1 in the flexible circuit board 20. The 2-2 transmission pad FB2 can be electrically connected to the 1-2 transmission pad FA2 through a second wiring FWL21. The 2-3 transmission pad FB3 can be electrically connected to the 1-2 transmission pad FA2 through a sub-wiring FWL22 which can be connected to the second wiring FWL21. In an embodiment, the 2-3 transmission pad FB3 can be electrically connected to the 1-2 transmission pad FA2 through the sub-wiring FWL22 and the second wiring FWL21. The 2-4 transmission pad FB4 can be electrically connected to the 1-3 transmission pad FA3 through a third wiring FWL3. The first wiring FWL1, the second wiring FWL21, the sub-wiring FWL22, and the third wiring FWL3 can be disposed in or on the flexible circuit board 20. Each of the first wiring FWL1, the second wiring FWL21, the third wiring FWL3, and the sub-wiring FWL22 can include a conductive material having low resistance. For example, each of the first wiring FWL1, the second wiring FWL21, the third wiring FWL3, and the sub-wiring FWL22 can include a conductive material including copper (Cu).

[0080] The flexible circuit board 20 can electrically connect the first PCB pad B1 of the printed circuit board 30 to the first panel pad A1 of the display panel 10. For example, the first PCB pad B1 can be electrically connected to the first panel pad A1 through the 2-1 transfer pad FB1 and the 1-1 transfer pad FA1. The second PCB pad B2 can be electrically connected to the second panel pad A2. For example, the second PCB pad B2 can be electrically connected to the second panel pad A2 through the 2-2 transfer pad FB2 and the 1-2 transfer pad FA2. The third PCB pad B3 can be electrically connected to the second panel pad A2. For example, the third PCB pad B3 can be electrically connected to the second panel pad A2 through the 2-3 transfer pad FB3 and the 1-2 transfer pad FA2. The fourth PCB pad B4 can be electrically connected to the third panel pad A3. For example, the fourth PCB pad B4 can be electrically connected to the third panel pad A3 through the 2-4 transfer pad FB4 and the 1-3 transfer pad FA3.

[0081] The display panel 10 can further include one or more first panel signal transfer pads SA and one or more second panel signal transfer pads SC. A plurality of first panel signal transfer pads SA and a plurality of second panel signal transfer pads SC can be provided. In an embodiment, the first panel signal transfer pads SA can be located between the first panel pad group ALG and the second panel pad group ARG. In an embodiment, the second panel signal transfer pads SC can overlap the integrated circuit chip 40. The display panel 10 can further include an IC input signal pad SD overlapping the integrated circuit chip 40.

[0082] The integrated circuit chip 40 can further include a PCB input signal pad ISC electrically connected to the second panel signal transfer pad SC and an IC output signal pad ISD electrically connected to the IC input signal pad SD.

[0083] The flexible circuit board 20 can further include one or more first signal transfer pads FSA and one or more second signal transfer pads FSB. A plurality of first signal transfer pads FSA and a plurality of second signal transfer pads FSB can be provided. In an embodiment, the first signal transfer pads FSA can be located between the 1-1 transfer pad group FALG and the 1-2 transfer pad group FARG. In an embodiment, the second signal transfer pads FSB can be located between the 2-1 transfer pad group FBLG and the 2-2 transfer pad group FBRG.

[0084] The printed circuit board 30 can further include one or more PCB output signal pads SB. A plurality of PCB output signal pads SB can be provided. In an embodiment, the PCB output signal pads SB can be located between the first PCB pad group BLG and the second PCB pad group BRG.

[0085] The first signal transmission pad FSA, the second signal transmission pad FSB, the first panel signal transmission pad SA, and the second panel signal transmission pad SC can electrically connect the PCB output signal pad SB of the printed circuit board 30 to the PCB input signal pad ISC of the integrated circuit chip 40. Accordingly, signals from the printed circuit board 30 can be transmitted to the integrated circuit chip 40.

[0086] The signals output from the integrated circuit chip 40 can be transmitted to the data line DL of the display panel 10, etc. through the IC output signal pad ISD (see FIG. 2 ) of the integrated circuit chip 40 and the IC input signal pad SD (see FIG. 3 ) of the display panel 10.

[0087] FIG. 4 Perspective views illustrating structures in a current path used during connection resistance measurement are shown. FIG. 2 and FIG. 3 .

[0088] Referring to FIG. 2 to FIG. 4 , when a test current is applied to the first input terminal IT, the test current can flow along a current path from the first input terminal IT to the second input terminal OT. The second input terminal OT can be referred to as an output terminal. In an embodiment, when a test current is applied to the first input terminal IT, the current can flow through a current path including the first PCB pad B1, the first panel pad A1, the second panel pad A2, and the second PCB pad B2. In an embodiment, when a test current is applied to the first input terminal IT, the test current can flow through a current path including the first PCB pad B1, the 2-1 transmission pad FB1, the 1-1 transmission pad FA1, the first panel pad A1, the second panel pad A2, the 1-2 transmission pad FA2, the 2-2 transmission pad FB2, and the second PCB pad B2.

[0089] In an embodiment, a current source for measuring a connection resistance between the panel test pad portion AP and the first transfer pad portion FAP (hereinafter referred to as a first connection resistance) and a current source for measuring a connection resistance between the PCB test pad portion BP and the second transfer pad portion FBP (hereinafter referred to as a second connection resistance) can be connected to each other in a common current structure. In the present specification, the term "common current structure" can refer to a structure in which a plurality of current sources share a common current path. That is, a current source for measuring a first connection resistance between the display panel 10 and the flexible circuit board 20 and a current source for measuring a second connection resistance between the flexible circuit board 20 and the printed circuit board 30 can be connected to each other in a common current structure. The common current structure can be connected to apply a current to the first input terminal IT and the second input terminal OT for simultaneous measurement or independent measurement of the first connection resistance and the second connection resistance.

[0090] The second connection resistance R2 is a connection resistance between the second transfer pad portion FBP of the flexible circuit board 20 and the PCB test pad portion BP of the printed circuit board 30, and can be measured by electrically connecting a current source to allow a current to flow from the first input terminal IT to the second input terminal OT and through a connection voltmeter to measure a voltage of the first measurement terminal MT1 and a voltage of the second measurement terminal MT2. A voltage difference between the first measurement terminal MT1 and the second measurement terminal MT2 can be used to derive the second connection resistance.

[0091] The first connection resistance R1 is a connection resistance between the first transfer pad portion FAP of the flexible circuit board 20 and the panel test pad portion AP of the display panel 10, and can be measured by electrically connecting a current source to allow a current to flow from the first input terminal IT to the second input terminal OT and through a connection voltmeter to measure a voltage of the second measurement terminal MT2 and a voltage of the third measurement terminal MT3. A voltage difference between the third measurement terminal MT3 and the second measurement terminal MT2 can be used to derive the first connection resistance.

[0092] In an embodiment, the first wiring FWL1, the second wiring FWL21, and the third wiring FWL3 can be disposed on the flexible circuit board 20, and can each have a low resistance value. In an embodiment, in order to further reduce the resistance value of the second wiring FWL21, the width of the second wiring FWL21 can be made greater than the width of the first wiring FWL1 or the width of the third wiring FWL3. In an embodiment, the thicknesses of the first wiring FWL1, the second wiring FWL21, the third wiring FWL3, and the sub-wiring FWL22 can be substantially the same.

[0093] Each trace connecting the first transfer pad portion FAP to the second transfer pad portion FBP (e.g., first to third traces FWL1, FWL21, and FWL3) can have a low resistance value, resulting in a small voltage difference between the first transfer pad portion FAP and the second transfer pad portion FBP. As described above, the second measurement terminal MT2 connected to the third PCB pad B3 can be used for both the measurement of the first connection resistance and the measurement of the second connection resistance. For example, since sub-trace FWL22 is connected between the second trace FWL21, which connects the first-second transfer pad FA2 and the second-second transfer pad FB2 to each other, and thus the third PCB pad B3 is electrically connected to the first-second transfer pad FA2, the second measurement terminal MT2 can be used for both the measurement of the first connection resistance and the measurement of the second connection resistance.

[0094] In the embodiment, as described above, the current source for measuring the first connection resistance between the panel test pad portion AP and the first transfer pad portion FAP and the current source for measuring the second connection resistance between the PCB test pad portion BP and the second transfer pad portion FBP can be connected to each other in a common current structure, and the second measurement terminal MT2 can be used for both the measurement of the first connection resistance and the measurement of the second connection resistance, and thus, the number of test terminals TP and the number of transfer pads arranged in the second transfer pad portion FBP can be reduced.

[0095] Based on reference FIG. 2 to FIG. 4 In the case of the display device 1 described in the embodiment, for each test pad group (e.g., the first test pad group TPG1 and the second test pad group TPG2), the number of test terminals TP used to measure both the first connection resistance between the panel test pad portion AP and the first transfer pad portion FAP, and the second connection resistance between the PCB test pad portion BP and the second transfer pad portion FBP is five. Furthermore, for each second transfer pad group (e.g., the second-1st transfer pad group FBLG and the second-2nd transfer pad group FBRG), the number of transfer pads of the second transfer pad portion FBP required to measure the first connection resistance and the second connection resistance is four.

[0096] In the comparative example using a separate 4-terminal measurement, a total of four test terminals, including two input terminals and two measurement terminals, are required to measure the first connection resistance between the panel test pad portion AP and the first transfer pad portion FAP. Similarly, to measure the second connection resistance between the PCB test pad portion BP and the second transfer pad portion FBP, a total of four test terminals, including two input terminals and two measurement terminals, are required. Therefore, for each test pad group, the number of test terminals required to measure both the first and second connection resistances according to the comparative example is eight.

[0097] However, in the display device 1 according to the present embodiment, for each test pad group (e.g., the first test pad group TPG1 and the second test pad group TPG2), the number of test terminals TP required to measure both the first connection resistance and the second connection resistance can be reduced to 5. This reduces the space occupied by the test terminals TP on the printed circuit board 30, and as a result, the restrictions on the design and arrangement of the test pads can be significantly reduced, and the printed circuit board 30 can be downsized.

[0098] FIG. 5 is an enlarged view of the area "A" according to the embodiment. FIG. 1A is an enlarged view of the area "A" according to the embodiment. FIG. 6 is a view of the display panel 10 excluding the flexible circuit board 20 and the integrated circuit chip 40. FIG. 1A is an enlarged view of the area "A" according to the embodiment. FIG. 5 and FIG. 6 The embodiment shown in FIG. 2 and FIG. 3 described above and identified by like reference numerals in FIG. 2 and FIG. 3 may be omitted in the interest of brevity where the most significant FIG. 5 and FIG. 6 of the components are the same as those described above, and the following description will focus on the differences between the components shown in

[0099] With reference to FIG. 5 and FIG. 6 , the integrated circuit chip 40 can further include an IC test pad portion ICP. The display panel 10 can further include an IC transmission pad portion CP electrically connected to the IC test pad portion ICP of the integrated circuit chip 40. The IC transmission pad portion CP of the display panel 10 can overlap the IC test pad portion ICP of the integrated circuit chip 40. The IC transmission pads of the IC transmission pad portion CP can be respectively electrically connected to the IC test pads of the IC test pad portion ICP. The IC test pads of the IC test pad portion ICP and the IC transmission pads of the IC transmission pad portion CP can serve as test pads for measuring the connection resistance between the display panel 10 and the integrated circuit chip 40.

[0100] The IC test pad portion ICP can include a first IC test pad group ICLG and a second IC test pad group ICRG each including a plurality of IC test pads. The first IC test pad group ICLG and the second IC test pad group ICRG can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the first IC test pad group ICLG and the second IC test pad group ICRG can each include a first IC test pad IC1, a second IC test pad IC2, and a third IC test pad IC3. The first IC test pad IC1, the second IC test pad IC2, and the third IC test pad IC3 can be connected (e.g., electrically connected) to each other.

[0101] In an embodiment, the PCB input signal pad ISC can be located between the first IC test pad group ICLG and the second IC test pad group ICRG. In an embodiment, the IC output signal pad ISD can be located between the first IC test pad group ICLG and the second IC test pad group ICRG.

[0102] The IC transmission pad portion CP can include a first IC transmission pad group CLG and a second IC transmission pad group CRG each including a plurality of IC transmission pads. The first IC transmission pad group CLG and the second IC transmission pad group CRG can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the first IC transmission pad group CLG and the second IC transmission pad group CRG can each include a first IC transmission pad C1, a second IC transmission pad C2, and a third IC transmission pad C3. The first IC transmission pad C1 can overlap the first IC test pad IC1, the second IC transmission pad C2 can overlap the second IC test pad IC2, and the third IC transmission pad C3 can overlap the third IC test pad IC3.

[0103] The panel test pad portion APa of the display panel 10 can include a first panel pad group ALGa and a second panel pad group ARGa each including a plurality of panel pads. The first panel pad group ALGa and the second panel pad group ARGa can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the first panel pad group ALGa and the second panel pad group ARGa can each include a first panel pad A1a, a second panel pad A2a, a third panel pad A3a, a fourth panel pad A4a, and a fifth panel pad A5a.

[0104] The first panel pad A1a can be electrically connected to the first IC transmission pad C1 through a first panel wire WL1. The second panel pad A2a can be electrically connected to the second IC transmission pad C2 through a second panel wire WL2. The third panel pad A3a can be electrically connected to the second panel pad A2a through a third panel wire WL3. In an embodiment, the third panel wire WL3 can connect the second panel pad A2a and the third panel pad A3a to each other. In an embodiment, the third panel pad A3a can be electrically connected to the second IC transmission pad C2 through the third panel wire WL3 and the second panel pad A2a. The fourth panel pad A4a can be electrically connected to the second IC transmission pad C2 through a fourth panel wire WL4. The fifth panel pad A5a can be electrically connected to the third IC transmission pad C3 through a fifth panel wire WL5. The first panel wire WL1, the second panel wire WL2, the third panel wire WL3, the fourth panel wire WL4, and the fifth panel wire WL5 can be disposed in or on the display panel 10.

[0105] The PCB test pad portion BPa can include a first PCB pad group BLGa and a second PCB pad group BRGa, each including a plurality of PCB pads that can be in or on the printed circuit board 30. The first PCB pad group BLGa and the second PCB pad group BRGa can be mirror-symmetrical to each other with respect to the y-axis. In an embodiment, the first PCB pad group BLGa and the second PCB pad group BRGa can each include a first PCB pad B1a, a second PCB pad B2a, a third PCB pad B3a, a fourth PCB pad B4a, a fifth PCB pad B5a, and a sixth PCB pad B6a.

[0106] The test terminal TPa can include a first test terminal group TPG1a and a second test terminal group TPG2a that can be in or on the printed circuit board 30. The first test terminal group TPG1a and the second test terminal group TPG2a can be mirror-symmetrical to each other with respect to the y-axis. The first test terminal group TPG1a can be electrically connected to the first PCB pad group BLGa, and the second test terminal group TPG2a can be electrically connected to the second PCB pad group BRGa.

[0107] The first and second test terminal groups TPG1a, TPG2a can each include a first input terminal ITa, a second input terminal OTa, a first measurement terminal MT1a, a second measurement terminal MT2a, a third measurement terminal MT3a, a fourth measurement terminal MT4a, and a fifth measurement terminal MT5a. The first input terminal ITa can be electrically connected to the first PCB pad B1a. The second input terminal OTa and the first measurement terminal MT1a can be electrically connected to the second PCB pad B2a. The second measurement terminal MT2a can be electrically connected to the third PCB pad B3a. The third measurement terminal MT3a can be electrically connected to the fourth PCB pad B4a. The fourth measurement terminal MT4a can be electrically connected to the fifth PCB pad B5a. The fifth measurement terminal MT5a can be electrically connected to the sixth PCB pad B6a.

[0108] The first transmission pad portion FAPa can include a first-1 transmission pad group FALGa and a first-2 transmission pad group FARGa, each group including a plurality of transmission pads that can be in or on the flexible circuit board 20. The first-1 transmission pad group FALGa and the first-2 transmission pad group FARGa can be mirror-symmetrical to each other with respect to the y-axis. The first-1 transmission pad group FALGa and the first-2 transmission pad group FARGa can each include a first-1 transmission pad FA1a, a first-2 transmission pad FA2a, a first-3 transmission pad FA3a, a first-4 transmission pad FA4a, and a first-5 transmission pad FA5a. The first-1 transmission pad FA1a can overlap the first panel pad A1a, the first-2 transmission pad FA2a can overlap the second panel pad A2a, and the first-3 transmission pad FA3a can overlap the third panel pad A3a. The first-4 transmission pad FA4a can overlap the fourth panel pad A4a, and the first-5 transmission pad FA5a can overlap the fifth panel pad A5a.

[0109] The second transmission pad portion FBPa can include a 2-1 transmission pad group FBLGa and a 2-2 transmission pad group FBRGa, each including a plurality of transmission pads that can be in or on the flexible circuit board 20. The 2-1 transmission pad group FBLGa and the 2-2 transmission pad group FBRGa can be mirror-symmetrical to each other with respect to the y-axis. In embodiments, the 2-1 transmission pad group FBLGa and the 2-2 transmission pad group FBRGa can each include a 2-1 transmission pad FB1a, a 2-2 transmission pad FB2a, a 2-3 transmission pad FB3a, a 2-4 transmission pad FB4a, a 2-5 transmission pad FB5a, and a 2-6 transmission pad FB6a. The 2-1 transmission pad FB1a can overlap the first PCB pad B1a, the 2-2 transmission pad FB2a can overlap the second PCB pad B2a, and the 2-3 transmission pad FB3a can overlap the third PCB pad B3a. The 2-4 transmission pad FB4a can overlap the fourth PCB pad B4a, the 2-5 transmission pad FB5a can overlap the fifth PCB pad B5a, and the 2-6 transmission pad FB6a can overlap the sixth PCB pad B6a.

[0110] The 2-1 transmission pad FB1a can be electrically connected to the 1-1 transmission pad FA1a by a first wiring FWL1a. The 2-2 transmission pad FB2a can be electrically connected to the 1-2 transmission pad FA2a by a second wiring FWL21a. The 2-3 transmission pad FB3a can be electrically connected to the 1-2 transmission pad FA2a by a sub-wiring FWL22a, which can be connected to the second wiring FWL21a. In embodiments, the 2-3 transmission pad FB3a can be electrically connected to the 1-2 transmission pad FA2a by the sub-wiring FWL22a and the second wiring FWL21a. The 2-4 transmission pad FB4a can be electrically connected to the 1-3 transmission pad FA3a by a third wiring FWL3a. The 2-5 transmission pad FB5a can be electrically connected to the 1-4 transmission pad FA4a by a fourth wiring FWL4a. The 2-6 transmission pad FB6a can be electrically connected to the 1-5 transmission pad FA5a by a fifth wiring FWL5a. The first wiring FWL1a, the second wiring FWL21a, the sub-wiring FWL22a, the third wiring FWL3a, the fourth wiring FWL4a, and the fifth wiring FWL5a can be in or on the flexible circuit board 20.

[0111] The first wiring FWL1a, the second wiring FWL21a, the third wiring FWL3a, the fourth wiring FWL4a, the fifth wiring FWL5a, and the sub-wiring FWL22a may each comprise a conductive material with low resistance. For example, the first wiring FWL1a, the second wiring FWL21a, the third wiring FWL3a, the fourth wiring FWL4a, the fifth wiring FWL5a, and the sub-wiring FWL22a may each comprise a conductive material containing copper (Cu). In an embodiment, the resistance of each of the first wiring FWL1a, the second wiring FWL21a, the third wiring FWL3a, the fourth wiring FWL4a, the fifth wiring FWL5a, and the sub-wiring FWL22a may be less than the resistance of each of the first panel wiring WL1, the second panel wiring WL2, the third panel wiring WL3, the fourth panel wiring WL4, and the fifth panel wiring WL5.

[0112] like FIG. 7 The anisotropic conductive film ACF shown can electrically connect the transfer pads of the first transfer pad portion FAPa to the panel pads of the panel test pad portion APa. The anisotropic conductive film ACF can also electrically connect the transfer pads of the second transfer pad portion FBPa to the PCB pads of the PCB test pad portion BPa. Furthermore, the anisotropic conductive film ACF can electrically connect the transfer pads of the IC transfer pad portion CP to the IC test pads of the IC test pad portion ICP.

[0113] The first PCB pad B1a can be electrically connected to the first panel pad A1a. For example, the first PCB pad B1a can be electrically connected to the first panel pad A1a through the 2-1 transfer pad FB1a and the 1-1 transfer pad FA1a. The second PCB pad B2a can be electrically connected to the second panel pad A2a. For example, the second PCB pad B2a can be electrically connected to the second panel pad A2a through the 2-2 transfer pad FB2a and the 1-2 transfer pad FA2a. The third PCB pad B3a can be electrically connected to the second panel pad A2a. For example, the third PCB pad B3a can be electrically connected to the second panel pad A2a through the 2-3 transfer pad FB3a and the 1-2 transfer pad FA2a. The fourth PCB pad B4a can be electrically connected to the third panel pad A3a. For example, the fourth PCB pad B4a can be electrically connected to the third panel pad A3a through the 2-4 transfer pad FB4a and the 1-3 transfer pad FA3a. The fifth PCB pad B5a can be electrically connected to the fourth panel pad A4a. For example, the fifth PCB pad B5a can be electrically connected to the fourth panel pad A4a through the 2-5 transfer pad FB5a and the 1-4 transfer pad FA4a. The sixth PCB pad B6a can be electrically connected to the fifth panel pad A5a. For example, the sixth PCB pad B6a can be electrically connected to the fifth panel pad A5a through the 2-6 transfer pad FB6a and the 1-5 transfer pad FA5a.

[0114] The first panel pad A1a can be electrically connected to the first IC test pad IC1. For example, the first panel pad A1a can be electrically connected to the first IC test pad IC1 through the first IC transfer pad C1. The second panel pad A2a can be electrically connected to the second IC test pad IC2. For example, the second panel pad A2a can be electrically connected to the second IC test pad IC2 through the second IC transfer pad C2. The third panel pad A3a can be electrically connected to the second IC test pad IC2. For example, the third panel pad A3a can be electrically connected to the second IC test pad IC2 through the second panel pad A2a and the second IC transfer pad C2. The fourth panel pad A4a can be electrically connected to the second IC test pad IC2. For example, the fourth panel pad A4a can be electrically connected to the second IC test pad IC2 through the second IC transfer pad C2. The fifth panel pad A5a can be electrically connected to the third IC test pad IC3. For example, the fifth panel pad A5a can be electrically connected to the third IC test pad IC3 through the third IC transfer pad C3.

[0115] FIG. 7 A perspective view of a structure in a current path used during a connection resistance measurement is shown conceptually illustrating embodiments according to FIG. 5 and FIG. 6 ​

[0116] Reference FIG. 5 to FIG. 7 When a test current is applied to the first input terminal ITa, a current path is formed between the first input terminal ITa and the second input terminal OTa. In an embodiment, when a test current is applied to the first input terminal ITa, the test current can flow through a current path including the first PCB pad B1a, the first panel pad A1a, the first IC test pad IC1, the second IC test pad IC2, the second panel pad A2a, and the second PCB pad B2a. In an embodiment, when a test current is applied to the first input terminal ITa, the test current can flow through a current path including the first PCB pad B1a, the 2-1 transfer pad FB1a, the 1-1 transfer pad FA1a, the first panel pad A1a, the first IC transfer pad C1, the first IC test pad IC1, the second IC test pad IC2, the second IC transfer pad C2, the second panel pad A2a, the 1-2 transfer pad FA2a, the 2-2 transfer pad FB2a, and the second PCB pad B2a.

[0117] In an embodiment, a current source for measuring a connection resistance between the IC transfer pad portion CP and the IC test pad portion ICP (hereinafter referred to as a third connection resistance), a current source for measuring a connection resistance between the panel test pad portion APa and the first transfer pad portion FAPa (e.g., a first connection resistance), and a current source for measuring a connection resistance between the PCB test pad portion BPa and the second transfer pad portion FBPa (e.g., a second connection resistance) can be connected to each other in a common current structure. That is, a current source for measuring a third connection resistance between the display panel 10 and the integrated circuit chip 40, a current source for measuring a first connection resistance between the display panel 10 and the flexible circuit board 20, and a current source for measuring a second connection resistance between the flexible circuit board 20 and the printed circuit board 30 can be connected to each other in a common current structure.

[0118] A second connection resistance, which is a resistance between the second transfer pad portion FBPa of the flexible circuit board 20 and the PCB test pad portion BPa of the printed circuit board 30, can be measured by electrically connecting a current source to allow a current to flow from the first input terminal ITa to the second input terminal OTa and by connecting a voltmeter to each of the first measurement terminal MT1a and the second measurement terminal MT2a to measure a voltage of the first measurement terminal MT1a and a voltage of the second measurement terminal MT2a.

[0119] is a first connection resistance of the resistance between the first transmission pad portion FAPa of the flexible circuit board 20 and the panel test pad portion APa of the display panel 10, which can be measured by electrically connecting a current source to allow a current from the first input terminal ITa to the second input terminal OTa and by connecting a voltmeter to each of the second measurement terminal MT2a and the third measurement terminal MT3a to measure the voltage of the second measurement terminal MT2a and the voltage of the third measurement terminal MT3a.

[0120] is a third connection resistance of the resistance between the IC test pad portion ICP of the integrated circuit chip 40 and the IC transmission pad portion CP of the display panel 10, which can be measured by electrically connecting a current source to the first input terminal ITa and the second input terminal OTa to apply a current and by connecting a voltmeter to each of the fourth measurement terminal MT4a and the fifth measurement terminal MT5a to measure the voltage of the fourth measurement terminal MT4a and the voltage of the fifth measurement terminal MT5a.

[0121] In an embodiment, similar to the embodiments described with reference to FIG. 2 to FIG. 4 In an embodiment, similar to the embodiments described with reference to

[0122] The first to fifth panel wirings WL1, WL2, WL3, WL4, and WL5 provided on the display panel 10 can have a resistance value greater than that of the first to fifth wirings FWL1a, FWL2la, FWL3a, FWL4a, and FWL5a provided on the flexible circuit board 20. Thus, the third connection resistance between the IC transmission pad portion CP of the display panel 10 and the IC test pad portion ICP of the integrated circuit chip 40 can be measured using other measurement terminals (e.g., fourth measurement terminal MT4a and fifth measurement terminal MT5a) separate from the measurement terminals (e.g., first measurement terminal MT1a and second measurement terminal MT2a) for measuring the second connection resistance and the measurement terminals (e.g., second measurement terminal MT2a and third measurement terminal MT3a) for measuring the first connection resistance.

[0123] Thus, in the case of the display device 1 according to the embodiment described above, the number of test terminals TPa required to measure all of the first connection resistance between the panel test pad portion APa and the first transmission pad portion FAPa, the second connection resistance between the PCB test pad portion BPa and the second transmission pad portion FBPa, and the third connection resistance between the IC transmission pad portion CP and the IC test pad portion ICP is seven for each test pad group (e.g., first test pad group TPG1a and second test pad group TPG2a). Further, the number of transmission pads of the second transmission pad portion FBPa required to measure the first to third connection resistances is six for each second transmission pad group (e.g., 2-1 transmission pad group FBLGa and 2-2 transmission pad group FBRGa). FIG. 5 to FIG. 7 As described above, the number of test terminals required to measure the first and second connection resistances using the typical 4-terminal measurement method is eight for each test pad group. Further, in the case of the typical 4-terminal measurement method, a total of four test terminals including two input terminals and two measurement terminals are required to measure the third connection resistance between the display panel 10 and the integrated circuit chip 40. That is, the number of test terminals required to measure all of the first to third connection resistances using the typical 4-terminal measurement method is eight for each test pad group.

[0124] In the display device 1 according to the embodiment, the number of test terminals TPa required to measure all of the first, second, and third connection resistances can be reduced to seven for each test pad group (e.g., first test pad group TPG1a and second test pad group TPG2a).

[0125]

[0126] is a display device according to an embodiment FIG. 8 FIG. 1B ​an enlarged view of the area "B" of FIG. 1. FIG. 9 is an enlarged view of an embodiment of the area corresponding to the first flexible circuit board 20a and the second flexible circuit board 20b in FIG. 8 FIG. 10 is an enlarged view of the area "A" of FIG. 1 excluding the first flexible circuit board 20a and the second flexible circuit board 20b and the first integrated circuit chip 40a and the second integrated circuit chip 40b. FIG. 9

[0127] FIG. 8 to FIG. 10 The embodiment shown in FIG. 1 includes some of the same components described above with reference to FIG. 2 and FIG. 3 and identified by the same or similar reference numerals as those used in FIG. 2 and FIG. 3 and thus, redundant descriptions of these components can be omitted from the following description in order to focus on FIG. 8 to FIG. 10 how the components in FIG. 1 differ from the components described above.

[0128] Referring to FIG. 8 to FIG. 10 , the display panel 10 can include a plurality of panel test pad portions AP. For example, the display panel 10 can include a first panel test pad portion AP1, a second panel test pad portion AP2, a third panel test pad portion AP3, and a fourth panel test pad portion AP4. Although FIG. 8 four panel test pad portions AP are shown, the present disclosure is not limited thereto. For example, three or more panel test pad portions AP can be provided. In an embodiment, the structures of the panel test pad portions AP can be substantially the same as each other.

[0129] In an embodiment, the third panel test pad portion AP3 and the fourth panel test pad portion AP4 can be disposed between the first panel test pad portion AP1 and the second panel test pad portion AP2. For example, the third panel test pad portion AP3 can be adjacent to the first panel test pad portion AP1. For example, the third panel test pad portion AP3 can be located between the first panel test pad portion AP1 and the fourth panel test pad portion AP4. For example, the fourth panel test pad portion AP4 can be adjacent to the second panel test pad portion AP2. For example, the fourth panel test pad portion AP4 can be located between the second panel test pad portion AP2 and the third panel test pad portion AP3.

[0130] ​​Each of the first panel test pad portion to the fourth panel test pad portion AP1, AP2, AP3, and AP4 can include a first panel pad group ALG and a second panel pad group ARG. In an embodiment, the first panel pad group ALG and the second panel pad group ARG can each include a first panel pad A1, a second panel pad A2, and a third panel pad A3. The first panel pad A1, the second panel pad A2, and the third panel pad A3 can be connected (e.g., electrically connected) to each other.

[0131] The printed circuit board 30 can include a plurality of PCB test pad portions BP and test terminals TP. For example, the printed circuit board 30 can include a first PCB test pad portion BP1, a second PCB test pad portion BP2, a third PCB test pad portion BP3, and a fourth PCB test pad portion BP4. Although FIG. 8 Four PCB test pad portions BP are illustrated, but the present disclosure is not limited thereto. For example, three or more PCB test pad portions BP can be provided. In an embodiment, the structures of the PCB test pad portions BP can be substantially identical to each other.

[0132] Each of the first PCB test pad portion to the fourth PCB test pad portion BP1, BP2, BP3, and BP4 can include a first PCB pad group BLG and a second PCB pad group BRG. In an embodiment, the first PCB pad group BLG and the second PCB pad group BRG can each include a first PCB pad B1, a second PCB pad B2, a third PCB pad B3, and a fourth PCB pad B4.

[0133] In an embodiment, the third PCB test pad portion BP3 and the fourth PCB test pad portion BP4 can be disposed between the first PCB test pad portion BP1 and the second PCB test pad portion BP2. For example, the third PCB test pad portion BP3 can be adjacent to the first PCB test pad portion BP1. For example, the third PCB test pad portion BP3 can be located between the first PCB test pad portion BP1 and the fourth PCB test pad portion BP4. For example, the fourth PCB test pad portion BP4 can be adjacent to the second PCB test pad portion BP2. For example, the fourth PCB test pad portion BP4 can be located between the second PCB test pad portion BP2 and the third PCB test pad portion BP3.

[0134] The test terminal TP can include a first input terminal IT, a second input terminal OT, and a plurality of measurement terminal portions electrically connected to the plurality of PCB test pad portions BP, respectively. For example, the test terminal TP can include a first measurement terminal portion MTP1 electrically connected to the first PCB test pad portion BP1, a second measurement terminal portion MTP2 electrically connected to the second PCB test pad portion BP2, a third measurement terminal portion MTP3 electrically connected to the third PCB test pad portion BP3, and a fourth measurement terminal portion MTP4 electrically connected to the fourth PCB test pad portion BP4.

[0135] The first input terminal IT can be electrically connected to the first PCB pad B1 of the first PCB pad group BLG of the first PCB test pad portion BP1. In an embodiment, the first input terminal IT can be electrically connected to the first PCB pad B1 of the first PCB pad group BLG of the first PCB test pad portion BP1 through the first PCB wiring PWL1.

[0136] The second input terminal OT can be electrically connected to the first PCB pad B1 of the second PCB pad group BRG of the second PCB test pad portion BP2. In an embodiment, the second input terminal OT can be electrically connected to the first PCB pad B1 of the second PCB pad group BRG of the second PCB test pad portion BP2 through the second PCB wiring PWL2.

[0137] Each of the first to fourth measurement terminal portions MTP1, MTP2, MTP3, and MTP4 can include a first measurement terminal group MLG and a second measurement terminal group MRG. The first and second measurement terminal groups MLG and MRG can be mirror-symmetrical to each other with respect to a vertical axis (e.g., a y-axis) between the first and second measurement terminal groups MLG and MRG.

[0138] The first measurement terminal group MLG of each of the first to fourth measurement terminal portions MTP1, MTP2, MTP3, and MTP4 can be electrically connected to the first PCB pad group BLG of the corresponding PCB test pad portion BP. For example, the first measurement terminal group MLG of the first measurement terminal portion MTP1 can be electrically connected to the first PCB pad group BLG of the first PCB test pad portion BP1, the first measurement terminal group MLG of the second measurement terminal portion MTP2 can be electrically connected to the first PCB pad group BLG of the second PCB test pad portion BP2, the first measurement terminal group MLG of the third measurement terminal portion MTP3 can be electrically connected to the first PCB pad group BLG of the third PCB test pad portion BP3, and the first measurement terminal group MLG of the fourth measurement terminal portion MTP4 can be electrically connected to the first PCB pad group BLG of the fourth PCB test pad portion BP4.

[0139] The second measurement terminal group MRG of each of the first to fourth measurement terminal portions MTP1, MTP2, MTP3, and MTP4 can be electrically connected to the second PCB pad group BRG of the corresponding PCB test pad portion BP. For example, the second measurement terminal group MRG of the first measurement terminal portion MTP1 can be electrically connected to the second PCB pad group BRG of the first PCB test pad portion BP1, the second measurement terminal group MRG of the second measurement terminal portion MTP2 can be electrically connected to the second PCB pad group BRG of the second PCB test pad portion BP2, the second measurement terminal group MRG of the third measurement terminal portion MTP3 can be electrically connected to the second PCB pad group BRG of the third PCB test pad portion BP3, and the second measurement terminal group MRG of the fourth measurement terminal portion MTP4 can be electrically connected to the second PCB pad group BRG of the fourth PCB test pad portion BP4.

[0140] Each of the first and second measurement terminal groups MLG and MRG can include a first measurement terminal MT1, a second measurement terminal MT2, and a third measurement terminal MT3. The first measurement terminal group MLG can include the first measurement terminal MT1 electrically connected to the second PCB pad B2 of the first PCB pad group BLG, the second measurement terminal MT2 electrically connected to the third PCB pad B3 of the first PCB pad group BLG, and the third measurement terminal MT3 electrically connected to the fourth PCB pad B4 of the first PCB pad group BLG. The second measurement terminal group MRG can include the first measurement terminal MT1 electrically connected to the second PCB pad B2 of the second PCB pad group BRG, the second measurement terminal MT2 electrically connected to the third PCB pad B3 of the second PCB pad group BRG, and the third measurement terminal MT3 electrically connected to the fourth PCB pad B4 of the second PCB pad group BRG.

[0141] In an embodiment, a plurality of flexible circuit boards 20 can be provided. Each of the plurality of flexible circuit boards 20 can correspond to a corresponding one of the plurality of panel test pad portions AP and to a corresponding one of the plurality of PCB test pad portions BP. For example, the flexible circuit boards 20 can include a first flexible circuit board 20a, a second flexible circuit board 20b, a third flexible circuit board 20c, and a fourth flexible circuit board 20d. In an embodiment, the structures of the flexible circuit boards 20 can be identical to each other.

[0142] One end of the first flexible circuit board 20a can be connected to the first panel test pad portion API, and the other end can be connected to the first PCB test pad portion BP1. One end of the second flexible circuit board 20b can be connected to the second panel test pad portion AP2, and the other end can be connected to the second PCB test pad portion BP2. One end of the third flexible circuit board 20c can be connected to the third panel test pad portion AP3, and the other end can be connected to the third PCB test pad portion BP3. One end of the fourth flexible circuit board 20d can be connected to the fourth panel test pad portion AP4, and the other end can be connected to the fourth PCB test pad portion BP4. Although FIG. 8 Four flexible circuit boards 20 are illustrated, but the present disclosure is not limited thereto. For example, three or more flexible circuit boards 20 can be provided.

[0143] Each of the plurality of flexible circuit boards 20 can include a first transfer pad portion FAP disposed at one end thereof and a second transfer pad portion FBP disposed at the opposite end thereof. That is, the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can include first transfer pad portions FAP1, FAP2, FAP3, and FAP4 disposed at one end thereof and second transfer pad portions FBP1, FBP2, FBP3, and FBP4 disposed at the opposite end thereof, respectively.

[0144] Each of the first transfer pad portions FAP1, FAP2, FAP3, and FAP4 can include a first-1 transfer pad group FALG and a first-2 transfer pad group FARG. The first-1 transfer pad group FALG and the first-2 transfer pad group FARG can each include a first-1 transfer pad FA1, a first-2 transfer pad FA2, and a first-3 transfer pad FA3.

[0145] Each of the second transfer pad portions FBP1, FBP2, FBP3, and FBP4 can include a second-1 transfer pad group FBLG and a second-2 transfer pad group FBRG. In an embodiment, the second-1 transfer pad group FBLG and the second-2 transfer pad group FBRG can each include a second-1 transfer pad FB1, a second-2 transfer pad FB2, a second-3 transfer pad FB3, and a second-4 transfer pad FB4.

[0146] The first transfer pad portions FAP of the plurality of flexible circuit boards 20 can be electrically connected to panel test pad portions AP of the corresponding display panels 10, respectively. For example, the first transfer pad portion FAP1 of the first flexible circuit board 20a can be electrically connected to the first panel test pad portion API. For example, the first transfer pad portion FAP2 of the second flexible circuit board 20b can be electrically connected to the second panel test pad portion AP2. For example, the first transfer pad portion FAP3 of the third flexible circuit board 20c can be electrically connected to the third panel test pad portion AP3. For example, the first transfer pad portion FAP4 of the fourth flexible circuit board 20d can be electrically connected to the fourth panel test pad portion AP4.

[0147] The second transfer pad portions FBP of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can be electrically connected to PCB test pad portions BP of the printed circuit board 30, respectively. For example, the second transfer pad portion FBP1 of the first flexible circuit board 20a can be electrically connected to the first PCB test pad portion BP1. For example, the second transfer pad portion FBP2 of the second flexible circuit board 20b can be electrically connected to the second PCB test pad portion BP2. For example, the second transfer pad portion FBP3 of the third flexible circuit board 20c can be electrically connected to the third PCB test pad portion BP3. For example, the second transfer pad portion FBP4 of the fourth flexible circuit board 20d can be electrically connected to the fourth PCB test pad portion BP4.

[0148] Each of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can include a first wiring FWL1, a second wiring FWL21, a third wiring FWL3, and a sub-wiring FWL22. For convenience of description, since the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d have the same configuration and the connection relationship of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d is substantially the same, the following description will be made with reference to the first flexible circuit board 20a. FIG. 9 The first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can be electrically connected to the display panels 10 and the printed circuit board 30, respectively. For example, the first flexible circuit board 20a can be electrically connected to the first display panel 10a and the printed circuit board 30. For example, the second flexible circuit board 20b can be electrically connected to the second display panel 10b and the printed circuit board 30. For example, the third flexible circuit board 20c can be electrically connected to the third display panel 10c and the printed circuit board 30. For example, the fourth flexible circuit board 20d can be electrically connected to the fourth display panel 10d and the printed circuit board 30.

[0149] The 2-1 transfer pad FB1 can be electrically connected to the 1-1 transfer pad FA1 through a first wiring FWL1. The 2-2 transfer pad FB2 can be electrically connected to the 1-2 transfer pad FA2 through a second wiring FWL21. The 2-3 transfer pad FB3 can be electrically connected to the 1-2 transfer pad FA2 through a sub-wiring FWL22 connected to the second wiring FWL21. In an embodiment, the 2-3 transfer pad FB3 can be electrically connected to the 1-2 transfer pad FA2 through the sub-wiring FWL22 and the second wiring FWL21. The 2-4 transfer pad FB4 can be electrically connected to the 1-3 transfer pad FA3 through a third wiring FWL3. The first wiring FWL1, the second wiring FWL21, the sub-wiring FWL22, and the third wiring FWL3 can be provided on the first flexible circuit board 20a. Each of the first wiring FWL1, the second wiring FWL21, the third wiring FWL3, and the sub-wiring FWL22 can include a conductive material having low resistance. For example, each of the first wiring FWL1, the second wiring FWL21, the third wiring FWL3, and the sub-wiring FWL22 can include a conductive material including Cu.

[0150] As shown in FIG. 1A, the transfer pads of the first transfer pad portion FAP can be electrically connected to the panel pads of the panel test pad portion AP through anisotropic conductive film ACF. Likewise, the transfer pads of the second transfer pad portion FBP can be electrically connected to the PCB pads of the PCB test pad portion BP through anisotropic conductive film ACF. FIG. 11

[0151] In an embodiment, the electrical connection relationship between the pads of the panel test pad portion AP, the first transfer pad portion FAP, the second transfer pad portion FBP, and the PCB test pad portion BP corresponding to each other can be the same as the electrical connection relationship described in the embodiments with reference to FIGS. 1A and 1B. FIG. 2 FIG. 3

[0152] The first transfer pad portions FAP1, FAP2, FAP3, and FAP4 of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can respectively overlap the panel test pad portions AP of the corresponding display panels 10. For example, the first transfer pad portion FAP1 of the first flexible circuit board 20a can overlap the first panel test pad portion AP1. For example, the first transfer pad portion FAP2 of the second flexible circuit board 20b can overlap the second panel test pad portion AP2. For example, the first transfer pad portion FAP3 of the third flexible circuit board 20c can overlap the third panel test pad portion AP3. For example, the first transfer pad portion FAP4 of the fourth flexible circuit board 20d can overlap the fourth panel test pad portion AP4.

[0153] ​​​The second transmission pad portions FBP1, FBP2, FBP3, and FBP4 of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can respectively overlap with the PCB test pad portions BP. For example, the second transmission pad portion FBP1 of the first flexible circuit board 20a can overlap with the first PCB test pad portion BP1. For example, the second transmission pad portion FBP2 of the second flexible circuit board 20b can overlap with the second PCB test pad portion BP2. For example, the second transmission pad portion FBP3 of the third flexible circuit board 20c can overlap with the third PCB test pad portion BP3. For example, the second transmission pad portion FBP4 of the fourth flexible circuit board 20d can overlap with the fourth PCB test pad portion BP4.

[0154] In an embodiment, the third flexible circuit board 20c and the fourth flexible circuit board 20d can be disposed between the first flexible circuit board 20a and the second flexible circuit board 20b. For example, the third flexible circuit board 20c can be adjacent to the first flexible circuit board 20a. For example, the third flexible circuit board 20c can be between the first flexible circuit board 20a and the fourth flexible circuit board 20d. For example, the fourth flexible circuit board 20d can be adjacent to the second flexible circuit board 20b. For example, the fourth flexible circuit board 20d can be between the second flexible circuit board 20b and the third flexible circuit board 20c.

[0155] In an embodiment, the display device 1 can include a plurality of integrated circuit chips 40. For example, the display device 1 can include a first integrated circuit chip 40a, a second integrated circuit chip 40b, a third integrated circuit chip 40c, and a fourth integrated circuit chip 40d. Although FIG. 8 Four integrated circuit chips 40 are illustrated, but the present disclosure is not limited thereto. In an embodiment, the integrated circuit chips 40 can be at respective positions corresponding to the flexible circuit boards 20. In an embodiment, each of the integrated circuit chips 40 can have substantially the same structure as that of each of the other integrated circuit chips 40.

[0156] In each of the PCB test pad portions BP, the second PCB pads B2 of the first PCB pad group BLG can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG. For example, the second PCB pads B2 of the first PCB pad group BLG of the first PCB test pad portion BP1 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the first PCB test pad portion BP1. In an embodiment, the second PCB pads B2 of the first PCB pad group BLG of the first PCB test pad portion BP1 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the first PCB test pad portion BP1 by the 3-1 PCB wiring PWL3a. Likewise, the second PCB pads B2 of the first PCB pad group BLG of the second PCB test pad portion BP2 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the second PCB test pad portion BP2 by the 3-2 PCB wiring PWL3b. Likewise, the second PCB pads B2 of the first PCB pad group BLG of the third PCB test pad portion BP3 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the third PCB test pad portion BP3 by the 3-3 PCB wiring PWL3c. Likewise, the second PCB pads B2 of the first PCB pad group BLG of the fourth PCB test pad portion BP4 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the fourth PCB test pad portion BP4 by the 3-4 PCB wiring PWL3d.

[0157] The first PCB pads B1 of the second PCB pad group BRG of any one of the PCB test pad portions BP can be electrically connected to the first PCB pads B1 of the first PCB pad group BLG of another PCB test pad portion BP adjacent to the one of the PCB test pad portions BP. For example, the first PCB pads B1 of the second PCB pad group BRG of the first PCB test pad portion BP1 can be electrically connected to the first PCB pads B1 of the first PCB pad group BLG of the third PCB test pad portion BP3 by the 4-1 PCB wiring PWL4a. Likewise, the first PCB pads B1 of the second PCB pad group BRG of the third PCB test pad portion BP3 can be electrically connected to the first PCB pads B1 of the first PCB pad group BLG of the fourth PCB test pad portion BP4 by the 4-2 PCB wiring PWL4b. Likewise, the first PCB pads B1 of the second PCB pad group BRG of the fourth PCB test pad portion BP4 can be electrically connected to the first PCB pads B1 of the first PCB pad group BLG of the second PCB test pad portion BP2 by the 4-3 PCB wiring PWL4c.

[0158] FIG. 11 is a perspective view illustrating a structure in a current path used during connection resistance measurement according to an embodiment of the present disclosure. FIG. 8 to FIG. 10 is a perspective view illustrating a structure in a current path used during connection resistance measurement according to an embodiment of the present disclosure.

[0159] Referring to FIG. 8 to FIG. 11 When a test current is applied to the first input terminal IT, a current path can be formed between the first input terminal IT and the second input terminal OT. When the test current is applied to the first input terminal IT, the test current can flow through the current path including the first PCB pad B1 of the first PCB pad group BLG of the first PCB test pad portion BP1, the first panel pad A1 of the first panel pad group ALG of the first panel test pad portion AP1, the second panel pad A2 of the first panel pad group ALG of the first panel test pad portion AP1, and the second PCB pad B2 of the first PCB pad group BLG of the first PCB test pad portion BP1.

[0160] The second PCB pad B2 of the first PCB pad group BLG of the first PCB test pad portion BP1 can be electrically connected to the second PCB pad B2 of the second PCB pad group BRG of the first PCB test pad portion BP1, such that the current path can further include the second PCB pad B2 of the second PCB pad group BRG of the first PCB test pad portion BP1, the second panel pad A2 of the second panel pad group ARG of the first panel test pad portion AP1, the first panel pad A1 of the second panel pad group ARG of the first panel test pad portion AP1, and the first PCB pad B1 of the second PCB pad group BRG of the first PCB test pad portion BP1.

[0161] In addition, the first PCB pad B1 of the first PCB pad group BLG of a third PCB test pad portion BP3 adjacent to the first PCB test pad portion BP1 can be electrically connected to the first PCB pad B1 of the second PCB pad group BRG of the first PCB test pad portion BP1, such that the current path can further include the first PCB pad B1 of the first PCB pad group BLG of the third PCB test pad portion BP3, the first panel pad A1 of the first panel pad group ALG of the third panel test pad portion AP3, the second panel pad A2 of the first panel pad group ALG of the third panel test pad portion AP3, and the second PCB pad B2 of the first PCB pad group BLG of the third PCB test pad portion BP3.

[0162] Furthermore, the second PCB pads B2 of the first PCB pad group BLG of the third PCB test pad portion BP3 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the third PCB test pad portion BP3, such that the current path can further comprise the second PCB pads B2 of the second PCB pad group BRG of the third PCB test pad portion BP3, the second panel pads A2 of the second panel pad group ARG of the third panel test pad portion AP3, the first panel pads Al of the second panel pad group ARG of the third panel test pad portion AP3, and the first PCB pads Bl of the second PCB pad group BRG of the third PCB test pad portion BP3.

[0163] Furthermore, the first PCB pads Bl of the first PCB pad group BLG of the fourth PCB test pad portion BP4 adjacent to the third PCB test pad portion BP3 can be electrically connected to the first PCB pads Bl of the second PCB pad group BRG of the third PCB test pad portion BP3, such that the current path can further comprise the first PCB pads Bl of the first PCB pad group BLG of the fourth PCB test pad portion BP4, the first panel pads Al of the first panel pad group ALG of the fourth panel test pad portion AP4, the second panel pads A2 of the first panel pad group ALG of the fourth panel test pad portion AP4, and the second PCB pads B2 of the first PCB pad group BLG of the fourth PCB test pad portion BP4.

[0164] Furthermore, the second PCB pads B2 of the first PCB pad group BLG of the fourth PCB test pad portion BP4 can be electrically connected to the second PCB pads B2 of the second PCB pad group BRG of the fourth PCB test pad portion BP4, such that the current path can further comprise the second PCB pads B2 of the second PCB pad group BRG of the fourth PCB test pad portion BP4, the second panel pads A2 of the second panel pad group ARG of the fourth panel test pad portion AP4, the first panel pads Al of the second panel pad group ARG of the fourth panel test pad portion AP4, and the first PCB pads Bl of the second PCB pad group BRG of the fourth PCB test pad portion BP4.

[0165] Furthermore, the first PCB pad B1 of the first PCB pad group BLG of the second PCB test pad portion BP2, which is adjacent to the fourth PCB test pad portion BP4, can be electrically connected to the first PCB pad B1 of the second PCB pad group BRG of the fourth PCB test pad portion BP4, such that the current path can also include the first PCB pad B1 of the first PCB pad group BLG of the second PCB test pad portion BP2, the first panel pad A1 of the first panel pad group ALG of the second panel test pad portion AP2, the second panel pad A2 of the first panel pad group ALG of the second panel test pad portion AP2, and the second PCB pad B2 of the first PCB pad group BLG of the second PCB test pad portion BP2.

[0166] Furthermore, the second PCB pad B2 of the first PCB pad group BLG of the second PCB test pad portion BP2 can be electrically connected to the second PCB pad B2 of the second PCB pad group BRG of the second PCB test pad portion BP2, such that the current path can also include the second PCB pad B2 of the second PCB pad group BRG of the second PCB test pad portion BP2, the second panel pad A2 of the second panel pad group ARG of the second panel test pad portion AP2, the first panel pad A1 of the second panel pad group ARG of the second panel test pad portion AP2, and the first PCB pad B1 of the second PCB pad group BRG of the second PCB test pad portion BP2.

[0167] That is, the first PCB test pad section BP1 and the second PCB test pad section BP2 located at opposite ends can be electrically connected to each other. For example, the first PCB pad B1 of the first PCB pad group BLG of the second PCB test pad section BP2 can be electrically connected to the first PCB pad B1 of the second PCB pad group BRG of the first PCB test pad section BP1. For example, the second input terminal OT connected to the first PCB pad B1 of the second PCB pad group BRG of the second PCB test pad section BP2 can be electrically connected to the second PCB pad B2 of the first PCB pad group BLG of the first PCB test pad section BP1. Therefore, multiple PCB test pad sections BP can use a common current source.

[0168] In the embodiments, as referenced FIG. 2 to FIG. 4 The current source described herein, used to measure the connection resistance (hereinafter referred to as the first connection resistance) between the panel test pad portion AP and the first transmission pad portion FAP, and the current source used to measure the connection resistance (hereinafter referred to as the second connection resistance) between the PCB test pad portion BP and the second transmission pad portion FBP, can be connected to each other in a common current structure.

[0169] In an embodiment, the second connection resistance between the second transmission pad portion FBP of each of the first to fourth flexible circuit boards 20a, 20b, 20c and 20d and the PCB test pad portion BP of the printed circuit board 30 can be measured by electrically connecting a current source to allow a current from a first input terminal IT connected to a first PCB pad Bl of a first PCB pad group BLG of the first PCB test pad portion BP1 to a second input terminal OT connected to a first PCB pad Bl of a second PCB pad group BRG of the second PCB test pad portion BP2 and by connecting a voltmeter to each of a first measurement terminal MT1 connected to a second PCB pad B2 and a second measurement terminal MT2 connected to a third PCB pad B3 of each of the first to fourth PCB test pad portions BP1, BP2, BP3 and BP4.

[0170] In an embodiment, the first connection resistance between the first transmission pad portion FAP of each of the first to fourth flexible circuit boards 20a, 20b, 20c and 20d and the panel test pad portion AP of the display panel 10 can be measured by electrically connecting a current source to allow a current from a first input terminal IT connected to a first PCB pad Bl of a first PCB pad group BLG of the first PCB test pad portion BP1 to a second input terminal OT connected to a first PCB pad Bl of a second PCB pad group BRG of the second PCB test pad portion BP2 and by connecting a voltmeter to each of a second measurement terminal MT2 connected to a third PCB pad B3 and a third measurement terminal MT3 connected to a fourth PCB pad B4 of each of the first to fourth PCB test pad portions BP1, BP2, BP3 and BP4.

[0171] In this embodiment, as described above, the current source for measuring the first connection resistance between the panel test pad portion AP and the first transfer pad portion FAP, and the current source for measuring the second connection resistance between the PCB test pad portion BP and the second transfer pad portion FBP, can be connected to each other in a common current structure. Furthermore, the second measurement terminal MT2 can be used for both the measurement of the first and second connection resistances, thus reducing the number of test terminals TP and the number of transfer pads arranged in the flexible circuit board 20. Additionally, since current sources for measuring the connection resistance of multiple flexible circuit boards 20 are commonly used, the number of test terminals TP and the number of transfer pads arranged in each second transfer pad portion FBP can be reduced.

[0172] In the case of the display device 1 according to the embodiment, the number of test terminals TP used to measure both the first connection resistance between the panel test pad portion AP and the first transfer pad portion FAP, and the second connection resistance between the PCB test pad portion BP and the second transfer pad portion FBP, can be 6n+2 (where n is the number of flexible circuit boards 20). For example, as FIG. 8 As shown in the embodiment where the number of flexible circuit boards 20 is four, the test terminals TP may include a first input terminal IT, a second input terminal OT, and first to fourth measurement terminal portions MTP1, MTP2, MTP3, and MPT4, each comprising six measurement terminals, and thus may include a total of 26 test terminals. In the case of including... FIG. 1B In the typical 4-terminal measurement case of the display device 1 with multiple flexible circuit boards 20 shown, 12n or more test terminals (where n is the number of flexible circuit boards 20) are required to measure the first connection resistance and the second connection resistance of each flexible circuit board 20. However, in the display device 1 according to this embodiment, by reducing the number of test terminals TP used to measure both the first connection resistance and the second connection resistance of each of the multiple flexible circuit boards 20 to 6n+2, and thereby reducing the space occupied by the test terminals TP on the printed circuit board 30, the limitations on the design and arrangement of the test pads can be significantly reduced, and the printed circuit board 30 can be miniaturized.

[0173] FIG. 12 According to the embodiments FIG. 1B A magnified view of region "B". FIG. 13 Is with FIG. 12 An enlarged view of an embodiment of the region corresponding to the first flexible circuit board 20a and the second flexible circuit board 20b. FIG. 14 It does not include the first flexible circuit board 20a and the second flexible circuit board 20b, nor the first integrated circuit chip 40a and the second integrated circuit chip 40b. FIG. 13FIG. 6 is a magnified view of the portion of FIG. 5.

[0174] FIG. 12 to FIG. 14 The embodiments illustrated in FIGS. 1 through 6 include components having the same or similar designations, references, or descriptions and have been described above with regard thereto. FIG. 2 to FIG. 10 The embodiments illustrated in FIGS. 1 through 6 include components having the same or similar designations, references, or descriptions and have been described above with regard thereto. FIG. 2 to FIG. 10 The embodiments illustrated in FIGS. 1 through 6 include components having the same or similar designations, references, or descriptions and have been described above with regard thereto. FIG. 12 to FIG. 14 The embodiments illustrated in FIGS. 1 through 6 include components having the same or similar designations, references, or descriptions and have been described above with regard thereto.

[0175] Referring to FIGS. 1 through 6, FIG. 12 to FIG. 14 The first through fourth integrated circuit chips 40a, 40b, 40c, and 40d can each further include an IC test pad portion ICP. The display panel 10 can further include IC transmission pad portions CP electrically connected to the IC test pad portions ICP of the first through fourth integrated circuit chips 40a, 40b, 40c, and 40d, respectively. The IC transmission pad portions CP of the display panel 10 can overlap the IC test pad portions ICP of the integrated circuit chips 40, respectively.

[0176] The IC test pad portion ICP of each of the first through fourth integrated circuit chips 40a, 40b, 40c, and 40d can include a first IC test pad group ICLG and a second IC test pad group ICRG each including a plurality of IC test pads. In an embodiment, the first IC test pad group ICLG and the second IC test pad group ICRG can each include a first IC test pad IC1, a second IC test pad IC2, and a third IC test pad IC3. The first IC test pad IC1, the second IC test pad IC2, and the third IC test pad IC3 can be connected (e.g., electrically connected) to each other.

[0177] Each of the IC transmission pad portions CP corresponding to the first through fourth integrated circuit chips 40a, 40b, 40c, and 40d, respectively, can include a first IC transmission pad group CLG and a second IC transmission pad group CRG. In an embodiment, the first IC transmission pad group CLG and the second IC transmission pad group CRG can each include a first IC transmission pad C1, a second IC transmission pad C2, and a third IC transmission pad C3. The first IC transmission pad C1 can overlap the first IC test pad IC1, the second IC transmission pad C2 can overlap the second IC test pad IC2, and the third IC transmission pad C3 can overlap the third IC test pad IC3.

[0178] The display panel 10 may include multiple panel test pad portions APa. For example, the display panel 10 may include a first panel test pad portion AP1a, a second panel test pad portion AP2a, a third panel test pad portion AP3a, and a fourth panel test pad portion AP4a. Each of the first to fourth panel test pad portions AP1a, AP2a, AP3a, and AP4a may include a first panel pad group ALGa and a second panel pad group ARGa. In an embodiment, the first panel pad group ALGa and the second panel pad group ARGa may each include a first panel pad A1a, a second panel pad A2a, a third panel pad A3a, a fourth panel pad A4a, and a fifth panel pad A5a.

[0179] The first panel test pad portion to the fourth panel test pad portion AP1a, AP2a, AP3a and AP4a, which correspond to the first to fourth flexible circuit boards 20a, 20b, 20c and 20d respectively, and the IC test pad portion ICP have essentially the same structure. Therefore, for ease of description, the following description focuses on the components and connection relationships of the first panel test pad portion AP1a and the IC test pad portion ICP corresponding to the first flexible circuit board 20a.

[0180] like FIG. 14 As shown, the first panel pad A1a can be electrically connected to the first IC transmission pad C1 via the first panel wiring WL1. The second panel pad A2a can be electrically connected to the second IC transmission pad C2 via the second panel wiring WL2. The third panel pad A3a can be electrically connected to the second panel pad A2a via the third panel wiring WL3. In an embodiment, the third panel wiring WL3 can connect the second panel pad A2a and the third panel pad A3a to each other. In an embodiment, the third panel pad A3a can be electrically connected to the second panel pad A2a via the third panel wiring WL3 and the second panel pad A2a via the second panel pad C2. The fourth panel pad A4a can be electrically connected to the second IC transmission pad C2 via the fourth panel wiring WL4. The fifth panel pad A5a can be electrically connected to the third IC transmission pad C3 via the fifth panel wiring WL5. The first panel wiring WL1, the second panel wiring WL2, the third panel wiring WL3, the fourth panel wiring WL4, and the fifth panel wiring WL5 can be disposed in or on the display panel 10.

[0181] The printed circuit board 30 can include a plurality of PCB test pad portions BPa and test terminals TPa. For example, the printed circuit board 30 can include a first PCB test pad portion BP1a, a second PCB test pad portion BP2a, a third PCB test pad portion BP3a, and a fourth PCB test pad portion BP4a. The PCB test pad portions BPa can include a first PCB pad group BLa and a second PCB pad group BRGa each including a plurality of PCB pads. In an embodiment, the first PCB pad group BLa and the second PCB pad group BRGa can each include a first PCB pad B1a, a second PCB pad B2a, a third PCB pad B3a, a fourth PCB pad B4a, a fifth PCB pad B5a, and a sixth PCB pad B6a.

[0182] The test terminals TPa can include a first input terminal ITa, a second input terminal OTa, and a plurality of measurement terminal portions respectively electrically connected to the plurality of PCB test pad portions BPa. For example, the test terminals TPa can include a first measurement terminal portion MTP1a electrically connected to the first PCB test pad portion BP1a, a second measurement terminal portion MTP2a electrically connected to the second PCB test pad portion BP2a, a third measurement terminal portion MTP3a electrically connected to the third PCB test pad portion BP3a, and a fourth measurement terminal portion MTP4a electrically connected to the fourth PCB test pad portion BP4a. Each of the first to fourth measurement terminal portions MTP1a, MTP2a, MTP3a, and MTP4a can include a first measurement terminal group MLGa and a second measurement terminal group MRGa.

[0183] The first input terminal ITa can be electrically connected to the first PCB pad B1a of the first PCB pad group BLa of the first PCB test pad portion BP1a. In an embodiment, the first input terminal ITa can be electrically connected to the first PCB pad B1a of the first PCB pad group BLa of the first PCB test pad portion BP1a through a first PCB wiring PWL1a.

[0184] The second input terminal OTa can be electrically connected to the first PCB pad B1a of the second PCB pad group BRGa of the second PCB test pad portion BP2a. In an embodiment, the second input terminal OTa can be electrically connected to the first PCB pad B1a of the second PCB pad group BRGa of the second PCB test pad portion BP2a through a second PCB wiring PWL2a.

[0185] A first measurement terminal group MLGa of each of the first to fourth measurement terminal portions MTP1a, MTP2a, MTP3a, and MTP4a can be electrically connected to a first PCB pad group BLa of the corresponding PCB test pad portion BPa. A second measurement terminal group MRGa of each of the first to fourth measurement terminal portions MTP1a, MTP2a, MTP3a, and MTP4a can be electrically connected to a second PCB pad group BRGa of the corresponding PCB test pad portion BPa.

[0186] The first and second measurement terminal groups MLGa and MRGa can each include a first measurement terminal MT1a, a second measurement terminal MT2a, a third measurement terminal MT3a, a fourth measurement terminal MT4a, and a fifth measurement terminal MT5a. The first measurement terminal group MLGa can include the first measurement terminal MT1a electrically connected to the second PCB pad B2a of the first PCB pad group BLa, the second measurement terminal MT2a electrically connected to the third PCB pad B3a of the first PCB pad group BLa, the third measurement terminal MT3a electrically connected to the fourth PCB pad B4a of the first PCB pad group BLa, the fourth measurement terminal MT4a electrically connected to the fifth PCB pad B5a of the first PCB pad group BLa, and the fifth measurement terminal MT5a electrically connected to the sixth PCB pad B6a of the first PCB pad group BLa. The second measurement terminal group MRGa can include the first measurement terminal MT1a electrically connected to the second PCB pad B2a of the second PCB pad group BRGa, the second measurement terminal MT2a electrically connected to the third PCB pad B3a of the second PCB pad group BRGa, the third measurement terminal MT3a electrically connected to the fourth PCB pad B4a of the second PCB pad group BRGa, the fourth measurement terminal MT4a electrically connected to the fifth PCB pad B5a of the second PCB pad group BRGa, and the fifth measurement terminal MT5a electrically connected to the sixth PCB pad B6a of the second PCB pad group BRGa.

[0187] Each of the plurality of flexible circuit boards 20 can include a first transmission pad portion FAPa disposed at one end thereof and a second transmission pad portion FBPa disposed at the other end thereof. That is, the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can include the first transmission pad portions FAP1a, FAP2a, FAP3a, and FAP4a disposed at one end thereof and the second transmission pad portions FBP1a, FBP2a, FBP3a, and FBP4a disposed at the other end thereof, respectively.

[0188] Each of the first transmission pad portions FAP1a, FAP2a, FAP3a, and FAP4a can include a 1-1 transmission pad group FALGa and a 1-2 transmission pad group FARGa. The 1-1 transmission pad group FALGa and the 1-2 transmission pad group FARGa can each include a 1-1 transmission pad FA1a, a 1-2 transmission pad FA2a, a 1-3 transmission pad FA3a, a 1-4 transmission pad FA4a, and a 1-5 transmission pad FA5a.

[0189] Each of the second transmission pad portions FBP1a, FBP2a, FBP3a, and FBP4a can include a 2-1 transmission pad group FBLGa and a 2-2 transmission pad group FBRGa. In an embodiment, the 2-1 transmission pad group FBLGa and the 2-2 transmission pad group FBRGa can each include a 2-1 transmission pad FB1a, a 2-2 transmission pad FB2a, a 2-3 transmission pad FB3a, a 2-4 transmission pad FB4a, a 2-5 transmission pad FB5a, and a 2-6 transmission pad FB6a.

[0190] The first transmission pad portions FAPa of the plurality of flexible circuit boards 20 can be electrically connected to corresponding panel test pad portions APa of the display panel 10, respectively. The second transmission pad portions FBPa of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can be electrically connected to corresponding PCB test pad portions BPa of the printed circuit board 30, respectively.

[0191] The first to fourth flexible circuit boards 20a, 20b, 20c, and 20d can each include a first wiring FWL1a, a second wiring FWL21a, a third wiring FWL3a, a fourth wiring FWL4a, a fifth wiring FWL5a, and a sub-wiring FWL22a. Since the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d include the same configuration, and the connection relationship of the first to fourth flexible circuit boards 20a, 20b, 20c, and 20d is substantially the same, for the convenience of description, the following description focuses on the first flexible circuit board 20a as shown in FIG. 2A. FIG. 13

[0192] ​Transmit pad FB1a, number 2-1, can be electrically connected to transmit pad FA1a, number 1-1, via a first wiring FWL1a. Transmit pad FB2a, number 2-2, can be electrically connected to transmit pad FA2a, number 1-2, via a second wiring FWL21a. Transmit pad FB3a, number 2-3, can be electrically connected to transmit pad FA2a, number 1-2, via a sub-wiring FWL22a connected to the second wiring FWL21a. In an embodiment, transmit pad FB3a, number 2-3, can be electrically connected to transmit pad FA2a, number 1-2, via sub-wiring FWL22a and second wiring FWL21a. Transmit pad FB4a, number 2-4, can be electrically connected to transmit pad FA3a, number 1-3, via a third wiring FWL3a. Transmit pad FB5a, number 2-5, can be electrically connected to transmit pad FA4a, number 1-4, via a fourth wiring FWL4a. Transmit pad FB6a, number 2-6, can be electrically connected to transmit pad FA5a, number 1-5, via a fifth wiring FWL5a. The first wiring FWL1a, the second wiring FWL21a, the sub-wiring FWL22a, the third wiring FWL3a, the fourth wiring FWL4a, and the fifth wiring FWL5a can be disposed on the flexible circuit board 20.

[0193] The first wiring FWL1a, the second wiring FWL21a, the third wiring FWL3a, the fourth wiring FWL4a, the fifth wiring FWL5a, and the sub-wiring FWL22a may each comprise a conductive material with low resistance. In an embodiment, the resistance of each of the first wiring FWL1a, the second wiring FWL21a, the third wiring FWL3a, the fourth wiring FWL4a, the fifth wiring FWL5a, and the sub-wiring FWL22a may be less than the resistance of each of the first panel wiring WL1, the second panel wiring WL2, the third panel wiring WL3, the fourth panel wiring WL4, and the fifth panel wiring WL5. For example, the first wiring FWL1a, the second wiring FWL21a, the third wiring FWL3a, the fourth wiring FWL4a, the fifth wiring FWL5a, and the sub-wiring FWL22a may each comprise a conductive material comprising copper (Cu).

[0194] The transfer pads of the first transfer pad section FAPa can be electrically connected to the panel pads of the panel test pad section APa through anisotropic conductive film ACF, such as... FIG. 15 As shown in the diagram. Similarly, the transfer pads of the second transfer pad portion FBPa can be electrically connected to the PCB pads of the PCB test pad portion BPa via anisotropic conductive film ACF. Similarly, the transfer pads of the IC transfer pad portion CP can be electrically connected to the IC test pads of the IC test pad portion ICP via anisotropic conductive film ACF.

[0195] In an embodiment, the electrical connection relationship between the pads of the IC test pad portion ICP, the IC transmission pad portion CP, the panel test pad portion APa, the first transmission pad portion FAPa, the second transmission pad portion FBPa, and the PCB test pad portion BPa corresponding to each other can be the same as the electrical connection relationship described in the embodiments of FIG. 5 and FIG. 6 .

[0196] In an embodiment, similar to the embodiments of FIG. 8 to FIG. 10 , in each of the PCB test pad portions BPa, the second PCB pads B2a of the first PCB pad group BLa can be electrically connected to the second PCB pads B2a of the second PCB pad group BRa.

[0197] In an embodiment, similar to the embodiments of FIG. 8 to FIG. 10 , the first PCB pads B1a of the second PCB pad group BRa of any one of the PCB test pad portions BPa can be electrically connected to the first PCB pads B1a of the first PCB pad group BLa of another PCB test pad portion BPa adjacent to the one of the PCB test pad portions BPa.

[0198] FIG. 15 is a perspective view illustrating a structure in a current path used during connection resistance measurement according to an embodiment of FIG. 12 to FIG. 14 .

[0199] Referring to FIG. 12 to FIG. 15 , when a test current is applied to the first input terminal ITa, a current path can be formed between the first input terminal ITa and the second output terminal OTa.

[0200] In an embodiment, when a test current is applied to the first input terminal ITa, the test current can flow through a current path including the first PCB pads B1a of the first PCB pad group BLa of the first PCB test pad portion BP1a, the first panel pads A1a of the first panel pad group ALGa of the first panel test pad portion AP1a, the first and second IC test pads IC1 and IC2 of the IC test pad portion ICP corresponding to the first panel pad group ALGa of the first panel test pad portion AP1a, the second panel pads A2a of the first panel pad group ALGa of the first panel test pad portion AP1a, and the second PCB pads B2a of the first PCB pad group BLa of the first PCB test pad portion BP1a.

[0201] Furthermore, the second PCB pads B2a of the first PCB pad group BLa of the first PCB test pad portion BP1a can be electrically connected to the second PCB pads B2a of the second PCB pad group BRGa of the first PCB test pad portion BP1a, such that the test current can also flow through a current path comprising the second PCB pads B2a of the second PCB pad group BRGa of the first PCB test pad portion BP1a, the second panel pads A2a of the second panel pad group ARGa of the first panel test pad portion AP1a, the second IC test pad IC2 and the first IC test pad IC1 of the IC test pad portion ICP corresponding to the second panel pad group ARGa of the first panel test pad portion AP1a, the first panel pads A1a of the second panel pad group ARGa of the first panel test pad portion AP1a, and the first PCB pads B1a of the second PCB pad group BRGa of the first PCB test pad portion BP1a.

[0202] Furthermore, the first PCB pads B1a of the first PCB pad group BLa of the third PCB test pad portion BP3a can be electrically connected to the first PCB pads B1a of the second PCB pad group BRGa of the first PCB test pad portion BP1a, such that the test current can also flow through a current path comprising the first PCB pads B1a of the first PCB pad group BLa of the third PCB test pad portion BP3a, the first panel pads A1a of the first panel pad group ALGa of the third panel test pad portion AP3a, the first IC test pad IC1 and the second IC test pad IC2 of the IC test pad portion ICP corresponding to the first panel pad group ALGa of the third panel test pad portion AP3a, the second panel pads A2a of the first panel pad group ALGa of the third panel test pad portion AP3a, and the second PCB pads B2a of the first PCB pad group BLa of the third PCB test pad portion BP3a.

[0203] Further, the second PCB pads B2a of the first PCB pad group B LGa of the third PCB test pad portion BP3a can be electrically connected to the second PCB pads B2a of the second PCB pad group BRGa of the third PCB test pad portion BP3a, such that the test current can also flow through a current path comprising the second PCB pads B2a of the second PCB pad group BRGa of the third PCB test pad portion BP3a, the second panel pads A2a of the second panel pad group ARGa of the third panel test pad portion AP3a, the second IC test pad IC2 and the first IC test pad IC1 of the IC test pad portion ICP corresponding to the second panel pad group ARGa of the third panel test pad portion AP3a, the first panel pad A1a of the second panel pad group ARGa of the third panel test pad portion AP3a, and the first PCB pads B1a of the second PCB pad group BRGa of the third PCB test pad portion BP3a.

[0204] Further, the first PCB pads B1a of the first PCB pad group B LGa of the fourth PCB test pad portion BP4a adjacent to the third PCB test pad portion BP3a can be electrically connected to the first PCB pads B1a of the second PCB pad group BRGa of the third PCB test pad portion BP3a, such that the test current can also flow through a current path comprising the first PCB pads B1a of the first PCB pad group B LGa of the fourth PCB test pad portion BP4a, the first panel pads A1a of the first panel pad group ALGa of the fourth panel test pad portion AP4a, the first IC test pad IC1 and the second IC test pad IC2 of the IC test pad portion ICP corresponding to the first panel pad group ALGa of the fourth panel test pad portion AP4a, the second panel pads A2a of the first panel pad group ALGa of the fourth panel test pad portion AP4a, and the second PCB pads B2a of the first PCB pad group B LGa of the fourth PCB test pad portion BP4a.

[0205] Furthermore, the second PCB pad B2a of the first PCB pad group BLGa of the fourth PCB test pad section BP4a can be electrically connected to the second PCB pad B2a of the second PCB pad group BRGa of the fourth PCB test pad section BP4a, so that the test current can also flow through the current path including the second PCB pad B2a of the second PCB pad group BRGa of the fourth PCB test pad section BP4a, the second panel pad A2a of the second panel pad group ARGa of the fourth panel test pad section AP4a, the second IC test pad IC2 and the first IC test pad IC1 of the IC test pad section ICP corresponding to the second panel pad group ARGa of the fourth panel test pad section AP4a, the first panel pad A1a of the second panel pad group ARGa of the fourth panel test pad section AP4a, and the first PCB pad B1a of the second PCB pad group BRGa of the fourth PCB test pad section BP4a.

[0206] Furthermore, the first PCB pad B1a of the first PCB pad group BLGa of the second PCB test pad portion BP2a, which is adjacent to the fourth PCB test pad portion BP4a, can be electrically connected to the first PCB pad B1a of the second PCB pad group BRGa of the fourth PCB test pad portion BP4a. This allows the test current to flow through the current path including the first PCB pad B1a of the first PCB pad group BLGa of the second PCB test pad portion BP2a, the first panel pad A1a of the first panel pad group ALGa of the second panel test pad portion AP2a, the first IC test pad IC1 and the second IC test pad IC2 of the IC test pad portion ICP corresponding to the first panel pad group ALGa of the second panel test pad portion AP2a, the second panel pad A2a of the first panel pad group ALGa of the second panel test pad portion AP2a, and the second PCB pad B2a of the first PCB pad group BLGa of the second PCB test pad portion BP2a.

[0207] Further, the second PCB pads B2a of the first PCB pad group B LGa of the second PCB test pad portion BP2a can be electrically connected to the second PCB pads B2a of the second PCB pad group B RGa of the second PCB test pad portion BP2a, such that the test current can also flow through the current path comprising the second PCB pads B2a of the second PCB pad group B RGa of the second PCB test pad portion BP2a, the second panel pads A2a of the second panel pad group A RGa of the second panel test pad portion AP2a, the second IC test pad IC2 and the first IC test pad IC1 of the IC test pad portion ICP corresponding to the second panel pad group A RGa of the second panel test pad portion AP2a, the first panel pad A1a of the second panel pad group A RGa of the second panel test pad portion AP2a, and the first PCB pad B1a of the second PCB pad group B RGa of the second PCB test pad portion BP2a.

[0208] That is, the first PCB test pad portion BP1a and the second PCB test pad portion BP2a located at both ends can be electrically connected to each other. For example, the first PCB pad B1a of the first PCB pad group B LGa of the second PCB test pad portion BP2a can be electrically connected to the first PCB pad B1a of the second PCB pad group B RGa of the first PCB test pad portion BP1a. For example, the second input terminal OTa connected to the first PCB pad B1a of the second PCB pad group B RGa of the second PCB test pad portion BP2a can be electrically connected to the second PCB pad B2a of the first PCB pad group B LGa of the first PCB test pad portion BP1a. Accordingly, the plurality of PCB test pad portions BP a can use a common current source.

[0209] In an embodiment, the second connection resistance between the second transfer pad portion FBPa of the flexible circuit board 20 and the PCB test pad portion BPa of the printed circuit board 30 can be measured by electrically connecting a current source to the first input terminal ITa connected with the first PCB pad B1a of the first PCB pad group BLGa of the first PCB test pad portion BP1a and the second input terminal OTa connected with the first PCB pad B1a of the second PCB pad group BRGa of the second PCB test pad portion BP2a to apply a current and by connecting a voltmeter to each of the first measurement terminal MT1a connected with the second PCB pad B2a and the second measurement terminal MT2a connected with the third PCB pad B3a to measure the voltage of the first measurement terminal MT1a and the voltage of the second measurement terminal MT2a, the second PCB pad B2a and the third PCB pad B3a being in the first PCB pad group BLGa and the second PCB pad group BRGa of each of the first to fourth PCB test pad portions BP1a, BP2a, BP3a, and BP4a.

[0210] In an embodiment, the first connection resistance between the first transfer pad portion FAPa of the flexible circuit board 20 and the panel test pad portion APa of the display panel 10 can be measured by electrically connecting a current source to allow a current from the first input terminal ITa connected with the first PCB pad B1a of the first PCB pad group BLGa of the first PCB test pad portion BP1a to the second input terminal OTa connected with the first PCB pad B1a of the second PCB pad group BRGa of the second PCB test pad portion BP2a and by connecting a voltmeter to each of the second measurement terminal MT2a connected with the third PCB pad B3a and the third measurement terminal MT3a connected with the fourth PCB pad B4a to measure the voltage of the second measurement terminal MT2a and the voltage of the third measurement terminal MT3a, the third PCB pad B3a and the fourth PCB pad B4a being in the first PCB pad group BLGa and the second PCB pad group BRGa of each of the first to fourth PCB test pad portions BP1a, BP2a, BP3a, and BP4a.

[0211] In an embodiment, the third connection resistance between the IC test pad portion ICP of the integrated circuit chip 40 and the IC transfer pad portion CP of the display panel 10 can be measured by connecting the current source to allow the current to flow from the first input terminal ITa connected with the first PCB pad B1a of the first PCB pad group BLGa of the first PCB test pad portion BP1a to the second input terminal OTa connected with the first PCB pad B1a of the second PCB pad group BRGa of the second PCB test pad portion BP2a and by connecting the voltmeter to each of the fourth measurement terminal MT4a connected with the fifth PCB pad B5a and the fifth measurement terminal MT5a connected with the sixth PCB pad B6a to measure the voltage of the fourth measurement terminal MT4a and the voltage of the fifth measurement terminal MT5a, the fifth PCB pad B5a and the sixth PCB pad B6a being in the first PCB pad group BLGa and the second PCB pad group BRGa of each of the first to fourth PCB test pad portions BP1a, BP2a, BP3a, and BP4a.

[0212] In an embodiment, the current source for measuring the third connection resistance between the IC transfer pad portion CP and the IC test pad portion ICP, the current source for measuring the first connection resistance between the panel test pad portion APa and the first transfer pad portion FAPa, and the current source for measuring the second connection resistance between the PCB test pad portion BPa and the second transfer pad portion FBPa can be connected to each other in a common current structure, and the second measurement terminal MT2a can be used for both the measurement of the first connection resistance and the measurement of the second connection resistance, and thus, the number of test terminals TPa and the number of transfer pads arranged in the flexible circuit board 20 can be reduced. In addition, since the current sources for measuring the connection resistances of a plurality of flexible circuit boards 20 are commonly used, the number of test terminals TPa and the number of transfer pads arranged in each second transfer pad portion FBPa can be reduced.

[0213] In the case of the display apparatus 1 according to the embodiment, the number of test terminals TPa required to measure the first connection resistance between the panel test pad portion APa and the first transfer pad portion FAPa, the second connection resistance between the PCB test pad portion BPa and the second transfer pad portion FBPa, and the third connection resistance between the IC transfer pad portion CP and the IC test pad portion ICP can be 10n+2 (where n is the number of flexible circuit boards 20). For example, as shown in FIG. 7, in the case of the display apparatus 1 according to the embodiment, the number of test terminals TPa required to measure the first connection resistance between the panel test pad portion APa and the first transfer pad portion FAPa, the second connection resistance between the PCB test pad portion BPa and the second transfer pad portion FBPa, and the third connection resistance between the IC transfer pad portion CP and the IC test pad portion ICP can be 10n+2 (where n is the number of flexible circuit boards 20). FIG. 12As shown, in an embodiment where the number of flexible circuit boards 20 is four, the test terminal TPa may include a first input terminal ITa, a second input terminal OTa, and a first to fourth measurement terminal portions MTP1a, MTP2a, MTP3a, and MPT4a, each comprising 10 measurement terminals, and thus may include a total of 42 test terminals.

[0214] In the display device 1 according to this embodiment, by reducing the number of all test terminals TPa used to measure the first to third connection resistances of each of the plurality of flexible circuit boards 20 to 10n+2, and thereby reducing the space occupied by the test terminals TPa on the printed circuit board 30, the limitations on the design and arrangement of the test pads can be significantly reduced, and the printed circuit board 30 can be miniaturized.

[0215] FIG. 16 This is a schematic cross-sectional view of the display area of ​​the display panel 10 included in the display device according to the embodiment.

[0216] refer to FIG. 16 The display panel 10 includes a substrate 110 and various layers and wiring thereon. The substrate 110 may include an insulating material, such as glass or plastic. For example, the substrate 110 may have a multilayer structure including two resin layers with an inorganic material layer therebetween.

[0217] A light-blocking layer LB can be located on the substrate 110. The light-blocking layer LB can block external light from reaching the semiconductor layer AL of the transistor TR, thereby preventing or reducing the degradation of the characteristics of the semiconductor layer AL. The light-blocking layer LB can be an electrode that receives a specific voltage or a wiring that transmits a specific voltage in the display panel 10. The light-blocking layer LB can include copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), titanium (Ti), or tantalum (Ta), and can have a single-layer structure or a multi-layer structure.

[0218] This can include silicon nitride (SiN) x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y An inorganic insulating material barrier layer (not shown) can be disposed between the substrate 110 and the light-blocking layer LB. The barrier layer can have a single-layer structure or a multi-layer structure.

[0219] Buffer layer 120 may be located on light-blocking layer LB. Buffer layer 120 can prevent impurities from diffusing from substrate 110 to semiconductor layer AL, and can provide a planarized or flattened upper surface. Buffer layer 120 may include materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x) or silicon oxynitride (SiO x N y ) and can have a single-layer structure or a multi-layer structure.

[0220] The semiconductor layer AL can be located on the buffer layer 120. The semiconductor layer AL can include a channel region of the transistor TR and a source region and a drain region on opposite sides of the channel region. The semiconductor layer AL can include one of amorphous silicon, polysilicon, and an oxide semiconductor. When the semiconductor layer AL includes an oxide semiconductor, the semiconductor layer AL can include at least one of zinc (Zn), indium (In), gallium (Ga), and tin (Sn). For example, the semiconductor layer AL can include indium gallium zinc oxide (IGZO).

[0221] The gate insulating layer 140 can be located on the semiconductor layer AL. The gate insulating layer 140 can include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ) and can have a single-layer structure or a multi-layer structure.

[0222] The gate electrode GE of the transistor TR can be located on the gate insulating layer 140. The gate electrode GE can include molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), etc.

[0223] The interlayer insulating layer 160 can be located on the gate electrode GE. The interlayer insulating layer 160 can include an inorganic insulating material such as silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO x N y ) and can have a single-layer structure or a multi-layer structure.

[0224] The source electrode SE and the drain electrode DE of the transistor TR can be located on the interlayer insulating layer 160. If necessary, the drain electrode DE can be connected to the light-blocking layer LB through a contact hole formed in the interlayer insulating layer 160 and the buffer layer 120. The source electrode SE and the drain electrode DE can each include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), or copper (Cu), etc.

[0225] A planarization layer 180 can be located on the source electrode SE and the drain electrode DE. The planarization layer 180 can be an organic layer. For example, the planarization layer 180 can include an organic insulating material such as a general-purpose polymer (e.g., polymethyl methacrylate or polystyrene), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, a polyimide, or a siloxane polymer.

[0226] A pixel electrode E1 of a light-emitting diode LED can be located on the planarization layer 180. The pixel electrode E1 can be connected to the drain electrode DE through a contact hole formed in the planarization layer 180. The pixel electrode E1 can include a reflective conductive material or a semi-transmissive conductive material, or can include a transparent conductive material. For example, the pixel electrode E1 can include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or can include a metal such as lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg), or gold (Au) or a metal alloy.

[0227] A pixel-defining layer 360 having an opening overlapping the pixel electrode E1 can be located on the planarization layer 180. The pixel-defining layer 360 can include an organic insulating material such as an acrylic polymer or an imide polymer.

[0228] An emission layer EL can be located on the pixel electrode E1. In addition to the emission layer EL, at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer can be on the pixel electrode E1.

[0229] A common electrode E2 can be located on the emission layer EL. The common electrode E2 can be integrally formed as one body for a plurality of pixels. The common electrode E2 can include a metal or a metal alloy having a low work function such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), or silver (Ag), and can be formed as a thin layer and have light transmittance. If necessary, the common electrode E2 can include a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0230] A light-emitting diode LED such as an organic light-emitting diode can be located in each pixel. Each light-emitting diode LED can include the pixel electrode E1, the emission layer EL, and the common electrode E2 as described above. The pixel electrode E1 can be an anode of the light-emitting diode LED, and the common electrode E2 can be a cathode of the light-emitting diode LED.

[0231] An encapsulation layer (not shown) can be located on the common electrode E2. The encapsulation layer can be a thin film encapsulation layer in which one or more inorganic layers and one or more organic layers are stacked.

[0232] According to one or more embodiments, the display device can allow the bonding state between the flexible circuit board and the display panel and the bonding state between the flexible circuit board and the printed circuit board to be effectively tested. However, the above-described effects are examples, and the scope of the disclosure is not limited by these effects.

[0233] It is to be understood that the embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as being applicable to other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display apparatus comprising: a display panel including a panel test pad portion; a printed circuit board including a printed circuit board (PCB) test pad portion and a test terminal; and a flexible circuit board including a first transfer pad portion electrically connected to the panel test pad portion and a second transfer pad portion electrically connected to the PCB test pad portion, wherein the panel test pad portion includes a first panel pad, a second panel pad, and a third panel pad, the PCB test pad portion includes a first PCB pad electrically connected to the first panel pad, a second PCB pad electrically connected to the second panel pad, a third PCB pad electrically connected to the second panel pad, and a fourth PCB pad electrically connected to the third panel pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad, a second input terminal, a first measurement terminal electrically connected to the second PCB pad, a second measurement terminal electrically connected to the third PCB pad, and a third measurement terminal electrically connected to the fourth PCB pad.

2. The display device according to claim 1, wherein the second input terminal is electrically connected to the second PCB pad, and wherein, when a test current is applied to the first input terminal, the test current flows through a current path including the first PCB pad, the first panel pad, the second panel pad, and the second PCB pad.

3. The display device according to claim 1, wherein the first transfer pad portion includes a 1-1 transfer pad overlapping the first panel pad, a 1-2 transfer pad overlapping the second panel pad, and a 1-3 transfer pad overlapping the third panel pad, and the second transfer pad portion includes a 2-1 transfer pad overlapping the first PCB pad, a 2-2 transfer pad overlapping the second PCB pad, a 2-3 transfer pad overlapping the third PCB pad, and a 2-4 transfer pad overlapping the fourth PCB pad, and wherein the 2-1 transfer pad is electrically connected to the 1-1 transfer pad through a first wiring, the 2-2 transfer pad is electrically connected to the 1-2 transfer pad through a second wiring, the 2-3 transfer pad is electrically connected to the 1-2 transfer pad through the second wiring and a sub wiring connected to the second wiring, and the 2-4 transfer pad is electrically connected to the 1-3 transfer pad through a third wiring. 4.The display apparatus of claim 1, further comprising an integrated circuit (IC) chip including an IC test pad portion, wherein the display panel further includes an IC transfer pad portion electrically connected to the IC test pad portion, and the IC test pad portion includes a first IC test pad, a second IC test pad, and a third IC test pad, and wherein the first IC test pad is electrically connected to the first panel pad, and the second IC test pad is electrically connected to the second panel pad.

5. The display device of claim 4, wherein, the second input terminal is electrically connected to the second PCB pad, and wherein, when a test current is applied to the first input terminal, the test current flows through a current path including the first PCB pad, the first panel pad, the first IC test pad, the second IC test pad, the second panel pad, and the second PCB pad.

6. The display device according to claim 4, wherein the IC transmission pad portion includes a first IC transmission pad overlapping the first IC test pad, a second IC transmission pad overlapping the second IC test pad, and a third IC transmission pad overlapping the third IC test pad, and the panel test pad portion further includes a fourth panel pad and a fifth panel pad, wherein the first panel pad is electrically connected to the first IC transmission pad by a first panel wiring, the second panel pad is electrically connected to the second IC transmission pad by a second panel wiring, the third panel pad is electrically connected to the second IC transmission pad by the second panel pad and a third panel wiring electrically connecting the second panel pad to the third panel pad, the fourth panel pad is electrically connected to the second IC transmission pad by a fourth panel wiring, and the fifth panel pad is electrically connected to the third IC transmission pad by a fifth panel wiring, wherein the PCB test pad portion further includes a fifth PCB pad electrically connected to the fourth panel pad and a sixth PCB pad electrically connected to the fifth panel pad, and the test terminal further includes a fourth measurement terminal electrically connected to the fifth PCB pad and a fifth measurement terminal electrically connected to the sixth PCB pad.

7. The display device according to claim 1, wherein a plurality of panel test pad portions are provided, a plurality of PCB test pad portions are provided, and a plurality of flexible circuit boards are provided, wherein the plurality of flexible circuit boards are respectively positioned to correspond to the plurality of panel test pad portions and to correspond to the plurality of PCB test pad portions, wherein the first input terminal is electrically connected to the first PCB pad of a first PCB pad group of a first PCB test pad portion among the plurality of PCB test pad portions by a first PCB wiring, the second input terminal is electrically connected to the first PCB pad of a second PCB pad group of a second PCB test pad portion among the plurality of PCB test pad portions by a second PCB wiring, and a plurality of first measurement terminals, a plurality of second measurement terminals, and a plurality of third measurement terminals respectively electrically connected to the plurality of PCB test pad portions are provided.

8. A display device comprising: a display panel including a panel test pad portion; a printed circuit board including a printed circuit board (PCB) test pad portion and a test terminal; and a flexible circuit board including a first transmission pad portion electrically connected to the panel test pad portion and a second transmission pad portion electrically connected to the PCB test pad portion, wherein the panel test pad portion includes a first panel pad and a second panel pad, the first transmission pad portion includes a 1-1 transmission pad overlapping the first panel pad and a 1-2 transmission pad overlapping the second panel pad, the second transmission pad portion includes a 2-1 transmission pad electrically connected to the 1-1 transmission pad through a first wiring, a 2-2 transmission pad electrically connected to the 1-2 transmission pad through a second wiring, and a 2-3 transmission pad electrically connected to the 1-2 transmission pad through the second wiring and a sub wiring connected to the second wiring, the PCB test pad portion includes a first PCB pad overlapping the 2-1 transmission pad, a second PCB pad overlapping the 2-2 transmission pad, and a third PCB pad overlapping the 2-3 transmission pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad, a second input terminal electrically connected to the second PCB pad, a first measurement terminal electrically connected to the second PCB pad, and a second measurement terminal electrically connected to the third PCB pad.

9. A display device comprising: a display panel including a first panel test pad portion and a second panel test pad portion; a printed circuit board including a first PCB test pad portion, a second PCB test pad portion, and a test terminal; and a first flexible circuit board having one end connected to the first panel test pad portion and an opposite end connected to the first PCB test pad portion, and a second flexible circuit board having one end connected to the second panel test pad portion and an opposite end connected to the second PCB test pad portion, wherein each of the first PCB test pad portion and the second PCB test pad portion includes a first PCB pad group and a second PCB pad group, each of the first PCB pad group and the second PCB pad group includes a first PCB pad, a second PCB pad, a third PCB pad, and a fourth PCB pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad of the first PCB pad group of the first PCB test pad portion, a second input terminal electrically connected to the first PCB pad of the second PCB pad group of the second PCB test pad portion, a first measurement terminal portion electrically connected to the first PCB test pad portion, and a second measurement terminal portion electrically connected to the second PCB test pad portion.

9. A display device comprising: a display panel including a first panel test pad portion and a second panel test pad portion; a printed circuit board including a first PCB test pad portion, a second PCB test pad portion, and a test terminal; and a first flexible circuit board having one end connected to the first panel test pad portion and an opposite end connected to the first PCB test pad portion, and a second flexible circuit board having one end connected to the second panel test pad portion and an opposite end connected to the second PCB test pad portion, wherein each of the first PCB test pad portion and the second PCB test pad portion includes a first PCB pad group and a second PCB pad group, each of the first PCB pad group and the second PCB pad group includes a first PCB pad, a second PCB pad, a third PCB pad, and a fourth PCB pad, and the test terminal includes a first input terminal electrically connected to the first PCB pad of the first PCB pad group of the first PCB test pad portion, a second input terminal electrically connected to the first PCB pad of the second PCB pad group of the second PCB test pad portion, a first measurement terminal portion electrically connected to the first PCB test pad portion, and a second measurement terminal portion electrically connected to the second PCB test pad portion. wherein each of the first and second measurement terminal portions includes a 1-1 measurement terminal electrically connected to the second PCB pad of the first PCB pad group, a 2-1 measurement terminal electrically connected to the third PCB pad of the first PCB pad group, a 3-1 measurement terminal electrically connected to the fourth PCB pad of the first PCB pad group, a 1-2 measurement terminal electrically connected to the second PCB pad of the second PCB pad group, a 2-2 measurement terminal electrically connected to the third PCB pad of the second PCB pad group, and a 3-2 measurement terminal electrically connected to the fourth PCB pad of the second PCB pad group.

10. An electronic device, comprising: the display device according to any one of claims 1 to 9; and a housing accommodating the display device.

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