Flexible circuit board, chip on film module, and electronic device including the same

Abstract

A flexible circuit board includes a substrate, a plurality of circuit patterns disposed on the substrate, and a protective layer disposed on the circuit patterns, wherein each of the plurality of circuit patterns has a thickness greater than 8 µm and less than or equal to 25 µm, and wherein a thickness deviation between the plurality of circuit patterns is 0.5 µm to 3 µm. When the flexible circuit board is connected with a display panel, the display panel can have high performance and high current can flow through the display panel. The circuit pattern having the features according to the present invention is prevented from being damaged by high current.

Description

Technical Field

[0001] The embodiments relate to a flexible circuit board, a flip-chip thin film module, and an electronic device including the flip-chip thin film module. Background Technology

[0002] Recently, electronic products have been becoming increasingly thinner and smaller. As a result, it is necessary to install semiconductor chips at high density in the narrow areas of electronic products.

[0003] Chip-on-film (COF) comprises a circuit board and a chip disposed on that circuit board. The circuit board is flexible; that is, COF is a flexible circuit board. Therefore, COF is used in flexible displays. For example, COF can be used in various wearable electronic devices. Furthermore, COF has fine pitch. Therefore, COF is used in displays with high resolution.

[0004] Chips include semiconductor chips. For example, a chip can be an integrated circuit (IC) chip or a large-scale integrated circuit (LSI) chip.

[0005] The chip is connected to an external circuit board and a display panel via a circuit pattern. For example, pads are provided at one end and the other end of the circuit pattern. One pad is electrically connected to a terminal of the chip. The other pad is connected to a terminal of the external circuit board and the display panel. Therefore, the chip, the external circuit board, and the display panel are electrically connected via a flip-chip film. Thus, signals are transmitted to the display panel through the circuit pattern.

[0006] As display panel performance improves, the current draw of the display panel increases. Therefore, the flexible circuit board is connected to the display panel. Consequently, the circuit patterns may be damaged by the high current. As a result, the reliability of the flip-chip module may decrease.

[0007] Therefore, there is a need for new structures of flexible circuit boards, flip-chip thin-film modules, and electronic devices that include them, which can solve the above problems.

[0008] As a patent related to flexible circuit boards, Korean Patent Registration No. KR10-0618898 (September 1, 2006) has been published. Summary of the Invention

[0009] Technical issues

[0010] The embodiments provide a flexible circuit board with improved reliability and a flip-chip thin film module including the flexible circuit board.

[0011] Technical means for solving technical problems

[0012] A flexible circuit board according to one embodiment includes: a substrate; a plurality of circuit patterns disposed on the substrate; and a protective layer disposed on the circuit patterns, wherein the thickness of each of the plurality of circuit patterns is greater than 8 μm and less than or equal to 25 μm, and wherein the thickness deviation between the plurality of circuit patterns is 0.5 μm to 3 μm.

[0013] In addition, each of the multiple circuit patterns includes a buffer layer disposed on the substrate, a metal layer disposed on the buffer layer, and a bonding layer disposed on the metal layer.

[0014] In addition, the bonding layer is configured to cover the side surface of the buffer layer, the side surface of the metal layer, and the top surface of the metal layer.

[0015] In addition, the thickness variation between the metal layers of multiple circuit patterns is 0.5 μm to 3 μm.

[0016] In addition, the metal layer includes a first metal layer and a second metal layer on the first metal layer, wherein the thickness of the second metal layer is greater than the thickness of the first metal layer.

[0017] In addition, the thickness deviation between the second metal layers of multiple circuit patterns is 0.5 μm to 3 μm.

[0018] In addition, the substrate includes a first side end and a second side end, and the protective layer includes a first open region that overlaps with the region between the first side end and the second side end along the thickness direction, a second open region that is spaced apart from the first open region and is closest to the first side end, and a third open region that is spaced apart from the first open region and the second open region and is closest to the second side end.

[0019] In addition, the multiple circuit patterns include: a first circuit pattern including a first pad portion disposed in a first open area, a second pad portion disposed in a second open area, and a first wiring portion connecting the first pad portion and the second pad portion; and a second circuit pattern including a third pad portion disposed in the first open area, a fourth pad portion disposed in the third open area, and a second wiring portion connecting the third pad portion and the fourth pad portion.

[0020] In addition, the thickness deviation of the first circuit pattern is 0.3 μm to 2.5 μm.

[0021] In addition, the thickness deviation of the second circuit pattern is 0.3 μm to 5 μm.

[0022] In addition, the thickness deviation of the first pad portion and the third pad portion is 0.3μm to 0.9μm respectively.

[0023] In addition, the thickness deviation of the second pad is 0.5μm to 3μm.

[0024] In addition, the thickness deviation of the fourth pad is 1μm to 5μm.

[0025] In addition, the multiple circuit patterns also include a third circuit pattern, which includes a fifth pad portion disposed in the second open area, a sixth pad portion disposed in the third open area, and a third wiring portion connecting the fifth pad portion and the sixth pad portion.

[0026] In addition, the thickness deviation between the first circuit pattern, the second circuit pattern and the third circuit pattern is 1 μm to 5 μm.

[0027] Furthermore, a first circuit pattern is disposed on one surface of the substrate, a third circuit pattern is disposed on another surface of the substrate, and a second circuit pattern is disposed on both the first and second surfaces and connected by a via.

[0028] Beneficial effects

[0029] A flexible circuit board according to one embodiment includes multiple circuit patterns. The circuit patterns have a defined thickness. Specifically, the thickness of the circuit patterns is greater than 8 μm. Furthermore, the circuit patterns have a uniform linewidth.

[0030] The flexible circuit board is connected to the display panel. The display panel can have high performance. Therefore, high current can flow through the display panel.

[0031] High current is transmitted to the flexible circuit board. Because the circuit pattern is formed within a set thickness range, damage to the circuit pattern by high current is prevented.

[0032] The circuit pattern has a uniform thickness. That is, the thickness deviation of the circuit pattern is small.

[0033] Specifically, the plating process used to form the circuit pattern is controlled. Specifically, during the plating process, a shielding layer can be placed in areas with thicker plating thickness to control the plating thickness in other areas to have a uniform thickness.

[0034] Therefore, the thickness deviation between circuit patterns is reduced. Furthermore, the thickness deviation of each circuit pattern is reduced. Additionally, the thickness deviation of each pad is reduced.

[0035] Therefore, the signals or currents flowing in each circuit pattern become more uniform. Consequently, the electrical characteristics of flexible circuit boards and flip-chip thin-film modules are improved. Attached Figure Description

[0036] Figure 1 This is a top view of a flexible circuit board according to one embodiment.

[0037] Figure 2 and Figure 3 It is along Figure 1A cross-sectional view taken from region A-A'.

[0038] Figure 4 It is along Figure 1 A cross-sectional view taken from region B-B'.

[0039] Figure 5 and Figure 6 This is a diagram showing the first step in forming a circuit pattern.

[0040] Figure 7 It is a scanning electron microscope (SEM) image of the circuit pattern formed through the first process.

[0041] Figures 8 to 16 This is a diagram showing the second step in forming the circuit pattern.

[0042] Figure 17 It is a scanning electron microscope (SEM) image of a circuit pattern formed through the second process.

[0043] Figure 18 This is a diagram illustrating the connection between a flip-chip thin film module and other components according to one embodiment.

[0044] Figures 19 to 21 This is a diagram illustrating an electronic device including a flexible circuit board according to one embodiment. Detailed Implementation

[0045] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the spirit and scope of the present invention are not limited to the portion of the described embodiments, and it can be implemented in many other forms. Furthermore, within the spirit and scope of the present invention, one or more elements of the embodiments can be selectively combined and reconfigured.

[0046] Furthermore, unless otherwise expressly defined and described, the terms (including technical and scientific terms) used in the embodiments of this invention may be interpreted as having the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains, and terms defined in common dictionaries may be interpreted as having the same meaning as in the context of the relevant technical field.

[0047] Furthermore, the terminology used in the embodiments of this invention is for describing the implementation methods and is not intended to limit the invention. In this specification, unless otherwise specified in the phrase, the singular form may also include the plural form, and when described as "at least one (or more) of A (and), B and C", it may include at least one of all possible combinations of A, B and C.

[0048] Furthermore, when describing the elements of embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the element from other elements, and they do not limit the nature, order, or sequence of the elements.

[0049] Furthermore, when an element is described as being “connected” or “coupled” to another element, it includes not only cases where the element is directly “connected” or “coupled” to other elements, but also cases where the “connection” or “coupling” between the element and the other element is achieved through another element.

[0050] Additionally, when described as being formed or set "above" or "below" each element, "above" or "below" includes not only the case where two elements are directly connected to each other, but also the case where one or more other elements are formed or set between the two elements.

[0051] Furthermore, when expressed as "above" or "below", it can include not only the upward direction based on an element, but also the downward direction.

[0052] In the following description, the first direction 1D is the direction in which the pads of the display panel and the pads of the circuit board face each other. Furthermore, the second direction 2D is a direction perpendicular to the first direction 1D.

[0053] The following description, in conjunction with the accompanying drawings, describes a flexible circuit board according to one embodiment and a flip-chip module including the flexible circuit board.

[0054] Reference Figure 1 The flexible circuit board 1000 according to the embodiment includes a substrate 100, a circuit pattern, and a protective layer 300.

[0055] The substrate 100 includes a first surface 1S and a second surface 2S opposite to the first surface 1S. A circuit pattern and a protective layer 300 are disposed on the first surface 1S.

[0056] The substrate 100 includes a dicing line CL. The flexible circuit board 1000 is cut along the dicing line CL. For example, circuit patterns, metal patterns, protective layers, and chips are disposed on the substrate 100. Subsequently, the substrate 100 is cut along the dicing line CL. This manufactures a flip-chip thin-film module. Therefore, the edge of the flip-chip thin-film module becomes the dicing line CL.

[0057] The substrate 100 includes an effective region AA and an ineffective region UA. Specifically, the first surface 1S includes the effective region AA and the ineffective region UA.

[0058] The valid region AA and the invalid region UA ​​are separated by the tangent line CL. The valid region AA is the region inside the tangent line CL. The invalid region UA ​​is the region outside the tangent line CL.

[0059] The circuit pattern, protective layer, and chip are disposed on the active area AA. Additionally, a dummy pattern and sprocket hole SH are disposed on the inactive area UA. The dummy pattern increases the strength of the substrate 100. Furthermore, the flexible circuit board 1000 is rolled up or unrolled in a roll-to-roll manner through the sprocket hole SH.

[0060] The substrate 100 includes a chip mounting region CHA. The chip mounting region CHA is disposed on a first surface 1S. The chip mounting region CHA is disposed on an effective region AA. The chip CH is disposed on the chip mounting region CHA. Furthermore, the pad portion of the circuit pattern is disposed within the chip mounting region CHA. Furthermore, the protective layer 300 is not disposed on the chip mounting region CHA.

[0061] The substrate 100 includes a flexible material. For example, the substrate 100 may include polyimide (PI). However, the implementation is not limited to this. The substrate 100 may include a polymer material comprising polyethylene terephthalate (PET) or polyethylene naphthalate (PEN). Therefore, flexible circuit boards can be applied to various electronic devices, including curved display devices.

[0062] The thickness of substrate 100 can be from 20 μm to 100 μm. For example, the thickness of substrate 100 can be from 25 μm to 50 μm. For example, the thickness of substrate 100 can be from 30 μm to 40 μm. If the thickness of substrate 100 exceeds 100 μm, the overall thickness of the flexible circuit board increases. As a result, the flexibility of the flexible circuit board may be reduced. Furthermore, if the thickness of substrate 100 is less than 20 μm, the heat and pressure applied to the substrate when mounting the chip onto the flexible circuit board may damage substrate 100.

[0063] A circuit pattern and a protective layer 300 are disposed on the substrate 100. Specifically, the circuit pattern and the protective layer 300 are disposed on the first surface 1S. Specifically, the circuit pattern and the protective layer 300 are disposed on at least one region among the active region AA and the inactive region UA.

[0064] The circuit pattern includes a first circuit pattern 210, a second circuit pattern 220, and a third circuit pattern 230.

[0065] Reference Figure 1The first circuit pattern 210 includes a first wiring portion 211, a first pad portion 212a, and a second pad portion 212b. The first wiring portion 211, the first pad portion 212a, and the second pad portion 212b may be made of the same material. Furthermore, the first wiring portion 211, the first pad portion 212a, and the second pad portion 212b may be integrally formed.

[0066] The first pad portion 212a is provided within the chip mounting area CHA. Thus, the first pad portion 212a is connected to the terminals of the chip. Thus, the first circuit pattern 210 is connected to the chip.

[0067] The second pad portion 212b is disposed outside the chip mounting area CHA. The second pad portion 212b is connected to the pad portion of the circuit board 3000. Thus, the first circuit pattern 210 is connected to the circuit board 3000.

[0068] A first wiring section 211 is disposed between a first pad section 212a and a second pad section 212b. The first wiring section 211 connects the first pad section 212a and the second pad section 212b. Thus, the chip CH is connected to the circuit board 3000. As a result, the signal generated by the chip CH is transmitted to the circuit board 3000.

[0069] The first circuit pattern 210 may also include a test pad section. Specifically, the first test pad section TP1 is disposed on the non-active area UA. The first wiring section 211, the first pad section 212a, the second pad section 212b, and the first test pad section TP1 may be integrally formed.

[0070] Before connecting the circuit board to the second pad portion 212b, the first circuit pattern 210 can be tested by the first test pad portion TP1. For example, the first test pad portion TP1 can be used to check whether there is an open circuit or a short circuit in the first circuit pattern.

[0071] The second circuit pattern 220 includes a second wiring portion 221, a third pad portion 222a, and a fourth pad portion 222b. The second wiring portion 221, the third pad portion 222a, and the fourth pad portion 222b may be made of the same material. Furthermore, the second wiring portion 221, the third pad portion 222a, and the fourth pad portion 222b may be integrally formed.

[0072] The third pad portion 222a is provided within the chip mounting area CHA. Thus, the third pad portion 222a is connected to the chip's terminals. Consequently, the second circuit pattern 220 is connected to the chip CH.

[0073] The fourth pad portion 222b is provided outside the chip mounting area CHA. The fourth pad portion 222b is connected to the pad portion of the external display panel 4000. Thus, the second circuit pattern 220 is connected to the display panel 4000.

[0074] The second wiring section 221 is disposed between the third pad section 222a and the fourth pad section 222b. The second wiring section 221 connects the third pad section 222a and the fourth pad section 222b. Thus, the chip CH is connected to the display panel 4000. As a result, the signal generated by the chip CH is transmitted to the display panel 4000.

[0075] The second circuit pattern 220 may also include a test pad section. Specifically, the second test pad section TP2 is disposed on the inactive area UA. The second test pad section TP2 is disposed outside the cut line CL. The second test pad section TP2 is disposed on the inactive area UA. The second wiring section 221, the third pad section 222a, the fourth pad section 222b, and the second test pad section TP2 can be integrally formed.

[0076] Before connecting the circuit board and the fourth pad portion 222b, the second circuit pattern 220 can be tested using the second test pad portion TP2. For example, the second test pad portion TP2 can be used to check whether the second circuit pattern has an open circuit or a short circuit.

[0077] The third circuit pattern 230 includes a third wiring portion 231, a fifth pad portion 232a, and a sixth pad portion 232b. The third wiring portion 231, the fifth pad portion 232a, and the sixth pad portion 232b may be made of the same material. Furthermore, the third wiring portion 231, the fifth pad portion 232a, and the sixth pad portion 232b may be integrally formed.

[0078] The fifth pad portion 232a and the sixth pad portion 232b are provided outside the chip mounting area CHA. The fifth pad portion 232a can be connected to the pad portion of the circuit board. In addition, the sixth pad portion 232b can be connected to the pad portion of the display panel 4000.

[0079] The third wiring section 231 is disposed between the fifth pad section 232a and the sixth pad section 232b. The third wiring section 231 connects the fifth pad section 232a and the sixth pad section 232b. Thus, the circuit board 3000 is connected to the display panel 4000.

[0080] The third circuit pattern 230 can be a bypass circuit. For example, the third circuit pattern 230 can be a power supply pattern. Thus, the circuit board and the display panel can be powered by the third circuit pattern 230.

[0081] The third circuit pattern 230 may include a plurality of third circuit patterns spaced apart in the second direction 2D. The line width and spacing of the third circuit pattern 230 may be greater than the line width and spacing of the first circuit pattern 210. Furthermore, the line width and spacing of the third circuit pattern 230 may be greater than the line width and spacing of the second circuit pattern 220.

[0082] Although not shown in the accompanying drawings, at least one virtual pattern can be set on the effective area AA.

[0083] Virtual patterns can prevent the flexible circuit board 1000 from bending. In addition, the spacing and line width of the circuit patterns can be made uniform through virtual patterns.

[0084] The virtual pattern may include the same material as the circuit pattern. The linewidth of the virtual pattern may be the same as or different from that of the circuit pattern. The virtual pattern is not connected to the chip CH, circuit board 3000, or display panel 4000.

[0085] At least one of the third circuit pattern and the virtual pattern can be the outermost pattern. Specifically, the outermost pattern on the second direction 2D of the substrate 100 can be at least one of the third circuit pattern and the virtual pattern.

[0086] A protective layer 300 is disposed on the first surface 1S. Therefore, the protective layer 300 is disposed on the first circuit pattern 210, the second circuit pattern 220, and the third circuit pattern 230. The protective layer 300 is disposed on the first wiring portion 211, the second wiring portion 221, and the third wiring portion 231. The protective layer 300 is not disposed on the first pad portion 212a, the second pad portion 212b, the third pad portion 222a, the fourth pad portion 222b, the fifth pad portion 232a, and the sixth pad portion 232b. Furthermore, the protective layer 300 is not disposed on the chip mounting area CHA.

[0087] Reference Figure 2 and Figure 3 The circuit pattern is formed into a multi-layered structure. Figure 2 and Figure 3 The following description is based on the first circuit pattern. The same applies to the second and third circuit patterns.

[0088] Reference Figure 2 The first circuit pattern is formed as a multi-layer structure. Specifically, the first wiring portion 211, the first pad portion 212a, and the second pad portion 212b include a buffer layer 205, a metal layer 201, and a bonding layer 203.

[0089] The buffer layer 205 may include a multilayer structure. Specifically, the buffer layer 205 includes a first buffer layer 205a and a second buffer layer 205b. The first buffer layer 205a is disposed on the substrate 100. The second buffer layer 205b is disposed on the first buffer layer 205a.

[0090] The first buffer layer 205a includes a material that has good adhesion to the substrate 100. For example, the first buffer layer 205a may include nickel (Ni). Furthermore, the second buffer layer 205b includes a material that has good adhesion to circuit patterns. For example, the second buffer layer 205b may include chromium (Cr).

[0091] The buffer layer 205 can have a film thickness in the nanometer unit. For example, the thickness of the buffer layer 205 can be less than 20 nm.

[0092] The adhesion between the substrate 100 and the circuit pattern is improved by the buffer layer 205.

[0093] A metal layer 201 is disposed on the buffer layer 205. Specifically, the metal layer 201 is disposed on the second buffer layer 205b. The metal layer 201 comprises a metallic material. For example, the metal layer 201 may comprise copper (Cu).

[0094] The metal layer 201 can be formed by electroplating with a buffer layer as the seed layer. That is, the metal layer 201 can be a plating layer.

[0095] The thickness of the metal layer 201 can be from 10 μm to 30 μm.

[0096] The bonding layer 203 is disposed on the metal layer 201.

[0097] A bonding layer 203 is disposed on the side surface and the top surface of the metal layer 201. For example, the bonding layer 203 may be disposed in a manner that surrounds the metal layer 201.

[0098] The bonding layer 203 comprises metal. For example, the bonding layer 203 may comprise tin (Sn). The bonding layer 203 is formed by a plating process. Specifically, the bonding layer 203 may be a plating layer.

[0099] The thickness of the bonding layer 203 can be from 0.3 μm to 0.7 μm. The tin content can increase from the lower surface of the bonding layer 203 toward the upper surface of the bonding layer 203.

[0100] That is, the bonding layer 203 is in contact with the metal layer 201. Therefore, the tin content increases from the lower surface of the bonding layer 203 toward the upper surface of the bonding layer 203. In addition, the copper content decreases from the lower surface of the bonding layer 203 toward the upper surface of the bonding layer 203.

[0101] Thus, pure tin can be retained within a thickness range of 0.1 μm to 0.3 μm from the upper surface of the bonding layer 203.

[0102] Through bonding layer 203, the pad portion can be easily bonded to the terminals of circuit boards, display panels, and chips. For example, when heat and pressure are applied to the pad portion, the upper surface of the bonding layer melts. Pure tin remains on the upper surface of the bonding layer. Therefore, the pad portion can be easily bonded to the terminals of circuit boards, display panels, and chips.

[0103] Reference Figure 3 The metal layer 201 may include a first metal layer 201a and a second metal layer 201b. The first metal layer 201a is disposed on the buffer layer 205. The second metal layer 201b is disposed on the first metal layer 201a. The second metal layer 201b can be formed by electroplating with the first metal layer 201a as a seed layer. That is, the second metal layer 201b can be a plating layer.

[0104] The thickness of the first metal layer 201a can be less than the thickness of the second metal layer 201b.

[0105] For example, the thickness of the first metal layer 201a can be from 0.7 μm to 2 μm, and the thickness of the second metal layer 201b can be from 6 μm to 25 μm.

[0106] The first metal layer 201a and the second metal layer 201b may comprise the same metallic material. For example, the first metal layer 201a and the second metal layer 201b may comprise copper (Cu).

[0107] The bonding layer 203 may include a first bonding layer 203a and a second bonding layer 203b.

[0108] The first bonding layer 203a is disposed on the metal layer 201. Specifically, the first bonding layer 203a is disposed on the second wiring portion 221, the third pad portion 222a, and the fourth pad portion 222b.

[0109] The second bonding layer 203b is disposed on the first bonding layer 203a. Specifically, the second bonding layer 203b is disposed on the third pad portion 222a and the fourth pad portion 222b.

[0110] Therefore, the second wiring portion 221 includes a buffer layer 205, a metal layer 201, and a first bonding layer 203a. In addition, the third pad portion 222a and the fourth pad portion 222b include a buffer layer 205, a metal layer 201, a first bonding layer 203a, and a second bonding layer 203b.

[0111] Therefore, the layer structure of the second wiring section 221 is different from the layer structure of the first pad section 212a and the second pad section 212b.

[0112] The first bonding layer 203a and the second bonding layer 203b comprise metal. Specifically, the first bonding layer 203a and the second bonding layer 203b may comprise tin (Sn).

[0113] The first bonding layer 203a and the second bonding layer 203b are configured with different thicknesses. Specifically, the thickness of the second bonding layer 203b is greater than the thickness of the first bonding layer 203a.

[0114] For example, the first bonding layer 203a has a thickness of 0.02 μm to 0.06 μm. Furthermore, the second bonding layer 203b has a thickness of 0.2 μm to 0.6 μm.

[0115] Accordingly, the thickness of the first wiring portion 211 is reduced. The flexible circuit board includes a bent region BA that is bent in one area. The wiring portion is disposed on the bent region BA. Therefore, a bonding layer with a small thickness is formed on the wiring portion. Accordingly, cracks can be prevented from appearing in the first wiring portion 211 when the flexible circuit board is bent.

[0116] The thickness of the circuit pattern can be greater than 8 μm and less than or equal to 25 μm. Specifically, the thickness of the circuit pattern can be from 9 μm to 20 μm. Specifically, the thickness of the circuit pattern can be from 10 μm to 15 μm.

[0117] If the thickness of the circuit pattern is less than 8 μm, the resistance of the circuit pattern may increase. Furthermore, the circuit pattern may be damaged when a large current flows through the display panel. If the thickness of the circuit pattern exceeds 25 μm, it becomes difficult to achieve fine patterns.

[0118] Figure 4 For along Figure 1 Cross-sectional view of region B-B' in the middle.

[0119] The first wiring portion 211 includes a buffer layer 205, a first metal layer 201a, a second metal layer 201b, and a bonding layer 203. The buffer layer 205 and the bonding layer 203 are formed with a thin film thickness. Accordingly, the total thickness T3 of the first wiring portion 211 is determined by the thickness T2 of the metal layers (201a, 201b) or the thickness T2 of the second metal layer 201b.

[0120] Metal layers can be like Figure 2 The diagram shows a single metal layer. Alternatively, the metal layer can be formed as follows: Figure 3 The structure is formed as two metal layers.

[0121] Figures 5 to 7 This is a view used to illustrate the first step in forming the circuit pattern. The first step is as follows: Figure 2 The process shown is to form a circuit pattern using a metal layer.

[0122] Reference Figure 5 A buffer layer 205 is disposed on the substrate 100. A metal layer 201 is disposed on the buffer layer 205.

[0123] Subsequently, a photosensitive layer 400 is disposed on the metal layer 201. The photosensitive layer 400 forms multiple photosensitive patterns DP through exposure and development processes. The photosensitive patterns DP are disposed on the areas where circuit patterns are formed. Correspondingly, the areas between the photosensitive patterns DP become etching areas.

[0124] Reference Figure 6 This involves etching the etched area. For example, etchant is sprayed onto the etched area to etch it.

[0125] After etching the etched area, a bonding layer 203 is formed on the metal layer 201 to form a circuit pattern.

[0126] However, if the thickness of the metal layer 201 increases, the etching uniformity of the circuit pattern may decrease. For example, if the thickness of the metal layer 201 exceeds 8 μm, the linewidth uniformity of the circuit pattern may decrease. That is, the thickness of the metal layer 201 may be uniform, but the linewidth may be non-uniform.

[0127] Reference Figure 7 It can be seen that the line width W of circuit pattern 210 is uneven. That is, as shown... Figure 7 As shown in (a), the linewidth of the circuit pattern 210 increases as the circuit pattern 210 approaches the substrate 100. Correspondingly, the linewidths of the upper and lower surfaces of the circuit pattern 210 become different. As the thickness of the circuit pattern 210 increases, the linewidth difference between the upper and lower surfaces of the circuit pattern increases. Therefore, the linewidth W of the circuit pattern 210 becomes non-uniform at each location. Consequently, it is difficult to form a circuit pattern with fine linewidths.

[0128] Therefore, this embodiment forms the circuit pattern through a second process different from the first process.

[0129] Figures 8 to 17 This is a view showing the second process.

[0130] Reference Figure 8 A buffer layer 205 is disposed on the substrate 100. A first metal layer 201a is disposed on the buffer layer 205. The first metal layer 201a can be formed by electrolytic plating or chemical plating.

[0131] Reference Figure 9 and Figure 10 A photosensitive layer 400 is disposed on the first metal layer 201a. The photosensitive layer 400 forms multiple photosensitive patterns DP through exposure and development processes. The photosensitive patterns DP are disposed on areas where no circuit patterns are formed. Correspondingly, circuit patterns are formed on the areas between the photosensitive patterns DP. Correspondingly, the areas between the photosensitive patterns DP become plating areas. Accordingly, multiple plating areas are formed.

[0132] Reference Figures 11 to 14 A second metal layer 201b is deposited on the plating area. For example, a plating solution is sprayed onto the plating area. As the thickness of the second metal layer 201b increases, the plating thickness of each plating area may vary. Accordingly, the thickness deviation of multiple circuit patterns may increase.

[0133] For example, such as Figure 12 As shown, the thickness of one plating layer can be greater than the thickness of the plating layer in another region. Accordingly, the shielding layer 500 can be disposed on the plating region having a large plating layer thickness. The plating layer can have a large thickness in the wide region W2. Accordingly, the shielding layer 500 can be formed on the plating region having a large plating layer thickness. Plating is not performed on the plating regions overlapping with the shielding layer 500. Furthermore, plating is performed on the plating regions that do not overlap with the shielding layer 500. Therefore, the plating thickness in regions with large plating layer thickness and regions with small plating layer thickness can be uniformly controlled.

[0134] like Figure 13 As shown, the shielding layer 500 is set until the thickness of the plating layer in multiple plating areas becomes uniform. When the thickness of the plating layer in multiple plating areas becomes uniform, the shielding layer is removed.

[0135] Subsequently, as Figure 14 As shown, the plating process ends when the plating layer on the plating area reaches the set thickness.

[0136] Reference Figure 15 and Figure 16 The photosensitive pattern DP is removed. Then, the first metal layer 201a and buffer layer 205 disposed beneath the photosensitive pattern DP are etched to separate the multiple circuit patterns. During the etching of the first metal layer 201a and buffer layer 205, the second metal layer 201b is also etched. Therefore, the thickness of the second metal layer 201b may be slightly reduced from the thickness after the plating process. Thus, the plating process can be performed to a thickness slightly greater than the set circuit pattern thickness.

[0137] The second step is to deposit a second metal layer on the plated area. Accordingly, the linewidth of the circuit pattern can become uniform.

[0138] like Figure 17 As shown, the widths of the upper and lower parts of the circuit pattern can be similar. Accordingly, the linewidth W of the circuit pattern can become uniform. Furthermore, the linewidth deviation of multiple circuit patterns can be reduced.

[0139] Furthermore, the second process controls the plating thickness. Specifically, the thickness deviation of multiple plating areas is controlled by the shielding layer 500. Accordingly, the thickness of the circuit pattern can become uniform. In addition, the thickness deviation of multiple circuit patterns can be reduced.

[0140] Table 1

[0141] Table 2

[0142] Tables 1 and 2 show the thickness data of the circuit pattern formed through the second process. Tables 1 and 2 show the results after performing the plating process with a set thickness of 12 μm. Table 1 shows the comparative example data without using a shielding layer for plating. Table 2 shows the example data with a shielding layer for plating.

[0143] Referring to Table 1, the average thickness of the circuit pattern exceeds the set thickness. Furthermore, it can be seen that the thickness deviation of the circuit pattern is relatively large. In particular, it can be seen that the thickness deviation of the second and fourth pad portions is relatively large. Therefore, the thickness deviations of the first, second, third, and fourth pad portions also increase.

[0144] Referring to Table 2, the average thickness of the circuit pattern is similar to the set thickness. Furthermore, it can be seen that the thickness deviation of the circuit pattern is small. Specifically, the thickness deviation from the first pad to the fourth pad is less than 3 μm. Correspondingly, the thickness deviations of the first pad, second pad, third pad, and fourth pad are also reduced.

[0145] The thickness of the circuit pattern is determined by the thickness of the second metal layer. In this embodiment, the thickness of the second metal layer is controlled by the shielding layer.

[0146] Therefore, the thickness deviation of the second metal layer in the circuit pattern is reduced. Specifically, the thickness deviation of the second metal layer can be less than 3 μm. More specifically, the thickness deviation of the second metal layer can be 0.5 μm to 3 μm, 0.6 μm to 2.5 μm, or 0.5 μm to 2 μm.

[0147] Furthermore, the thickness deviation of the metal layer in the circuit pattern is reduced. Specifically, the thickness deviation of the metal layer can be less than 3 μm. More specifically, the thickness deviation of the metal layer can be 0.5 μm to 3 μm, 0.6 μm to 2.5 μm, or 0.5 μm to 2 μm.

[0148] Furthermore, the thickness deviation of the circuit pattern is reduced. Specifically, the thickness deviation of the circuit pattern can be less than 3 μm. More specifically, the thickness deviation of the circuit pattern can be 0.5 μm to 3 μm, 0.6 μm to 2.5 μm, or 0.5 μm to 2 μm.

[0149] In addition, the thickness deviation of each circuit pattern is reduced.

[0150] Specifically, the thickness deviation of the first circuit pattern can be 0.3μm to 2.5μm, 0.4μm to 2μm, or 0.5μm to 1.5μm.

[0151] Specifically, the thickness deviation of the second circuit pattern can be 0.3μm to 5μm, 0.4μm to 4μm, or 0.5μm to 2μm.

[0152] In addition, the thickness deviation of each pad is reduced.

[0153] Specifically, the thickness deviation of the first pad portion and the third pad portion can be from 0.3μm to 0.9μm.

[0154] In addition, the thickness deviation of the second pad portion can be 0.5μm to 3μm, 0.8μm to 2μm, or 1μm to 1.5μm.

[0155] In addition, the thickness deviation of the fourth pad can be 1μm to 5μm, 1.2μm to 3μm, or 1.5μm to 2μm.

[0156] Furthermore, the thickness deviation between the first, second, and third circuit patterns is reduced. The thickness deviation between the first, second, and third circuit patterns is the difference between the maximum and minimum thickness of each circuit pattern. The thickness deviation between the first, second, and third circuit patterns can be less than 5 μm. Specifically, the thickness deviation between the first, second, and third circuit patterns can be 1 μm to 5 μm, 1.2 μm to 4 μm, or 1.4 μm to 2 μm.

[0157] Therefore, the flexible circuit board according to this embodiment includes a circuit pattern having a uniform thickness and width. Furthermore, the circuit pattern has a thickness greater than 8 μm.

[0158] Therefore, damage to the circuit pattern due to the high current of the display panel can be prevented. Furthermore, because the linewidth and thickness of the circuit pattern become uniform, the current and signal flowing in each channel can become uniform. Accordingly, the electrical characteristics of the flexible circuit board and the flip-chip module are improved.

[0159] Reference Figure 18One end of the flip-chip thin-film module TP2 is connected to the display panel 4000, and the other end is connected to the circuit board 3000. For example, the display panel 4000 and the circuit board 3000 are disposed on one surface of the flip-chip thin-film module TP2. However, this embodiment is not limited to this. The display panel 4000 and the circuit board 3000 may also be disposed on different surfaces of the flip-chip thin-film module TP2. In this case, the flip-chip thin-film module TP2 may have circuit patterns disposed on both of its surfaces. For example, the flip-chip thin-film module TP2 may include a first circuit pattern and a second circuit pattern disposed on a first surface, and a second circuit pattern and a third circuit pattern disposed on a second surface. Each of the second circuit patterns can be interconnected through conductive portions.

[0160] Because the flip-chip module TP2 includes a flexible substrate, it has both a rigid shape and a curved shape between the display panel 3000 and the circuit board 4000. That is, the flip-chip module TP2 may include a curved region BA.

[0161] The flip-chip thin-film module TP2 connects the display panel 4000 and the circuit board 3000, which are positioned opposite each other, in a bent configuration. This reduces the thickness of the electronic device and increases design freedom. Furthermore, the flip-chip thin-film module TP2 prevents wiring disconnections even when bent, thus improving the reliability of the electronic device.

[0162] Because flip-chip thin-film modules are flexible, they can be used in a variety of electronic devices.

[0163] For example, refer to Figure 19 The flip-chip thin-film module can be applied to flexible touch windows. Therefore, a touch device containing this flip-chip thin-film module can be a flexible touch device. Thus, users can bend or fold the touch device by hand. This flexible touch window can be applied to wearable touch devices, etc.

[0164] Reference Figure 20 Chip-film modules can be applied to various wearable touch devices, including those with curved displays. Therefore, electronic devices incorporating chip-film modules can achieve a thinner and lighter design.

[0165] Reference Figure 21 Chip-free thin-film modules can be used in various electronic devices with display components, such as televisions, monitors, and laptops. In this regard, chip-free thin-film modules can also be used in electronic devices with curved display components.

[0166] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment of the present invention, but are not limited to only one embodiment. Furthermore, the features, structures, and effects shown in the embodiments can be combined or modified by those skilled in the art for use in other embodiments. Therefore, it should be understood that such combinations and modifications are included within the scope of the present invention.

[0167] Furthermore, the foregoing has primarily described embodiments, but these embodiments are merely examples and do not limit the invention. Those skilled in the art will understand that various modifications and applications not shown above can be made without departing from the essential characteristics of the embodiments. For example, the components specifically shown in the embodiments can be modified. Moreover, it should be considered that differences related to such modifications and applications are included within the scope of the invention as defined in the following claims.

Claims

1. A flexible circuit board, comprising: substrate; Multiple circuit patterns are disposed on the substrate; as well as A protective layer is disposed on the circuit pattern. Wherein, the thickness of each of the plurality of circuit patterns is greater than 8 μm and less than or equal to 25 μm, and The thickness deviation between the plurality of circuit patterns is 0.5 μm to 3 μm.

2. The flexible circuit board according to claim 1, wherein, Each of the plurality of circuit patterns includes: A buffer layer is disposed on the substrate; A metal layer is disposed on the buffer layer; and A bonding layer is disposed on the metal layer.

3. The flexible circuit board according to claim 2, wherein, The bonding layer is configured to cover the side surface of the buffer layer, the side surface of the metal layer, and the top surface of the metal layer.

4. The flexible circuit board according to claim 2, wherein, The thickness deviation between the metal layers of the plurality of circuit patterns is 0.5 μm to 3 μm.

5. The flexible circuit board according to claim 2, wherein, The metal layer includes a first metal layer and a second metal layer disposed on the first metal layer, and The thickness of the second metal layer is greater than the thickness of the first metal layer.

6. The flexible circuit board according to claim 5, wherein, The thickness deviation between the second metal layers of the plurality of circuit patterns is 0.5 μm to 3 μm.

7. The flexible circuit board according to claim 2, wherein, The substrate includes a first side end and a second side end. The protective layer includes: a first open region that overlaps with the region between the first side end and the second side end along the thickness direction; a second open region that is spaced apart from the first open region and is closest to the first side end; and a third open region that is spaced apart from the first open region and the second open region and is closest to the second side end.

8. The flexible circuit board according to claim 7, wherein, The plurality of circuit patterns include: The first circuit pattern includes a first pad portion disposed in the first open area, a second pad portion disposed in the second open area, and a first wiring portion connecting the first pad portion and the second pad portion; and The second circuit pattern includes a third pad portion disposed in the first open area, a fourth pad portion disposed in the third open area, and a second wiring portion connecting the third pad portion and the fourth pad portion.

9. The flexible circuit board according to claim 8, wherein, The thickness deviation of the first circuit pattern is from 0.3 μm to 2.5 μm.

10. The flexible circuit board according to claim 9, wherein, The thickness deviation of the second circuit pattern is 0.3 μm to 5 μm.

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