Circuit supporting external adjustability and built-in fixed minimum soft start time

Abstract

The utility model discloses a circuit supporting external adjustable and built-in fixed minimum soft start time, which comprises a chip internal system module, an enabling end EN, a reference current Iref, field effect transistors P1-P7 and field effect transistors N1-N7, one path of the enabling end EN is electrically connected with the grid electrode of the field effect transistor P2, and the other path of the enabling end EN is electrically connected with the grid electrode of the field effect transistor N3 through the inverter INV1; the drain electrode of the field effect transistor P2 is electrically connected with the grid electrode of the field effect transistor P1, the grid electrode of the field effect transistor P3 and the grid electrode of the field effect transistor P4. The drain electrode of the field effect transistor P1 is grounded through reference current Iref. According to the circuit supporting external adjustability and the built-in fixed minimum soft start time disclosed by the utility model, the requirements of the built-in fixed minimum soft start time and the longer external soft start time are met.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of analog integrated circuit, specifically relates to a support external adjustable and built -in fixed minimum soft start time circuit. BACKGROUND

[0002] The demand of power IC has increased greatly in recent years, especially the demand of domestic substitution, many domestic companies have launched switching power supply products or related power products, which involve the problem of starting reliability. Taking the boost DCDC as an example, generally, large inductance and large capacitance are used, when the chip is powered on, the input will charge the output capacitor through the inductor, at this time, the inductor current is uncontrollable, if the chip starts to work at this time, the switch will flow into a large surge current, which may cause the power tube to burn out. This is a reliability condition. In addition, even if the output capacitor charging has ended, if there is no soft start circuit, the chip will start switching immediately, and the output voltage will rise immediately according to the set value, which will cause a large current surge and voltage overshoot, which may also cause the chip to burn out.

[0003] Therefore, it is necessary to increase the soft start circuit, which can realize the slow rise of the output voltage by clamping the internal control node, that is, to complete a soft start, generally, an external soft start port is needed, which is connected with resistance and capacitance to ground, used for setting the soft start time. However, sometimes due to the limitation of packaging or the simplification of peripherals, there is no such port, so it is necessary to design the built-in soft start time, but due to the limitation of chip area, the size of the built-in capacitor is limited, if it is necessary to ensure sufficient reliability, the port must be sealed out during packaging. Therefore, it is necessary to design the circuit with built-in fixed minimum soft start time to ensure most application conditions, and support external setting of soft start time, which can exceed the internal soft start time.

[0004] Therefore, in view of the above problems, further improvement is needed. UTILITY MODEL CONTENTS

[0005] The main purpose of the utility model is to provide a support external adjustable and built-in fixed minimum soft start time circuit, which overcomes the demand of built-in fixed minimum soft start time and external setting of longer soft start time.

[0006] In order to achieve the above purpose, the utility model provides a support external adjustable and built-in fixed minimum soft start time circuit, which comprises (arbitrary) chip internal system module (SYSTEM), enable end EN, reference current Iref, field effect tube P1-P7 and field effect tube N1-N7, wherein:

[0007] The enable end EN is electrically connected with the gate of the field effect tube P2, and the other end of the enable end is electrically connected with the gate of the field effect tube N3 through the inverter INV1; the drain of the field effect tube P2 is electrically connected with the gate of the field effect tube P1, the gate of the field effect tube P3 and the gate of the field effect tube P4 respectively, and the drain of the field effect tube P1 is grounded through the reference current Iref;

[0008] The drain of the field effect tube P3 is connected with the drain of the field effect tube N6, and the gate of the field effect tube N6 is electrically connected with the gate of the field effect tube N7; the drain of the field effect tube N7 is electrically connected with the source of the field effect tube N5.

[0009] The internal signal vclamp of the internal system module of the chip is electrically connected with the gate of the field effect tube N5 and the drain of the field effect tube N4 respectively, and the gate and the drain of the field effect tube N4 are connected with the compensation capacitor C2; the gate of the field effect tube N4 is electrically connected with the drain of the field effect tube N3, the drain of the field effect tube P7, the drain of the field effect tube P6 and the drain of the field effect tube N2 respectively; the drain of the field effect tube P4 is electrically connected with the source of the field effect tube P5, the source of the field effect tube P6 and the source of the field effect tube P7 respectively; the source of the field effect tube P5 is electrically connected with the drain of the field effect tube N1, and the gate of the field effect tube P5 is electrically connected with the drain of the field effect tube N7; the gate of the field effect tube N1 is electrically connected with the gate of the field effect tube N2; the gate of the field effect tube P7 is connected with the built-in soft start voltage signal SS_INNER, and the gate of the field effect tube P6 is connected with the external soft start voltage signal SS_OUT.

[0010] As a further preferred technical solution of the above technical solution, the gate of the field effect tube P1 is electrically connected with the drain, and the gate of the field effect tube P1 is also connected with the filter capacitor C1.

[0011] As a further preferred technical solution of the above technical solution, the gate of the field effect tube N6 is electrically connected with the drain, and the gate of the field effect tube N1 is electrically connected with the drain.

[0012] As a further preferred technical solution of the above technical solution, the source of the field effect tube N1, the source of the field effect tube N2, the source of the field effect tube N3, the source of the field effect tube N4, the source of the field effect tube N6 and the source of the field effect tube N7 are all grounded.

[0013] As a further preferred technical solution of the above technical solution, the internal signal vclamp is an output voltage. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 It is the support external adjustable and built-in fixed minimum soft start time circuit diagram of the utility model.

[0015] Figure 2 is the built-in soft start time circuit diagram of the utility model.

[0016] Figure 3 is the external soft start time circuit diagram of the utility model. DETAILED DESCRIPTION

[0017] The following description is provided to enable any person skilled in the art to practice the present application. The preferred embodiments described herein are only examples of the present application and various modifications can be made by those skilled in the art without departing from the spirit and scope of the present application. The basic principles defined in the following description can be applied to other embodiments, variations, improvements, equivalents and other technical solutions without departing from the spirit and scope of the present application.

[0018] The utility model discloses a kind of support external adjustable and built-in fixed minimum soft start time circuit, the following is further described with preferred embodiment to the specific embodiment of utility model.

[0019] In the embodiment of the utility model, those skilled in the art should note that the chip internal system module etc.

[0020] Preferred embodiment.

[0021] The utility model is applied to all the power chip involving needing soft start time.

[0022] As Figure 3 As shown in the utility model discloses a kind of support external adjustable and built-in fixed minimum soft start time circuit, including (arbitrary) chip internal system module (SYSTEM), enable end EN, reference current Iref, field effect tube P1-P7 and field effect tube N1-N7, wherein:

[0023] Enable end EN is electrically connected with the gate of field effect tube P2 and another way of enable end is electrically connected with the gate of field effect tube N3 by reverser INV1;The drain of field effect tube P2 is electrically connected with the gate of field effect tube P1, the gate of field effect tube P3 and the gate of field effect tube P4 respectively, and the drain of field effect tube P1 is grounded by reference current Iref;

[0024] The drain of field effect tube P3 is connected with the drain of field effect tube N6 and the gate of field effect tube N6 is electrically connected with the gate of field effect tube N7, and the drain of field effect tube N7 is electrically connected with the source of field effect tube N5;

[0025] The internal signal vclamp of the chip internal system module is electrically connected with the gate of the field effect tube N5 and the drain of the field effect tube N4 respectively, and a compensation capacitor C2 is connected between the gate and the drain of the field effect tube N4, the gate of the field effect tube N4 is electrically connected with the drain of the field effect tube N3, the drain of the field effect tube P7, the drain of the field effect tube P6 and the drain of the field effect tube N2 respectively, and the drain of the field effect tube P4 is electrically connected with the source of the field effect tube P5, the source of the field effect tube P6 and the source of the field effect tube P7 respectively; the source of the field effect tube P5 is electrically connected with the drain of the field effect tube N1, and the gate of the field effect tube P5 is electrically connected with the drain of the field effect tube N7, the gate of the field effect tube N1 is electrically connected with the gate of the field effect tube N2; the gate of the field effect tube P7 is connected with an inner built-in soft start voltage signal SS_INNER, and the gate of the field effect tube P6 is connected with an outer built-in soft start voltage signal SS_OUT.

[0026] Specifically, the gate of the field effect tube P1 is electrically connected with the drain, and the gate of the field effect tube P1 is also connected with a filter capacitor C1.

[0027] More specifically, the gate of the field effect tube N6 is electrically connected with the drain, and the gate of the field effect tube N1 is electrically connected with the drain.

[0028] Further, the source of the field effect tube N1, the source of the field effect tube N2, the source of the field effect tube N3, the source of the field effect tube N4, the source of the field effect tube N6 and the source of the field effect tube N7 are all grounded.

[0029] Further, the internal signal vclamp is used as an output voltage.

[0030] In order to better understand the circuit of the utility model, first, the external adjustable and built-in fixed minimum soft start time circuit is split into a built-in soft start time circuit for charging (as shown in Figure 1 ) and an external soft start time circuit for charging (as shown in Figure 2 ), wherein:

[0031] As shown in Figure 1 , P1-P7 are PMOS, N1-N7 are NMOS, C1-C3 are filter capacitors, Cssin is a built-in charging capacitor, R1 is a resistor, INV1-INV4 are inverters, and Iref is a reference current.

[0032] In order to better understand the circuit design, the parameters and proportions of important devices are set, Iref=1uA, P1:P3:P6=40:1:20, N1:N2=1:12, N5:N6=1:1, and the actual parameters and proportions can be adjusted.

[0033] When the chip is not enabled, the circuit is disabled, EN is low, ENB is high, P2 is on, the gate of P1, P3, P4 is pulled high, so P1, P3, P4 are off, the gate of N3 is pulled high, N3 is on, the upper plate of Cssin is pulled to ground, the gate of N7 is pulled high, N7 is on, SS_INNER is pulled to ground, P6 gate is pulled high and off through INV2-INV4.

[0034] When the chip is enabled, the circuit is enabled at the same time, EN is high, ENB is low, P2, N3, N7 are all released, Iref current flows through P1, through P3, P4 current mirror, Cssin upper plate slowly rises from 0V, and SS_INNER is initially low, then P5 is also on, with P4 on mirror current flowing through N6, then mirror to N5, so the path of R1-N4-N5 is also generated, SS_INNER is released from low level, and since the current of N5 is determined, N4 Vgs naturally remains stable, SS_INNER slowly rises with the upper plate of Cssin. When SS_INNER rises to a certain threshold, INV2-IN3 flips, making P5 gate pull high and off, then N5 current disappears, SS_INNER is pulled high quickly because there is no pull-down current mirror, at the same time, P5 gate is pulled high, P6 is on through INV4, so P6, P7, N7 form a clocked inverter, P6 is the clocked signal, P6, P7 are on, N7 is off, and finally SS_INNER is pulled to the power supply voltage.

[0035] Due to the limited internal chip area, a small current is generally used to charge a large capacitor, according to the previously set parameters, Iref = 1uA, according to the proportional conversion, the current flowing through P3 is 1uA / 40 = 25nA, and this current is still relatively large, a large Cssin is needed to get a long enough charging time, and this charging time represents the length of the soft start time. Therefore, N1, N2 form a current mirror, the total current flowing through N1, N2 is 25nA, and N1:N2 = 1:12, the current flowing through N1 is only 1 / 13, about 2nA, so the charging current of Cssin is only 2nA, so the charging time is the same, Cssin can be further reduced, generally in the pF level. The above is the basic structure of the built-in soft start circuit.

[0036] As Figure 2As shown, the external soft-start circuit uses a single current source to charge the external Css. The slow rise of the upper plate of Css represents the soft-start time. Since the external Css can be very large, in the nF range or even larger, the external charging current does not need to be set very small. P1-P3 are PMOS transistors, N1 is an NMOS transistor, C1 is a filter capacitor, INV1 is an inverter, and Iref is the internal reference current. Because SS_OUT is a chip port, and the charging time is set externally by adding Cssout, this open port requires internal ESD protection.

[0037] When the circuit is not enabled, EN is low and ENB is high, so P2 and N1 are turned on, P1 and P3 are turned off, and ss_out is pulled to ground.

[0038] When the circuit is enabled, EN goes high and ENB goes low, ss_out is released, Iref is mirrored by the current mirrors of P1 and P3, and the current flowing through P3 charges Cssout, causing ss_out to rise slowly, which also represents the soft-start time. The charging current here can be relatively large, for example, Iref = 1uA, P1:P3 = 1:1, that is, the charging current is also 1uA.

[0039] The above describes the soft-start time circuit structure for both built-in and external charging circuits. Next, the SS_INNER and SS_OUT signals need to be combined. When there is no external port, SS_INNER determines the soft-start time, i.e., the built-in fixed minimum soft-start time. When an SS_OUT port exists, the soft-start time can also be set by connecting an external Cssout to ground. If the designed startup time of the external Cssout is less than the built-in startup time, then the entire startup time is determined by the built-in time. If the designed startup time of the external Cssout is greater than the built-in startup time, then the entire startup time is determined by the external time, ensuring better reliability.

[0040] Therefore, as Figure 3 As shown, P1-P7 are PMOS transistors, N1-N7 are NMOS transistors, C1 is a filter capacitor, C2 is a compensation capacitor, INV1 is an inverter, and SYSTEM refers to any internal system module of the chip. Its internal signal vclamp is an inductor current signal that controls the switching of the power transistor, or a control signal that controls the output voltage. Taking a boost DC-DC converter as an example, this SYSTEM can be the error amplifier in a switching power supply, and vclamp is the output signal VCOMP of the error amplifier, which can control the change in inductor current. Similarly, vclamp can also be the reference voltage signal of the error amplifier; a slowly rising vclamp indicates a slowly rising output voltage.

[0041] The specific implementation process is as follows:

[0042] SS_OUT and SS_INNER will each slope up because of different charging rates, but the above circuit as a whole constitutes a negative feedback operational amplifier, vclamp as the output voltage, after N5 Vgs (voltage between the gate and the source) returns to the gate of P5, according to the virtual short characteristics, so vclamp-vgs = min (SS_OUT, SS_INNER), that is, vclamp = min (SS_OUT, SS_INNER) + Vgs. It is obvious that vclamp is clamped by the lowest voltage of SS_OUT and SS_INNER, thereby realizing the built-in fixed soft start time and adjustable external soft start time.

[0043] If two charging circuits are directly combined, for example, the charging circuit only uses the internal soft start circuit, and only needs to be connected in parallel with an external large capacitor through an external port when needed, it is feasible in principle, but in practice, because the port needs to be opened to connect the large capacitor, the SS_INNER of the built-in charging circuit needs to be increased ESD, and the charging current of the built-in circuit is only 2nA, which is because of the limitation of the area of the built-in soft start capacitor, so under high temperature conditions, the 2nA current is very small due to process leakage, and in the more common actual situation, the high-temperature leakage is much larger than 2nA, and this part of the leakage is caused by ESD, because the transistor area of ESD is large, the high-temperature leakage will be very obvious, which will cause the loss of soft start function or the chip cannot start.

[0044] In summary, the reasons why the switching power supply or power chip needs soft start are analyzed, some customers want to simplify the periphery and save the external adjustable soft start time port, and ensure the basic reliability by using the built-in fixed soft start time, but in special application situations, customers want external adjustable soft start time to ensure higher reliability, and the above structure can meet the design needs of customers.

[0045] It is worth mentioning that the chip internal system module and other technical features involved in the utility model patent application should be regarded as prior art, the specific structure, working principle and possible control method and spatial arrangement method of these technical features can be selected by using the conventional selection in the field, and should not be regarded as the invention point of the utility model patent, and the utility model patent will not be further expanded and described in detail.

[0046] For those skilled in the art, the technical solutions described in the foregoing embodiments can still be modified, or some technical features can be replaced, and any modification, equivalent replacement, improvement, etc. within the spirit and principles of the utility model should be included in the protection scope of the utility model.

Claims

1. A circuit that supports external adjustment and has a built-in fixed minimum soft-start time, characterized in that, This includes the chip's internal system modules, enable terminal EN, reference current Iref, field-effect transistors P1-P7, and field-effect transistors N1-N7, among which: One enable terminal EN is electrically connected to the gate of field-effect transistor P2, and the other enable terminal is electrically connected to the gate of field-effect transistor N3 through inverter INV1; the drain of field-effect transistor P2 is electrically connected to the gate of field-effect transistor P1, the gate of field-effect transistor P3, and the gate of field-effect transistor P4, respectively; the drain of field-effect transistor P1 is grounded through the reference current Iref. The drain of field-effect transistor P3 is connected to the drain of field-effect transistor N6, and the gate of field-effect transistor N6 is electrically connected to the gate of field-effect transistor N7. The drain of field-effect transistor N7 is electrically connected to the source of field-effect transistor N5. The internal signal vclamp of the chip's internal system module is electrically connected to the gate of MOSFET N5 and the drain of MOSFET N4, respectively. A compensation capacitor C2 is connected between the gate and drain of MOSFET N4. The gate of MOSFET N4 is electrically connected to the drain of MOSFET N3, the drain of MOSFET P7, the drain of MOSFET P6, and the drain of MOSFET N2. The drain of MOSFET P4 is electrically connected to the source of MOSFET P5, the source of MOSFET P6, and the source of MOSFET P7. The source of MOSFET P5 is electrically connected to the drain of MOSFET N1, and the gate of MOSFET P5 is electrically connected to the drain of MOSFET N7. The gate of MOSFET N1 is electrically connected to the gate of MOSFET N2. The gate of MOSFET P7 is connected to the built-in soft-start voltage signal SS_INNER, and the gate of MOSFET P6 is connected to the external soft-start voltage signal SS_OUT.

2. A circuit that supports externally adjustable and internally fixed minimum soft-start time according to claim 1, characterized in that, The gate and drain of the field-effect transistor P1 are electrically connected, and the gate of the field-effect transistor P1 is also connected to the filter capacitor C1.

3. A circuit that supports externally adjustable and internally fixed minimum soft-start time according to claim 2, characterized in that, The gate and drain of field-effect transistor N6 are electrically connected, and the gate and drain of field-effect transistor N1 are electrically connected.

4. A circuit that supports externally adjustable and internally fixed minimum soft-start time according to claim 3, characterized in that, The sources of field-effect transistors N1, N2, N3, N4, N6, and N7 are all grounded.

5. A circuit that supports externally adjustable and internally fixed minimum soft-start time according to claim 4, characterized in that, The internal signal vclamp serves as the output voltage.

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