A low power bandgap reference current source circuit and control method

Abstract

The application discloses a low-power bandgap reference current source circuit and a control method, and the circuit comprises a current mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; the current mode bandgap circuit is internally provided with an error amplifier OPAMP and a proportional resistance network; the error amplifier input stage circuit is a PMOS pair tube input stage circuit; the threshold modulation circuit is a source-liner forward bias threshold modulation circuit, which is used for forward biasing the threshold voltage of all PMOS tubes in the low-power bandgap reference current source circuit and enabling the NMOS tube connected with the error amplifier OPAMP output stage to work in a saturation region; and the current mirror circuit is a series diode compensation method current mirror circuit structure. The application is compatible with a standard CMOS process, realizes sub-1V low voltage, micro-nano ampere level low power consumption, high-precision low-noise small area effect, solves various technical pain points of a traditional scheme, and has excellent application prospects in a wearable device power management system.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power bandgap reference current source circuit and control method. Background Technology

[0002] Currently, the extreme demand for battery life in wearable devices is driving their power systems into the era of "microamps" or even "nanoamps". The traditional power supply solution that uses a 1.2V classic bandgap reference with a low dropout linear regulator is no longer suitable for the low-voltage operation requirements of devices below 1V, exposing many technical pain points, including the disappearance of operating voltage margin, prominent power consumption bottlenecks, and the existence of noise-power paradox.

[0003] To address these issues, the "gapless" low-power solutions emerging in the industry, while reducing current to the 10nA level, suffer from large process angle drift, high temperature coefficient, and an accuracy of only ±3%, failing to meet the 0.5% reference accuracy requirement of a 12-bit ADC for medical-grade sensors. Conventional sub-1V bandgap solutions, while achieving low-voltage operation, rely on low-threshold devices or BiCMOS processes, increasing process costs. Furthermore, they exhibit high op-amp bias current, high output noise, and require complex three-branch current mirrors, resulting in large layout areas, which contradicts the SiP integration requirements of wearable chips. Bandgap reference op-amps with input transistors directly connected to the top node of the source-substrate junction result in a large input common-mode voltage, easily causing the op-amp to enter the linear region, affecting the circuit's power supply rejection ratio, and limiting further reduction in operating voltage. Traditional current mirror circuits are affected by threshold mismatch and the Early effect, leading to large current replication errors and further reducing the accuracy of the reference output. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a low-power bandgap reference current source circuit and control method that is compatible with standard CMOS technology, achieves sub-1V low voltage, micro-nano ampere-level low power consumption, high precision, low noise and small area, solves various technical pain points of traditional solutions, and has excellent prospects for application in power management systems of wearable devices.

[0005] This invention provides a low-power bandgap reference current source circuit, which includes a current-mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit, and a current mirror circuit.

[0006] The current-mode bandgap circuit has an built-in error amplifier OPAMP and a proportional resistor network. The input stage of the error amplifier OPAMP is connected to the input stage circuit of the error amplifier. The proportional resistor network is used to divide the reference voltage to the sub-1V level. The error amplifier input stage circuit is a PMOS transistor input stage circuit. The threshold modulation circuit is a source-substrate forward bias threshold modulation circuit. The threshold modulation circuit is used to forward bias the threshold voltage of all PMOS transistors in the low-power bandgap reference current source circuit and to make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. The current mirror circuit is a series diode compensation current mirror circuit structure, and several MOS transistors of the same size are connected in series in the current mirror circuit.

[0007] Furthermore, the current-mode bandgap circuit includes an error amplifier OPAMP, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2A1, a third resistor R2A2, a fourth resistor R2B1, a fifth resistor R2B2, a tenth resistor R7, a twentieth PMOS transistor PM20, a twenty-first PMOS transistor PM21, and a twenty-second PMOS transistor PM22. The base and collector of the first transistor Q1 are grounded, and the emitter of the first transistor Q1 is connected to node N4 and to the drain of the twentieth PMOS transistor PM20. The base and collector of the second transistor Q2 are grounded, and the emitter of the second transistor Q2 is connected to the MINUS terminal of the first resistor R1; The drain of the twentieth PMOS transistor PM20 is connected to the PLUS terminal of the second resistor R2A1; The drain of the 21st PMOS transistor PM21 is also connected to the PLUS terminal of the first resistor R1 and the PLUS terminal of the fourth resistor R2B1. The non-inverting input of the error amplifier OPAMP is connected to node N1, and is also connected to the MINUS terminal of the fourth resistor R2B1 and the PLUS terminal of the fifth resistor R2B2. The inverting input of the error amplifier OPAMP is connected to node N2, and is also connected to the MINUS terminal of the second resistor R2A1 and the PLUS terminal of the third resistor R2A2. The output of the error amplifier OPAMP is connected to the gate of the twentieth PMOS transistor PM20, the gate of the twentieth PMOS transistor PM21, and the gate of the twentieth PMOS transistor PM22.

[0008] Furthermore, the input stage of the error amplifier OPAMP uses a pair of PMOS transistors. The input stage circuit of the error amplifier includes the twentieth PMOS transistor PM20, the twenty-first PMOS transistor PM21, the twenty-third PMOS transistor PM23, the twenty-fourth PMOS transistor PM24, the twenty-fifth PMOS transistor PM25, the twenty-sixth PMOS transistor PM26, the twenty-seventh PMOS transistor PM27, the twenty-eighth PMOS transistor PM28, the first transistor Q1, the second transistor Q2, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, the first resistor R1, the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2. The gate of the 23rd PMOS transistor PM23 is connected to a bias voltage vbp1, and the gate of the 24th PMOS transistor PM24 is connected to a bias voltage vbp2. The 23rd PMOS transistor PM23 and the 24th PMOS transistor PM24 form the tail current source of the input stage of the error amplifier OPAMP. The 25th PMOS transistor PM25 and the 26th PMOS transistor PM26 serve as the input pair of the error amplifier OPAMP. The gate of the 25th PMOS transistor PM25 is connected to node N1 of the current-mode bandgap circuit, and the gate of the 26th PMOS transistor PM26 is connected to node N2 of the current-mode bandgap circuit. The 25th PMOS transistor PM25 and the 6th NMOS transistor NM6, as well as the 26th PMOS transistor PM26 and the 7th NMOS transistor NM7, form a folded common-source common-gate pair. The gates of the 6th NMOS transistor NM6 and the 7th NMOS transistor NM7 are connected to a bias voltage vbn1. The 27th PMOS transistor PM27 and the 28th PMOS transistor PM28 form a common-source cascode current mirror load; The gates of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are connected to a bias voltage vbn2.

[0009] Furthermore, the proportional resistor network is composed of the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2. The proportional resistor network scales the reference voltage downward by setting the voltage division ratio. The current-mode bandgap circuit generates a PTAT+CTAT current through the current mirror circuit and injects it into the tenth resistor R7. The voltage value after voltage division is taken at the output terminal of the current-mode bandgap circuit.

[0010] Furthermore, the threshold modulation circuit includes a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, an eleventh resistor R8, a twenty-ninth PMOS transistor PM29, and a thirtieth PMOS transistor PM30. The gate and drain of the twelfth NMOS transistor NM12 are shorted and connected to the bias current ic, and are also connected to the gate of the thirteenth NMOS transistor NM13 and the gate of the fourteenth NMOS transistor NM14. The drain of the thirteenth NMOS transistor NM13 is connected to the MINUS terminal of the eleventh resistor R8 via the output node vb. The gate and drain of the thirtieth PMOS transistor PM30 are shorted together, and the gate of the twenty-ninth PMOS transistor PM29 and the drain of the fourteenth NMOS transistor NM14 are connected together, and the bias voltage vbp2 is connected to it.

[0011] Furthermore, the current mirror circuit includes an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a nineteenth NMOS transistor NM19, and a twentieth NMOS transistor NM20. The gate of the nineteenth NMOS transistor NM19 is connected to the gate of the twentieth NMOS transistor NM20, and the source of the nineteenth NMOS transistor NM19 is connected to the drain of the twentieth NMOS transistor NM20. The source of the tenth NMOS transistor NM10 is connected to the drain of the eighth NMOS transistor NM8, and the gate of the tenth NMOS transistor NM10 is connected to the gate of the eighth NMOS transistor NM8. The source of the eleventh NMOS transistor NM11 is connected to the drain of the ninth NMOS transistor NM9, and the gate of the eleventh NMOS transistor NM11 is connected to the gate of the ninth NMOS transistor NM9, and is also connected to the gate of the nineteenth NMOS transistor NM19, the gate of the twentieth NMOS transistor NM20, the gate of the tenth NMOS transistor NM10, and the gate of the eighth NMOS transistor NM8.

[0012] Furthermore, the low-power bandgap reference current source also includes a startup circuit, which is used to inject startup current into the input stage of the error amplifier OPAMP, so that the current-mode bandgap circuit is taken out of the zero-current state.

[0013] Furthermore, the low-power bandgap reference current source also includes a cascode current mirror circuit, which is used to improve the output impedance and current replication accuracy of the low-power bandgap reference current source circuit.

[0014] Furthermore, a capacitor C1 is provided between the output terminal of the error amplifier OPAMP and the power supply VDD. The capacitor C1 is used to increase the bandwidth of the low-power bandgap reference current source circuit.

[0015] The present invention also provides a control method for a low-power bandgap reference current source circuit, the control method being implemented based on the aforementioned low-power bandgap reference current source circuit, the control method comprising: Start-up phase: Start-up current is injected into the input stage of the error amplifier OPAMP through the start-up circuit, causing the current-mode bandgap circuit to leave the zero-current state and complete the power-on start-up. Steady-state operation phase: The error amplifier OPAMP clamps the potentials of nodes N1 and N2 in the current-mode bandgap circuit to be equal, generating a temperature-compensated PTAT+CTAT current, which is then divided by the proportional resistor network to output a sub-1V reference voltage. Substrate modulation stage: The threshold modulation circuit generates a substrate bias voltage, which is applied to the source-substrate junction of the PMOS transistor in the low-power bandgap reference current source circuit to achieve forward bias, reduce the threshold voltage of the PMOS transistor, and make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. Current mirror compensation stage: The current mirror circuit compensates for the mirror current in the low-power bandgap reference current source circuit.

[0016] This invention provides a low-power reference current source circuit and control method. It achieves a sub-1V reference voltage output by setting a proportional resistor network, eliminating the need for low-threshold devices or BiCMOS technology, while remaining compatible with standard CMOS technology. This eliminates the voltage margin loss problem of traditional solutions. The total current of its core and bias circuits reaches the nanoamp level, overcoming the power consumption bottleneck. The PMOS pair input stage circuit combined with a source-substrate forward bias threshold modulation circuit restores the operational amplifier's high gain, solving the problems of poor linearity and power supply rejection ratio caused by excessive common-mode voltage at the operational amplifier input. The circuit output accuracy meets requirements, overcoming the large drift and low accuracy defects of "bandgap-free" solutions. The series diode compensation current mirror circuit effectively suppresses threshold mismatch and the Early effect, reducing current replication error and improving reference output accuracy. Furthermore, the circuit eliminates the need for a complex three-branch current mirror, resulting in a small layout area, which is suitable for wearable chip SiP. It integrates various requirements and breaks the noise-power paradox, solving the problems of high bias current and high output noise of conventional sub-1V bandgap op-amp solutions. It achieves comprehensive technical effects of sub-1V low voltage, microamp / nanoamp level low power consumption, high precision, low noise, and small area, and has excellent prospects for application in power management systems for wearable devices. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the low-power bandgap reference current source circuit module in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the low-power bandgap reference current source circuit in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the current-mode bandgap circuit in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the error amplifier input stage circuit in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the threshold modulation circuit in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the current mirror circuit in Embodiment 1 of the present invention; Figure 7 This is a flowchart of the control method for the low-power bandgap reference current source circuit in Embodiment 2 of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In this invention, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of features, figures, steps, behaviors, components, portions or combinations thereof disclosed in this specification, and are not intended to exclude the possibility that one or more other features, figures, steps, behaviors, components, portions or combinations thereof are present or added.

[0021] It should also be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0022] In wearable device power systems, traditional bandgap reference circuits face multiple technical challenges when the operating voltage drops to sub-1V. Firstly, the direct connection of the error amplifier input pair to the top node of the source-substrate junction leads to a high input common-mode voltage, making the operational amplifier prone to entering the linear operating region and thus reducing its power supply rejection ratio (PSRR). Secondly, the current mirror circuit is affected by MOSFET threshold voltage mismatch and the Early effect, resulting in increased current replication error and insufficient reference output accuracy, failing to meet the reference accuracy requirements of medical-grade sensors. Furthermore, conventional sub-1V solutions rely on low-threshold devices or BiCMOS processes, increasing process complexity and cost, which contradicts the system-in-package (SoC) integration requirements of wearable chips.

[0023] Specifically, in wearable medical monitoring devices with integrated analog-to-digital converters, the sensor module requires a stable and reliable sub-1V reference voltage to ensure data acquisition quality. Specifically, when the device operates in a low-power state, the power supply voltage drops to the sub-1V range. The input stage of the error amplifier in a traditional bandgap reference circuit cannot maintain saturation due to excessively high common-mode voltage, causing fluctuations in the output reference voltage. Simultaneously, the replication error of the current mirror leads to reference current deviation, reducing the conversion accuracy of the analog-to-digital converter and affecting the reliability of physiological parameter monitoring.

[0024] Instability in the reference voltage will directly lead to sensor data distortion, failing to meet the standards for medical-grade applications. Consequently, the system may frequently trigger anomaly handling mechanisms, reducing overall reliability. Furthermore, process-dependent solutions are difficult to adapt to advanced CMOS process nodes, hindering the evolution of wearable devices towards smaller sizes and lower power consumption.

[0025] Example 1 Embodiment 1 of the present invention provides a low-power bandgap reference current source circuit, the low-power bandgap reference current source circuit including a current-mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit and a current mirror circuit; The current-mode bandgap circuit has an built-in error amplifier OPAMP and a proportional resistor network. The input stage of the error amplifier OPAMP is connected to the input stage circuit of the error amplifier. The proportional resistor network is used to divide the reference voltage to the sub-1V level. The error amplifier input stage circuit is a PMOS transistor input stage circuit. The threshold modulation circuit is a source-substrate forward bias threshold modulation circuit. The threshold modulation circuit is used to forward bias the threshold voltage of all PMOS transistors in the low-power bandgap reference current source circuit and to make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. The current mirror circuit is a series diode compensation current mirror circuit structure, and several MOS transistors of the same size are connected in series in the current mirror circuit.

[0026] In one optional implementation of this embodiment, such as Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of a low-power bandgap reference current source circuit module according to Embodiment 1 of the present invention is shown. Figure 2 A schematic diagram of a low-power bandgap reference current source circuit according to Embodiment 1 of the present invention is shown. The low-power bandgap reference current source circuit includes a current-mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit, and a current mirror circuit.

[0027] In an optional implementation of this embodiment, the current-mode bandgap circuit incorporates an error amplifier OPAMP and a proportional resistor network. The input stage of the error amplifier OPAMP is connected to the input stage circuit of the error amplifier, and the proportional resistor network is used to divide the reference voltage to a sub-1V level.

[0028] Specifically, such as Figure 3 As shown, Figure 3 The diagram shows a schematic of the current-mode bandgap circuit in Embodiment 1 of the present invention. The current-mode bandgap circuit includes an error amplifier OPAMP, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2A1, a third resistor R2A2, a fourth resistor R2B1, a fifth resistor R2B2, a tenth resistor R7, a twentieth PMOS transistor PM20, a twenty-first PMOS transistor PM21, and a twenty-second PMOS transistor PM22. The base and collector of the first transistor Q1 are grounded, and the emitter of the first transistor Q1 is connected to node N4 and to the drain of the twentieth PMOS transistor PM20. The base and collector of the second transistor Q2 are grounded, and the emitter of the second transistor Q2 is connected to the MINUS terminal of the first resistor R1; The drain of the twentieth PMOS transistor PM20 is connected to the PLUS terminal of the second resistor R2A1; The drain of the 21st PMOS transistor PM21 is also connected to the PLUS terminal of the first resistor R1 and the PLUS terminal of the fourth resistor R2B1. The non-inverting input of the error amplifier OPAMP is connected to node N1, and is also connected to the MINUS terminal of the fourth resistor R2B1 and the PLUS terminal of the fifth resistor R2B2. The inverting input of the error amplifier OPAMP is connected to node N2, and is also connected to the MINUS terminal of the second resistor R2A1 and the PLUS terminal of the third resistor R2A2. The output of the error amplifier OPAMP is connected to the gate of the twentieth PMOS transistor PM20, the gate of the twentieth PMOS transistor PM21, and the gate of the twentieth PMOS transistor PM22.

[0029] Furthermore, the proportional resistor network is composed of the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2. The proportional resistor network scales the reference voltage downward by setting the voltage division ratio. The current-mode bandgap circuit generates a PTAT+CTAT current through the current mirror circuit and injects it into the tenth resistor R7. The voltage value after voltage division is taken at the output terminal of the current-mode bandgap circuit.

[0030] Specifically, in traditional bandgap circuits, the input stage of an operational amplifier is connected to, as follows: Figure 3 In the current-mode bandgap circuit shown, nodes N3 and N4 have the same voltage V3 as node N4 due to the "virtual short" characteristic of the operational amplifier. Therefore, when R2A1 = R2B1 and R2A2 = R2B2, according to the loop current generation principle of the bandgap reference circuit, the expression for the current I generated by the loop formed by the first transistor Q1, the second transistor Q2, the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2 is:

[0031] In the formula, This is the difference between the emitter-base voltages of the first transistor Q1 and the second transistor Q2. , Thermoelectric voltage, The emitter area ratio, The resistance value of the first resistor R1.

[0032] The current I is injected through a current mirror consisting of the twentieth PMOS transistor PM20, the twenty-first PMOS transistor PM21, and the twenty-second PMOS transistor PM22. Therefore, the magnitude of the voltage V input to the op-amp input is:

[0033] When the voltage V input to the op-amp is not low enough, the MOS transistor at the upper end of the op-amp input stage will be pushed into the linear region, causing the op-amp, which acts as an error amplifier, to not operate in its normal state. The power supply rejection ratio of the entire bandgap reference circuit will be affected. At the same time, a large input voltage V will force the circuit's operating voltage to fail to meet the current wearable device's requirement for low operating voltage.

[0034] Therefore, in this embodiment, a voltage divider sampling resistor is inserted into the current-mode bandgap circuit to form a proportional resistor network. The input terminal of the error amplifier OPAMP is no longer directly connected to the top of the BE junction of the first transistor Q1 and the second transistor Q2, but is connected to resistor tap nodes N1 and N2. By setting the voltage division ratio k, Scale the reference voltage down:

[0035] When k=0.48, =603mV, achieving a "sub-1V" reference voltage output. Through a current mirror composed of the twentieth PMOS transistor PM20, the twenty-first PMOS transistor PM21, and the twenty-second PMOS transistor PM22, the PTAT+CTAT current is injected into the tenth resistor R7, generating a temperature-independent voltage. Because the error amplifier OMAPM clamps the voltages of nodes N1 and N2, nodes N1 and N2 are forced to be at the same potential by the op-amp, the currents in the two branches are equal, locking in the temperature offset, and R2B1 / R2B2 and R2A1 / R2A2 form a proportional voltage divider, making... Only a portion appears at the output. When the process angle or temperature changes, I and R drift in the same direction. The voltage division ratio k is composed of resistors of the same material, which cancels each other out in the first order. By correcting k with a mask, the output voltage value can be compressed, and the temperature coefficient remains constant, ensuring that the temperature drift remains basically unchanged.

[0036] In an optional implementation of this embodiment, the error amplifier input stage circuit is a PMOS transistor input stage circuit.

[0037] Specifically, such as Figure 4 As shown, Figure 4 The diagram shows a schematic of the input stage circuit of the error amplifier in Embodiment 1 of the present invention. The input stage of the error amplifier OPAMP uses a pair of PMOS transistors. The input stage circuit of the error amplifier includes the twentieth PMOS transistor PM20, the twenty-first PMOS transistor PM21, the twenty-third PMOS transistor PM23, the twenty-fourth PMOS transistor PM24, the twenty-fifth PMOS transistor PM25, the twenty-sixth PMOS transistor PM26, the twenty-seventh PMOS transistor PM27, the twenty-eighth PMOS transistor PM28, the first transistor Q1, the second transistor Q2, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, the first resistor R1, the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2. The gate of the 23rd PMOS transistor PM23 is connected to a bias voltage vbp1, and the gate of the 24th PMOS transistor PM24 is connected to a bias voltage vbp2. The 23rd PMOS transistor PM23 and the 24th PMOS transistor PM24 form the tail current source of the input stage of the error amplifier OPAMP. The 25th PMOS transistor PM25 and the 26th PMOS transistor PM26 serve as the input pair of the error amplifier OPAMP. The gate of the 25th PMOS transistor PM25 is connected to node N1 of the current-mode bandgap circuit, and the gate of the 26th PMOS transistor PM26 is connected to node N2 of the current-mode bandgap circuit. The 25th PMOS transistor PM25 and the 6th NMOS transistor NM6, as well as the 26th PMOS transistor PM26 and the 7th NMOS transistor NM7, form a folded common-source common-gate pair. The gates of the 6th NMOS transistor NM6 and the 7th NMOS transistor NM7 are connected to a bias voltage vbn1. The 27th PMOS transistor PM27 and the 28th PMOS transistor PM28 form a common-source cascode current mirror load; The gates of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are connected to a bias voltage vbn2.

[0038] Furthermore, in this embodiment, a PMOS pair is used as the input stage of the error amplifier OPAMP to replace the NMOS transistor in the traditional solution. The reason is that there is a fundamental conflict between the threshold voltage of the standard NMOS transistor and the voltage (VEB) generated by the bandgap core under low-voltage (1V) power supply. The PMOS combined with the resistor voltage division technology can solve this problem and achieve sub-1V operation without low-threshold devices. For the NMOS input differential pair, its conduction condition is that the NMOS gate-source voltage needs to satisfy VGS > Vthn + VDS(sat). For the input common-mode voltage limit, to make the input pair transistors operate in the saturation region, the minimum input common-mode voltage of the amplifier must be less than VEB(on), that is, it must satisfy: Vthn + 2VDS(sat) < VEB(on). Regarding the requirement for the threshold voltage, assuming VEB(on) = 0.7 V and VDS(sat) = 50 mV, then Vthn < 0.5 V is required; in the standard CMOS process, Vthn is usually 0.7V - 0.9V, which is much greater than 0.5V; therefore, low-threshold NMOS, that is, NMOS transistors with Vthn < 0.5 V or native NMOS transistors must be used. These devices are not generally provided by the standard process and require additional process steps or masks. At the same time, even if low-threshold NMOS is used, there are still temperature reliability problems. The temperature coefficient of VEB is about -2 mV / K, while the absolute value of the temperature coefficient of the NMOS threshold voltage is usually greater than 2 mV / K. At high temperatures, the Vthn of the NMOS transistor drops significantly, possibly below the threshold required for the normal operation of the circuit, resulting in the failure of the reference circuit.

[0039] Therefore, in this embodiment, high-threshold PMOS is used, without intrinsic NMOS, low Vth options or BICMOS, and cold start can be achieved.

[0040] In an alternative implementation of this embodiment, the threshold modulation circuit is a source-substrate forward-biased threshold modulation circuit. The threshold modulation circuit is used to forward-bias the threshold voltages of all PMOS transistors in the low-power bandgap reference current source circuit and make the NMOS transistor connected to the output stage of the error amplifier OPAMP operate in the saturation region.

[0041] Specifically, as Figure 5 shown, Figure 5 Fig. shows the schematic diagram of the principle of the threshold modulation circuit in Embodiment 1 of the present invention. The threshold modulation circuit includes the twelfth NMOS transistor NM12, the thirteenth NMOS transistor NM13, the fourteenth NMOS transistor NM14, the eleventh resistor R8, the twenty-ninth PMOS transistor PM29, and the thirtieth PMOS transistor PM30; The gate and drain of the twelfth NMOS transistor NM12 are shorted and connected to the bias current ic, and are also connected to the gate of the thirteenth NMOS transistor NM13 and the gate of the fourteenth NMOS transistor NM14. The drain of the thirteenth NMOS transistor NM13 is connected to the MINUS terminal of the eleventh resistor R8 via the output node vb. The gate and drain of the thirtieth PMOS transistor PM30 are shorted together, and the gate of the twenty-ninth PMOS transistor PM29 and the drain of the fourteenth NMOS transistor NM14 are connected together, and the bias voltage vbp2 is connected to it.

[0042] Furthermore, the core components of the threshold modulation circuit are the eleventh resistor R8 and the thirteenth NMOS transistor NM13 connected in series. By drawing bias current from NM13, a voltage drop vb is generated across R8, and then vb is connected to the substrate (N-well) of all PMOS transistors to achieve source-substrate forward bias.

[0043] Furthermore, the known threshold voltage The formula is:

[0044] In the formula, The threshold voltage at zero bias source-substrate voltage. The body effect coefficient, For Fermi potential, This is the source-substrate voltage.

[0045] As can be seen from the formula, when vb > 0, the key is to apply a positive bias. A negative value reduces the difference in the square root terms, ultimately lowering the threshold voltage. .

[0046] After the threshold voltage is reduced, the gate-source voltage of the PMOS transistor decreases, and the output node voltage of the error amplifier shifts from near ground potential to the high-gain region. The NMOS transistor connected to the output stage can then operate in the saturation region, restoring the high-gain characteristics of the error amplifier. In this embodiment, by adding a self-biased branch outside the reference core, the NM13 transistor mirrors the PTAT current I, which flows through resistor R8 to generate vb. This vb is simultaneously applied to the source-substrate junction of all common-source PMOS current mirrors, thereby forming a forward bias.

[0047] It should be noted that the current through NM13 exhibits PTAT characteristics, but the current injected into R8 is relatively small compared to the main bias current. Therefore, vb is approximately temperature independent and only decreases slightly with temperature. The maximum forward bias voltage must be strictly limited to within 0.3V to prevent the parasitic PN junction between the P-type substrate and the N-well from conducting (avoiding latch-up effects).

[0048] In an optional implementation of this embodiment, the current mirror circuit is a series diode compensation current mirror circuit structure, in which several MOS transistors of the same size are connected in series.

[0049] Specifically, such as Figure 6 As shown, Figure 6 The schematic diagram of the current mirror circuit in Embodiment 1 of the present invention is shown. The current mirror circuit includes an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a nineteenth NMOS transistor NM19, and a twentieth NMOS transistor NM20. The gate of the nineteenth NMOS transistor NM19 is connected to the gate of the twentieth NMOS transistor NM20, and the source of the nineteenth NMOS transistor NM19 is connected to the drain of the twentieth NMOS transistor NM20. The source of the tenth NMOS transistor NM10 is connected to the drain of the eighth NMOS transistor NM8, and the gate of the tenth NMOS transistor NM10 is connected to the gate of the eighth NMOS transistor NM8. The source of the eleventh NMOS transistor NM11 is connected to the drain of the ninth NMOS transistor NM9, and the gate of the eleventh NMOS transistor NM11 is connected to the gate of the ninth NMOS transistor NM9, and is also connected to the gate of the nineteenth NMOS transistor NM19, the gate of the twentieth NMOS transistor NM20, the gate of the tenth NMOS transistor NM10, and the gate of the eighth NMOS transistor NM8.

[0050] Furthermore, the current mirror circuit adopts a series diode compensation structure, that is, a series diode is introduced on the basis of the original standard current mirror branch to offset the current replication error caused by transistor base-emitter voltage (VEB) mismatch and Early effect.

[0051] like Figure 6 As shown, NMOS transistors with the same width-to-length ratio, namely NM8, NM9, and NM20, are connected in series in the current mirror branches where NM10, NM11, and NM19 are located. This increases the equivalent impedance of the current mirror branch, reduces the influence of the current mirror output voltage change on the current magnitude of the current mirror branch, and thus reduces the output conductance.

[0052] In an optional implementation of this embodiment, the low-power bandgap reference current source further includes a startup circuit, which is used to inject startup current into the input stage of the error amplifier OPAMP, so that the current-mode bandgap circuit is taken out of the zero-current state.

[0053] Specifically, such as Figure 2As shown, the startup circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, as well as resistors R5, R6, R7, NM1, NM2, and transistor Q3.

[0054] In an optional implementation of this embodiment, the low-power bandgap reference current source further includes a cascode current mirror circuit, which is used to improve the output impedance and current replication accuracy of the low-power bandgap reference current source circuit.

[0055] Specifically, such as Figure 2 As shown, PM7, PM8, PM9, PM10, PM11, PM12, PM13, PM14, PM15, PM16, PM17, PM18, and PM19 form a cascode current mirror circuit through a common source and common gate connection. This circuit features high output impedance and high accuracy, effectively overcoming the early effect limitation of simple current mirrors and making current replication more accurate.

[0056] Furthermore, the operating principle of the startup circuit and the cascode current mirror circuit includes: Since the gates of PM1, PM6, and PM7 are all connected to GND, these three transistors are all in the ON state. PM1's ON pulls the gate of NM1 high, activating its branch. Similarly, NM2 and NM3 also activate. PM6's ON pulls the gate voltage of PM2 low, activating its branch. Current is mirrored to the IC node via PM2 and PM3 and input to the op-amp. Similarly, PM4's branch activates, and current is mirrored to the PLUS terminal of R2A1 via PM4 and PM5, raising the voltage at the op-amp's inverting input. This high-level input, after being output from the op-amp's inverting input, outputs a low level at the gate of PM8, activating PM8's branch. This, in turn, raises the gate voltage of PM4, bringing PM4's gate high and forcing PM4's branch to turn off. At this point, the circuit startup ends, and the startup circuit is correspondingly turned off.

[0057] In an optional implementation of this embodiment, a capacitor C1 is provided between the output terminal of the error amplifier OPAMP and the power supply VDD. The capacitor C1 is used to increase the bandwidth of the low-power bandgap reference current source circuit.

[0058] Specifically, capacitor C1 is connected between the op-amp output and VDD to increase the circuit bandwidth. The circuit consisting of PM14-PM17, NM4, and NM5 provides fixed gate voltages for PM9 and PM11 to the cascode current mirror consisting of PM8-PM11.

[0059] In an optional implementation of this embodiment, a capacitor C1 is provided between the output terminal of the error amplifier OPAMP and the power supply VDD. The capacitor C1 is used to increase the bandwidth of the low-power bandgap reference current source circuit.

[0060] In summary, Embodiment 1 of this invention provides a low-power reference current source circuit. It achieves a sub-1V reference voltage output by setting a proportional resistor network, eliminating the need for low-threshold devices or BiCMOS technology, while remaining compatible with standard CMOS technology. This eliminates the voltage margin loss problem of traditional solutions. The total current of its core and bias circuits reaches the nanoamp level, overcoming the power consumption bottleneck. The use of a PMOS transistor input stage circuit combined with a source-substrate forward bias threshold modulation circuit restores the operational amplifier's high gain, solving the problems of poor linearity and power supply rejection ratio caused by excessive common-mode voltage at the operational amplifier input. The circuit output accuracy meets the requirements, overcoming the large drift and low accuracy defects of "bandgap-free" solutions. The series diode compensation current mirror circuit effectively suppresses threshold mismatch and the Early effect, reducing current replication error and improving reference output accuracy. Furthermore, the circuit eliminates the need for a complex three-branch current mirror, resulting in a small layout area, which is suitable for wearable chip SiP. It integrates various requirements and breaks the noise-power paradox, solving the problems of high bias current and high output noise of conventional sub-1V bandgap op-amp solutions. It achieves comprehensive technical effects of sub-1V low voltage, microamp / nanoamp level low power consumption, high precision, low noise, and small area, and has excellent prospects for application in power management systems for wearable devices.

[0061] Example 2 Embodiment 2 of the present invention provides a control method for a low-power bandgap reference current source circuit. The control method is based on the low-power bandgap reference current source circuit in Embodiment 1, and includes: Start-up phase: Start-up current is injected into the input stage of the error amplifier OPAMP through the start-up circuit, causing the current-mode bandgap circuit to leave the zero-current state and complete the power-on start-up. Steady-state operation phase: The error amplifier OPAMP clamps the potentials of nodes N1 and N2 in the current-mode bandgap circuit to be equal, generating a temperature-compensated PTAT+CTAT current, which is then divided by the proportional resistor network to output a sub-1V reference voltage. Substrate modulation stage: The threshold modulation circuit generates a substrate bias voltage, which is applied to the source-substrate junction of the PMOS transistor in the low-power bandgap reference current source circuit to achieve forward bias, reduce the threshold voltage of the PMOS transistor, and make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. Current mirror compensation stage: The current mirror circuit compensates for the mirror current in the low-power bandgap reference current source circuit.

[0062] In one optional implementation of this embodiment, such as Figure 7 As shown, Figure 7 A flowchart of the control method for the low-power bandgap reference current source circuit in Embodiment 2 of the present invention is shown, including the following steps: S701, Start-up phase: Start-up current is injected into the input stage of the error amplifier OPAMP through the start-up circuit, so that the current-mode bandgap circuit is removed from the zero-current state and the power-on start-up is completed. In an optional implementation of this embodiment, a startup circuit ensures that the low-power bandgap reference current source circuit can reliably transition from its initial state to its normal operating state. Since bandgap reference circuits typically have a stable operating point with zero current, the circuit may remain in this undesirable state without external intervention. The startup circuit forces the circuit out of this zero-current state by injecting startup current into the input stage of the error amplifier OPAMP, thereby completing the power-on startup.

[0063] S702, Steady-state operation stage: The error amplifier OPAMP clamps the potentials of nodes N1 and N2 in the current-mode bandgap circuit to be equal, generating a temperature-compensated PTAT+CTAT current, which is then divided by the proportional resistor network to output a sub-1V reference voltage. In an optional implementation of this embodiment, the error amplifier OPAMP precisely controls the operating point of the current-mode bandgap circuit by detecting the voltage difference between nodes N1 and N2 and adjusting its output, thereby generating a current I with PTAT (proportional to absolute temperature) and CTAT (complementary to absolute temperature) components. These two current components are cleverly designed to cancel each other out for temperature changes, ultimately forming a temperature-compensated current I. This current I is then precisely divided by a proportional resistor network to output a stable sub-1V reference voltage, meeting the low-voltage reference requirements of low-power applications.

[0064] S703, Substrate Modulation Stage: A substrate bias voltage is generated by the threshold modulation circuit, and the substrate bias voltage is applied to the source-substrate junction of the PMOS transistor in the low-power bandgap reference current source circuit to achieve forward bias, reduce the threshold voltage of the PMOS transistor, and make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. In an optional implementation of this embodiment, a threshold modulation circuit is used to generate a specific substrate bias voltage. This substrate bias voltage is applied to the source-substrate junctions of all PMOS transistors in the low-power bandgap reference current source circuit, achieving forward bias. Forward bias of the source-substrate junctions effectively reduces the threshold voltage of the PMOS transistors. In low-voltage supply environments, reducing the threshold voltage of the PMOS transistors increases the driving capability of the transistors and provides a larger voltage margin for other parts of the circuit (e.g., the NMOS transistors connected to the output stage of the error amplifier OPAMP), ensuring that these NMOS transistors can operate stably in the saturation region, thereby maintaining the high gain and good linearity of the error amplifier OPAMP.

[0065] It should be noted that this forward bias should not be applied to the source-substrate junction of the input differential pair transistors PM3 and PM4 of the error amplifier OPAMP, in order to avoid affecting the input offset characteristics.

[0066] S704, Current Mirror Compensation Stage: The current mirror circuit compensates for the mirror current in the low-power bandgap reference current source circuit.

[0067] In an optional implementation of this embodiment, the current mirror circuit is used to accurately replicate the reference current generated by the current-mode bandgap circuit. Due to process variations, temperature changes, and the channel length modulation effect of transistors, an uncompensated current mirror may cause errors between the mirrored current and the reference current. Through the compensation mechanism of the current mirror circuit, such as using a series diode compensation method, the accuracy of the mirrored current and the ability to suppress power supply voltage changes can be effectively improved, ensuring accurate current distribution in all parts of the circuit, thereby enhancing the overall performance of the reference current source.

[0068] In summary, Embodiment 2 of this invention provides a control method for a low-power bandgap reference current source circuit. Based on the low-power bandgap reference current source circuit in Embodiment 1, it achieves a sub-1V reference voltage output by setting a proportional resistor network. It eliminates the need for low-threshold devices or BiCMOS technology, is compatible with standard CMOS technology, and avoids the voltage margin loss problem of traditional solutions. The total current of its core and bias circuits reaches the nanoamplitude level, breaking through the power consumption bottleneck. The PMOS pair input stage circuit combined with a source-substrate forward bias threshold modulation circuit restores the high gain of the operational amplifier, solving the problems of device linear region operation and power supply rejection ratio impairment caused by excessive operational amplifier input common-mode voltage. The circuit output accuracy meets the accuracy requirements, overcoming the defects of large drift and low accuracy in "bandgap-free" solutions. The series diode compensation current mirror circuit effectively suppresses threshold mismatch and early effect, reduces current replication error, and improves reference output accuracy. Furthermore, the circuit does not require a complex three-branch current mirror, resulting in a small layout area, which is suitable for wearable chip SiP. It integrates various requirements and breaks the noise-power paradox, solving the problems of high bias current and high output noise of conventional sub-1V bandgap op-amp solutions. It achieves comprehensive technical effects of sub-1V low voltage, microamp / nanoamp level low power consumption, high precision, low noise, and small area, and has excellent prospects for application in power management systems for wearable devices.

[0069] The above provides a detailed description of a low-power bandgap reference current source circuit and control method provided by the present invention. Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0070] Furthermore, the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A low-power bandgap reference current source circuit, characterized in that, The low-power bandgap reference current source circuit includes a current-mode bandgap circuit, an error amplifier input stage circuit, a threshold modulation circuit, and a current mirror circuit. The current-mode bandgap circuit has an built-in error amplifier OPAMP and a proportional resistor network. The input stage of the error amplifier OPAMP is connected to the input stage circuit of the error amplifier. The proportional resistor network is used to divide the reference voltage to the sub-1V level. The error amplifier input stage circuit is a PMOS transistor input stage circuit. The threshold modulation circuit is a source-substrate forward bias threshold modulation circuit. The threshold modulation circuit is used to forward bias the threshold voltage of all PMOS transistors in the low-power bandgap reference current source circuit and to make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. The current mirror circuit is a series diode compensation current mirror circuit structure, and several MOS transistors of the same size are connected in series in the current mirror circuit.

2. The low-power reference current source circuit as described in claim 1, characterized in that, The current-mode bandgap circuit includes an error amplifier OPAMP, a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2A1, a third resistor R2A2, a fourth resistor R2B1, a fifth resistor R2B2, a tenth resistor R7, a twentieth PMOS transistor PM20, a twenty-first PMOS transistor PM21, and a twenty-second PMOS transistor PM22. The base and collector of the first transistor Q1 are grounded, and the emitter of the first transistor Q1 is connected to node N4 and to the drain of the twentieth PMOS transistor PM20. The base and collector of the second transistor Q2 are grounded, and the emitter of the second transistor Q2 is connected to the MINUS terminal of the first resistor R1; The drain of the twentieth PMOS transistor PM20 is connected to the PLUS terminal of the second resistor R2A1; The drain of the 21st PMOS transistor PM21 is also connected to the PLUS terminal of the first resistor R1 and the PLUS terminal of the fourth resistor R2B1. The non-inverting input of the error amplifier OPAMP is connected to node N1, and is also connected to the MINUS terminal of the fourth resistor R2B1 and the PLUS terminal of the fifth resistor R2B2. The inverting input of the error amplifier OPAMP is connected to node N2, and is also connected to the MINUS terminal of the second resistor R2A1 and the PLUS terminal of the third resistor R2A2. The output of the error amplifier OPAMP is connected to the gate of the twentieth PMOS transistor PM20, the gate of the twentieth PMOS transistor PM21, and the gate of the twentieth PMOS transistor PM22.

3. The low-power reference current source circuit as described in claim 2, characterized in that, The input stage of the error amplifier OPAMP uses a pair of PMOS transistors. The input stage circuit of the error amplifier includes the twentieth PMOS transistor PM20, the twenty-first PMOS transistor PM21, the twenty-third PMOS transistor PM23, the twenty-fourth PMOS transistor PM24, the twenty-fifth PMOS transistor PM25, the twenty-sixth PMOS transistor PM26, the twenty-seventh PMOS transistor PM27, the twenty-eighth PMOS transistor PM28, the first transistor Q1, the second transistor Q2, the sixth NMOS transistor NM6, the seventh NMOS transistor NM7, the eighth NMOS transistor NM8, the ninth NMOS transistor NM9, the first resistor R1, the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2. The gate of the 23rd PMOS transistor PM23 is connected to a bias voltage vbp1, and the gate of the 24th PMOS transistor PM24 is connected to a bias voltage vbp2. The 23rd PMOS transistor PM23 and the 24th PMOS transistor PM24 form the tail current source of the input stage of the error amplifier OPAMP. The 25th PMOS transistor PM25 and the 26th PMOS transistor PM26 serve as the input pair of the error amplifier OPAMP. The gate of the 25th PMOS transistor PM25 is connected to node N1 of the current-mode bandgap circuit, and the gate of the 26th PMOS transistor PM26 is connected to node N2 of the current-mode bandgap circuit. The 25th PMOS transistor PM25 and the 6th NMOS transistor NM6, as well as the 26th PMOS transistor PM26 and the 7th NMOS transistor NM7, form a folded common-source common-gate pair. The gates of the 6th NMOS transistor NM6 and the 7th NMOS transistor NM7 are connected to a bias voltage vbn1. The 27th PMOS transistor PM27 and the 28th PMOS transistor PM28 form a common-source cascode current mirror load; The gates of the eighth NMOS transistor NM8 and the ninth NMOS transistor NM9 are connected to a bias voltage vbn2.

4. The low-power reference current source circuit as described in claim 3, characterized in that, The proportional resistor network consists of the second resistor R2A1, the third resistor R2A2, the fourth resistor R2B1, and the fifth resistor R2B2. The proportional resistor network scales the reference voltage downward by setting the voltage division ratio. The current-mode bandgap circuit generates a PTAT+CTAT current through the current mirror circuit and injects it into the tenth resistor R7. The voltage value after voltage division is taken at the output terminal of the current-mode bandgap circuit.

5. The low-power reference current source circuit as described in claim 1, characterized in that, The threshold modulation circuit includes a twelfth NMOS transistor NM12, a thirteenth NMOS transistor NM13, a fourteenth NMOS transistor NM14, an eleventh resistor R8, a twenty-ninth PMOS transistor PM29, and a thirtieth PMOS transistor PM30. The gate and drain of the twelfth NMOS transistor NM12 are shorted and connected to the bias current ic, and are also connected to the gate of the thirteenth NMOS transistor NM13 and the gate of the fourteenth NMOS transistor NM14. The drain of the thirteenth NMOS transistor NM13 is connected to the MINUS terminal of the eleventh resistor R8 via the output node vb. The gate and drain of the thirtieth PMOS transistor PM30 are shorted together, and the gate of the twenty-ninth PMOS transistor PM29 and the drain of the fourteenth NMOS transistor NM14 are connected together, and the bias voltage vbp2 is connected to it.

6. The low-power reference current source circuit as described in claim 1, characterized in that, The current mirror circuit includes an eighth NMOS transistor NM8, a ninth NMOS transistor NM9, a tenth NMOS transistor NM10, an eleventh NMOS transistor NM11, a nineteenth NMOS transistor NM19, and a twentieth NMOS transistor NM20. The gate of the nineteenth NMOS transistor NM19 is connected to the gate of the twentieth NMOS transistor NM20, and the source of the nineteenth NMOS transistor NM19 is connected to the drain of the twentieth NMOS transistor NM20. The source of the tenth NMOS transistor NM10 is connected to the drain of the eighth NMOS transistor NM8, and the gate of the tenth NMOS transistor NM10 is connected to the gate of the eighth NMOS transistor NM8. The source of the eleventh NMOS transistor NM11 is connected to the drain of the ninth NMOS transistor NM9, and the gate of the eleventh NMOS transistor NM11 is connected to the gate of the ninth NMOS transistor NM9, and is also connected to the gate of the nineteenth NMOS transistor NM19, the gate of the twentieth NMOS transistor NM20, the gate of the tenth NMOS transistor NM10, and the gate of the eighth NMOS transistor NM8.

7. The low-power reference current source circuit as described in claim 1, characterized in that, The low-power bandgap reference current source also includes a startup circuit, which is used to inject startup current into the input stage of the error amplifier OPAMP, so that the current-mode bandgap circuit is taken out of the zero-current state.

8. The low-power reference current source circuit as described in claim 1, characterized in that, The low-power bandgap reference current source also includes a cascode current mirror circuit, which is used to improve the output impedance and current replication accuracy of the low-power bandgap reference current source circuit.

9. The low-power reference current source circuit as described in claim 1, characterized in that, A capacitor C1 is provided between the output terminal of the error amplifier OPAMP and the power supply VDD. The capacitor C1 is used to increase the bandwidth of the low-power bandgap reference current source circuit.

10. A control method for a low-power bandgap reference current source circuit, characterized in that, The control method is implemented based on the low-power bandgap reference current source circuit according to any one of claims 1-9, and the control method includes: Start-up phase: Start-up current is injected into the input stage of the error amplifier OPAMP through the start-up circuit, causing the current-mode bandgap circuit to leave the zero-current state and complete the power-on start-up. Steady-state operation phase: The error amplifier OPAMP clamps the potentials of nodes N1 and N2 in the current-mode bandgap circuit to be equal, generating a temperature-compensated PTAT+CTAT current, which is then divided by the proportional resistor network to output a sub-1V reference voltage. Substrate modulation stage: The threshold modulation circuit generates a substrate bias voltage, which is applied to the source-substrate junction of the PMOS transistor in the low-power bandgap reference current source circuit to achieve forward bias, reduce the threshold voltage of the PMOS transistor, and make the NMOS transistor connected to the output stage of the error amplifier OPAMP work in the saturation region. Current mirror compensation stage: The current mirror circuit compensates for the mirror current in the low-power bandgap reference current source circuit.

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