IGBT device with built-in ballast resistor

Abstract

The utility model relates to the technical field of power semiconductors, in particular to an IGBT (Insulated Gate Bipolar Transistor) device with a built-in ballast resistor, which comprises a trench region, N + type source regions, polycrystalline silicon regions and contact hole regions, a plurality of N + type source regions and polycrystalline silicon regions are alternately arranged at intervals along the length direction of the trench region, and the contact hole regions are positioned in the N + type source regions; along the thickness direction of the IGBT device, the IGBT device sequentially comprises a collector metal layer, a P + substrate and an N-substrate, and a deep groove is etched on the N-substrate corresponding to a groove region; first doped regions and second doped regions which are alternately distributed are formed on the N-substrate on the two opposite sides of the deep groove, the positions of the first doped regions correspond to the positions of the N + type source regions, and the positions of the second doped regions correspond to the positions of the polycrystalline silicon regions; the top end of the first doped region is provided with an N + well region, and the top end of the second doped region is provided with a second N-well region. The IGBT device provided by the utility model can obtain a larger positive temperature coefficient, and has little influence on the conduction voltage drop VCESAT of the IGBT device at normal temperature.

Description

TECHNICAL FIELD

[0001] The utility model relates to power semiconductor technology field especially relates to IGBT device with built-in ballast resistance. BACKGROUND

[0002] Semiconductor power device is the basic electronic component of energy control and conversion of power electronic system, and the continuous development of power electronic technology opens up a wide application field for semiconductor power device. MOS type semiconductor power device marked by IGBT, VDMOS and CoolMOS is the mainstream of today's power electronic devices, and the most representative semiconductor power device is IGBT.

[0003] IGBT (Insulated Gate Bipolar Transistor) is a voltage-controlled MOS / BJT composite device. In structure, the structure of IGBT is very similar to VDMOS, only the N + Substrate of VDMOS is adjusted to P + Substrate, but the introduced conductance modulation effect overcomes the contradiction between the on-resistance and the breakdown voltage inherent in VDMOS, so that IGBT has the main advantages of bipolar power transistor and power MOSFET: high input impedance, small input drive power, low on-voltage, large current capacity, fast switching speed, etc. It is due to the unique and irreplaceable performance advantages of IGBT that it has been widely used in many fields since the practical product is put into use, such as new energy technology, advanced transportation tools represented by high-speed rail and high-speed train, hybrid electric vehicle, office automation and household appliances, etc. In the resource-saving society advocating low-carbon and environmental protection, IGBT as a high-performance and high-efficiency switching control component is paid more attention and developed, and higher requirements are put forward for safety, reliability and intelligence.

[0004] At present, in order to pursue lower saturation voltage drop, the size of the trench is made smaller and the channel density is made larger in the trench gate IGBT technology, which will increase the saturation current of the device, thereby greatly reducing the short-circuit resistance of the device. In order to improve the short-circuit resistance of the device, the prior art periodically injects N-type impurities to form N+ regions between the trenches of the conventional carrier storage trench gate IGBT, so that the channel length is increased and the channel resistance R CH is increased, thereby reducing the saturation current of the device. Although this method can improve the short-circuit resistance of the device, it will also cause the on-voltage V CESAT to increase. The light-doped N-type ballast resistance of the prior art scheme is mainly proposed for planar gate IGBT device, and does not provide a layout unit of N-type ballast resistance, a corresponding longitudinal device structure diagram and a manufacturing process. Utility model content

[0005] Therefore, the utility model discloses an IGBT device with built-in ballast resistance to at least solve the problem of weak short-circuit resistance of the existing trench IGBT device. CESAT Significant increase.

[0006] The utility model solves the above technical problem through the following technical scheme:

[0007] The embodiment of the utility model provides a kind of IGBT device with built-in ballast resistance, including multiple trench area, and N+ type source area, polysilicon area and contact hole area being set between each adjacent two described trench area, the N+ type source area, polysilicon area and contact hole area are at least provided with two, multiple N+ type source area and polysilicon area are along the first direction interval alternately arranged, the contact hole area is located inside N+ type source area, the first direction is along the direction of trench area length;

[0008] Along second direction, the IGBT device includes collector metal layer, P+ substrate and N- substrate in turn, the N- substrate is etched to form deep groove corresponding trench area, the second direction is along the direction of IGBT device thickness;The N- substrate on the opposite side of the deep groove is formed with the first doped area and the second doped area that are alternately distributed, the position of the first doped area corresponds to N+ type source area, the position of the second doped area corresponds to polysilicon area;The top of the first doped area has N+ well area, and the top of the second doped area has second N- well area.

[0009] In some embodiments, the first doped area includes P- well area, first N- well area and N+ well area formed in N- substrate in turn, the inside of the first doped area is provided with P+ well area, the upper end of the P+ well area is located in the inside of N+ well area, the lower end is located in the inside of P- well area, and the position of the P+ well area corresponds to contact hole area.

[0010] In some embodiments, the N+ well area is injected with arsenic ion concentration of 10 19 ~ 10 20 cm -3 , and the junction depth size of the N+ well area on the first N- well area is 0.2-0.25 microns.

[0011] In some embodiments, the second doped area includes P- well area, first N- well area and second N- well area formed in N- substrate in turn, the composition and formation condition of the first N- well area and the second N- well area are same, and the first N- well area and the second N- well area are simultaneously formed.

[0012] In some embodiments, the first N-well region in the first and second doped regions is completely identical; the junction depth dimension of the first and second N-well regions on the P-well region is 0.35-0.45 microns, and the phosphorus ion concentration of the first and second N-well regions is 10 17 ~10 18 cm -3 .

[0013] In some embodiments, the P-well region in the first and second doped regions is completely identical, and the forming depth of the P-well region on the N-substrate is 2.5-3.5 microns.

[0014] In some embodiments, the depth dimension of the deep trench is 4-6 microns.

[0015] In some embodiments, the internal precipitated polysilicon material of the deep trench forms a gate polysilicon, and the second doped region is also precipitated with a polysilicon material to form a polysilicon layer, the polysilicon layer covers the deep trench and the second doped region, and the polysilicon layer and the gate polysilicon are connected.

[0016] In some embodiments, a gate oxide layer is formed between the trench wall and the bottom of the deep trench and the gate polysilicon, and a gate oxide layer is also formed between the polysilicon layer and the second doped region, and the thickness of the gate oxide layer is

[0017] In some embodiments, the IGBT device further comprises an emitter metal layer and an ILD dielectric layer, one side of the ILD dielectric layer faces the emitter metal layer, and the other side faces the first and second doped regions.

[0018] In the IGBT device with built-in ballast resistor, along the length direction of the deep trench, the alternating distribution region of the N+ well region and the second N-well region is formed, the second N-well region is lightly doped, and the lower the doping concentration, the greater the temperature change rate, which is a positive temperature coefficient, and can play a ballast effect at high temperature, improving the short-circuit resistance of the IGBT device. N- Because the N-substrate is located below the polysilicon gate, when the IGBT device is forward conducting, the polysilicon gate is high potential, and the surface of the N-substrate region will realize electron accumulation, reducing the on-resistance, so compared with the structure of the traditional IGBT device, the on-voltage drop V CESAT will not increase too much.

[0019] The IGBT device with built-in ballast resistor can obtain a larger positive temperature coefficient, and the on-voltage drop V CESATThe influence is little, compared with traditional IGBT device process or structure, has the advantages such as simple process, low cost, strong short-circuit resistance, long service life, is applicable to mass industrial production. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The layout unit of the IGBT device with built-in ballast resistor is provided in the utility model;

[0021] Figure 2 The layout unit of the IGBT device with built-in ballast resistor is provided in the utility model; Figure 1 The horizontal section structure diagram of the A-A' unit wire in the utility model is provided in the utility model;

[0022] Figure 3 The horizontal section structure diagram of the A-A' unit wire in the utility model is provided in the utility model; Figure 1 The horizontal section structure diagram of the B-B' unit wire in the utility model is provided in the utility model;

[0023] Figure 4 When V GE When V TH , Figure 1 The current Ic flow path circuit diagram of A-A' position and B-B' position in the utility model is provided in the utility model;

[0024] Figure 5 The short-circuit current density simulation waveform comparison diagram of the IGBT device and conventional trench gate IGBT device is provided in the utility model;

[0025] The trench area 1, N+ type source area 2, polycrystalline silicon area 3, contact hole area 4, collector metal layer 100, P+ substrate 200, N- substrate 300, N+ well area 320, second N- well area 330, first N- well area 340, P+ well area 350, P- well area 400, gate polycrystalline silicon 500, polycrystalline silicon layer 600, gate oxide layer 700, emitter metal layer 800, ILD dielectric layer 900. DETAILED DESCRIPTION

[0026] The advantages and effects of the utility model can be understood by the contents disclosed in the specification by the specific embodiment of the utility model. It should be noted that the drawings provided in the following embodiment are only used for example description, and the representation is only a schematic diagram, and cannot be understood as the limitation of the utility model, in order to better illustrate the embodiment of the utility model, some components in the drawing can be omitted, enlarged or reduced, and the size of the actual product is not represented; for those skilled in the art, some well-known structures and their description can be omitted.

[0027] The same or similar reference signs in the drawings of the embodiments of the utility model correspond to the same or similar components, and in the description of the utility model, it is understood that if the directions or position relations indicated by the terms "upper", "lower", "left", "right", "front", "back" and the like are based on the directions or position relations shown in the drawings, they are only for the convenience of describing the utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular direction, be constructed in a particular direction and be operated, therefore the terms used to describe the position relations in the drawings are only for exemplary illustration, and cannot be understood as a limitation on the utility model, and for ordinary skilled persons in the art, the specific meanings of the above terms can be understood according to the specific circumstances.

[0028] The IGBT device with the built-in ballast resistor of the utility model, the layout structure please see Figure 1 , the IGBT device includes a plurality of groove areas 1, and N+ type source area 2, polysilicon area 3 and contact hole area 4 arranged between every two adjacent groove areas 1, N+ type source area 2, polysilicon area 3 and contact hole area 4 are at least provided with two, a plurality of N+ type source area 2 and polysilicon area 3 are alternately arranged along the first direction, for example, are arranged according to the rule of N+ type source area 2, polysilicon area 3, N+ type source area 2, polysilicon area 3 … Contact hole area 4 is located in the inside of N+ type source area 2, and the first direction is the direction along the length of groove area 1.

[0029] Along the second direction, the IGBT device sequentially includes collector metal layer 100, P+ substrate 200 and N- substrate 300, and a deep groove is formed on N- substrate 300 corresponding to groove area 1 etching, and the second direction is along the direction of the thickness of the IGBT device. The N- substrate 300 on the opposite sides of the deep groove is formed with alternately distributed first doped area and second doped area, the position of the first doped area corresponds to N+ type source area 2, and the position of the second doped area corresponds to polysilicon area 3;The top end of the first doped area has N+ well area 320, and the top end of the second doped area has second N- well area 330.

[0030] Please refer to Figure 2 , the first doped area includes P- well area 400, first N- well area 340 and N+ well area 320 formed on N- substrate 300 in sequence, the inside of the first doped area is provided with P+ well area 350, the upper end of P+ well area 350 is located in the inside of N+ well area 320, the lower end is located in the inside of P- well area 400, and the position of P+ well area 350 corresponds to contact hole area 4. N+ well area 320 is formed by implanting arsenic ions into first N- well area 340 and high-temperature pushing, the arsenic ion concentration of N+ well area 320 is 10 19 ~10 20 cm -3 , the junction depth size of N+ well area 320 on first N- well area 340 is 0.2~0.25 microns.

[0031] Please refer to Figure 3 , the second doped region includes P-well region 400, first N-well region 340 and second N-well region 330 formed in sequence on N-substrate 300, and the composition and formation conditions of first N-well region 340 and second N-well region 330 are the same. First N-well region 340 in the first doped region and the second doped region is completely the same, and the phosphorus ion concentration injected by first N-well region 340 and second N-well region 330 is 10 17 ~ 10 18 cm -3 .

[0032] The internal deposition of polysilicon material in the deep trench forms gate polysilicon 500, and the second doped region also deposits polysilicon material to form polysilicon layer 600, polysilicon layer 600 covers the deep trench and the second doped region, and polysilicon layer 600 and gate polysilicon 500 are connected. The trench wall and the trench bottom of the deep trench and the gate polysilicon 500 form a gate oxide layer 700, and the polysilicon layer 600 and the second doped region also form a silicon dioxide gate oxide layer 700, and the thickness of the gate oxide layer 700 is

[0033] The IGBT device with built-in ballast resistor of the present application also includes an emitter metal layer 800 and an ILD dielectric layer 900, one side of the ILD dielectric layer 900 faces the emitter metal layer 800, and the other side faces the first doped region and the second doped region.

[0034] The forming method of the built-in ballast resistor of the above IGBT device is as follows:

[0035] A patterned first mask layer is formed on N-substrate 300 using a mask for photolithography, the first mask layer is formed with a trench area 1 by photolithography, and N-substrate 300 is etched corresponding to the trench area 1 to form at least two deep trenches on N-substrate 300, and the depth of the deep trench is 4-6 microns. The trench wall and the trench bottom of the deep trench and the top surface of N-substrate 300 form a gate oxide layer 700 by thermal growth, and the thickness of the gate oxide layer 700 is Boron ion implantation is performed on N-substrate 300 on both sides of the deep trench, and the implantation concentration of boron ions is 10 13 ~ 10 14 cm -2and at 950°C high temperature push knot 55 min, on the N- substrate 300 on both sides of the deep groove form P- well region 400, P- well region 400 on the N- substrate 300 on the junction depth size is 2.5 ~ 3.5 microns. On the gate oxide layer 700 precipitate polysilicon material, form gate polysilicon 500 in the deep groove, and form a polysilicon layer outside the deep groove, using a mask for lithography to form a patterned second mask layer, along the first direction, the second mask layer lithography has a plurality of N+ type source region 2 and polysilicon region 3 with alternating interval distribution, etching N+ type source region corresponding polysilicon layer to the gate oxide layer, after etching, gate polysilicon 500 and polysilicon layer 600 still have connection. Phosphorus ion implantation on P- well region 400, the injection concentration is 10 17 ~ 10 18 cm -3 , and at 950°C high temperature push knot 60 min, form N- well region on P- well region 400, the junction depth is 0.35 ~ 0.45 microns, the polysilicon region corresponding to N- well region at this time is the first N- well region 340 and the second N- well region 330 of the second doped region. Subsequently, arsenic implantation is performed on the N- well region corresponding to the N+ type source region 2, and the injection concentration is 10 19 ~ 10 20 cm -3 , and at 950°C high temperature push knot 30 min, form N+ well region 320 on the N- well region corresponding to the N+ type source region, with a junction depth of 0.2 ~ 0.25 um. At this time, the N- well region with arsenic injection in the N+ type source region is the first N- well region 340 of the first doped region.

[0036] In the IGBT device of the present application, along the first direction, the top of the first N- well region between every two adjacent deep grooves is provided with N+ well region 320 and second N- well region 330 with alternating interval, and the N+ well region 320 and the second N- well region 330 with alternating interval correspond to the N+ type source region 2 and the polysilicon region 3, respectively. The polysilicon layer connected to the polysilicon gate blocks the injection of N+ (arsenic), and through the difference in diffusion coefficient of phosphorus and arsenic, only an N- ballast resistance region is formed below the polysilicon layer, the length of the N- region is indirectly increased between the polysilicon regions, the ballast resistance R N- is increased, so that it can play a better ballast effect at high temperature. The polysilicon layer is connected to the polysilicon gate in the deep groove to realize equipotential, and when the gate is energized, the other side of the gate oxide layer will be inverted or electron accumulation into N, and the internal resistance will not increase too much when the IGBT device is turned on at room temperature, and the ballast resistance R N- has a positive temperature coefficient, which can realize the ballast effect.

[0037] The purpose of choosing N-type lightly doped ballast resistor in the application is that, at room temperature, impurities in the single crystal silicon are completely ionized, and when the temperature rises, the mobility decreases with the increase of temperature due to the scattering of lattice vibration, especially the scattering of phonon, so that the resistivity increases with the increase of temperature, and the temperature coefficient is positive at this time. If the ballast resistor is N-type heavily doped, the temperature coefficient may be negative, or the positive temperature coefficient is small, and the ballast effect is poor.

[0038] When V GE >V TH , the current I C flows through the circuit diagram of the flow path Figure 4 , Figure 4 , wherein Vbi represents the voltage generated by the built-in electric field of the PN junction, R SUB represents the substrate resistance, R CH represents the channel resistance, R N- represents the N-well region resistance, and R N+ represents the N+ well region resistance. It can be seen from Figure 4 that the currents Ic at the positions of A-A' and B-B' in Figure 1 all flow through the ballast resistor R N- . The value of the ballast resistor R N- is calculated as follows:

[0039]

[0040] , wherein μ n represents the electron mobility, q represents the elementary charge, t s represents the thickness, N D represents the doping concentration, and p s represents the resistivity, with the unit of Ω·cm.

[0041] To detect the related performance of the IGBT device of the application, the IGBT device of the application and the conventional trench gate IGBT device are taken as the detection objects, and the MEDICI software simulation is used to compare the 1200V trench gate IGBT short-circuit current density waveforms with R N- ballast resistor (the IGBT device of the application) and without R N- ballast resistor (the conventional trench gate IGBT device), and the simulation comparison diagram is shown in Figure 5 . It can be seen from Figure 5 that the saturation currents of the IGBT devices with R N- ballast resistor and without R N- ballast resistor are not much different at the initial stage of short circuit, and as the short-circuit time increases, the temperature of the device gradually rises, the ballast resistor R N- increases with the increase of temperature, forcing the saturation current to decrease, and finally the short-circuit resistance time of the 1200V trench gate IGBT with R N- ballast resistor is longer than that without RN- Length of ballast resistor.

[0042] The above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced by equivalents without departing from the purpose and scope of the present application, and all should be covered in the scope of the claims of the present application. The technical, shape, and structure parts not described in detail in the present application are well-known technologies.

Claims

1. An IGBT device with built-in ballast resistor, characterized in that, The IGBT device comprises a plurality of trench regions, and N+ type source regions, polysilicon regions and contact hole regions arranged between every two adjacent trench regions, wherein the N+ type source regions, the polysilicon regions and the contact hole regions are each provided with at least two, the plurality of N+ type source regions and the plurality of polysilicon regions are alternately arranged along a first direction, the contact hole regions are located inside the N+ type source regions, and the first direction is a direction along the length of the trench regions. Along a second direction, the IGBT device comprises, in sequence, a collector metal layer, a P+ substrate and an N- substrate, a deep trench is formed on the N- substrate corresponding to the trench regions, the second direction is a direction along the thickness of the IGBT device, first doped regions and second doped regions are alternately arranged on the N- substrate on opposite sides of the deep trench, the positions of the first doped regions correspond to the N+ type source regions, and the positions of the second doped regions correspond to the polysilicon regions, the top end of the first doped region has an N+ well region, and the top end of the second doped region has a second N- well region. The first doped region comprises, in sequence, a P- well region, a first N- well region and an N+ well region formed on the N- substrate, and the junction depth size of the N+ well region on the first N- well region is 0.2-0.25 microns.

2. The IGBT device with built-in ballast resistor according to claim 1, characterized in that, The first doped region is provided with a P+ well region, the upper end of the P+ well region is located inside the N+ well region, the lower end of the P+ well region is located inside the P- well region, and the position of the P+ well region corresponds to the contact hole region.

3. The IGBT device with built-in ballast resistor according to claim 2, characterized in that, The second doped region comprises, in sequence, a P- well region, a first N- well region and a second N- well region formed on the N- substrate, the composition and formation conditions of the first N- well region and the second N- well region are the same, and the first N- well region and the second N- well region are simultaneously formed.

4. The IGBT device with built-in ballast resistor according to claim 3, characterized in that, The first N- well regions in the first doped regions and the second doped regions are completely the same, and the junction depth size of the first N- well region and the second N- well region on the P- well region is 0.35-0.45 microns.

5. The IGBT device with built-in ballast resistor according to claim 3, characterized in that, The P- well regions in the first doped regions and the second doped regions are completely the same, and the formation depth of the P- well region on the N- substrate is 2.5-3.5 microns.

6. The IGBT device with built-in ballast resistor according to claim 1, characterized in that, The depth size of the deep trench is 4-6 microns.

7. The IGBT device with built-in ballast resistor according to claim 6, characterized in that, Polysilicon material is precipitated in the deep trench to form a gate polysilicon, and the second doped region is also precipitated with polysilicon material to form a polysilicon layer, the polysilicon layer covers the deep trench and the second doped region, and the polysilicon layer and the gate polysilicon are connected.

8. The IGBT device with built-in ballast resistor according to claim 7, characterized in that, A gate oxide layer is formed between the deep trench wall and the bottom and the gate polysilicon, and a gate oxide layer is also formed between the polysilicon layer and the second doped region, and the thickness of the gate oxide layer is 800Å-1200Å.

9. The IGBT device with built-in ballast resistor according to any one of claims 1-8, characterized in that, The IGBT device further comprises an emitter metal layer and an ILD dielectric layer, one side of the ILD dielectric layer faces the emitter metal layer, and the opposite side faces the first doped regions and the second doped regions.

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