Solar cell
By introducing a distribution design of metal particle layers and metal microcrystalline layers into solar cells, the problem of low carrier transport efficiency was solved, and a significant improvement in the photoelectric conversion efficiency of solar cells was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-03
- Publication Date
- 2026-03-27
AI Technical Summary
The carrier transport efficiency of existing solar cells is not high, which makes it difficult to improve the photoelectric conversion efficiency. In particular, in the design of tunneling silicon oxide layer and polycrystalline silicon layer in TOPCon cells, the problems of increased junction resistance and deterioration of fill factor are prominent.
The design employs a distribution of metal particle layers and metal microcrystalline layers to avoid large-sized metal particles from damaging the passivation effect of the tunneling layer. Furthermore, the local metal microcrystalline layers electrically connect the silicon substrate and the external metal gate layer, reducing lateral carrier transport losses and optimizing the carrier concentration at the tunneling layer interface.
It significantly improves carrier transport efficiency, enhances the photoelectric conversion efficiency of solar cells, reduces lateral carrier transport loss, and strengthens the overall performance of the cell.
Smart Images
Figure CN224054707U_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The utility model belongs to solar cell technical field, concretely relates to a solar cell. BACKGROUND
[0002] In the prior art, a high-quality ultra-thin tunneling oxide layer and a doped polysilicon layer are arranged on the back of a silicon substrate of a solar cell to form a passivation contact, which is called a TOPCon cell, has excellent interface passivation effect, and significantly reduces the recombination of the back electrode area, so it is widely used. The TOPCon cell needs a high-quality tunneling oxide silicon layer to reduce the saturation current density, and a relatively thin polysilicon layer to reduce light parasitic absorption, but it also faces problems such as increased junction resistance (i.e. tunneling junction resistance), deteriorated fill factor, and thus difficult to improve efficiency.
[0003] To solve the above problems, CN118299432A discloses a solar cell back structure, which includes a single crystal silicon substrate and a laminated polysilicon passivation layer structure located on one side of the single crystal silicon substrate. The laminated polysilicon passivation layer structure is sequentially arranged from the inside to the outside as follows: a first tunneling oxide layer, a first doped polysilicon layer, a second tunneling oxide layer, a second doped polysilicon layer, and a surface passivation layer. A metal electrode main body is located on the side of the laminated polysilicon passivation layer away from the single crystal silicon substrate. The solar cell back structure also includes silver particles type I and silver particles type II, which are located between the metal electrode main body and the single crystal silicon substrate. This patent uses a thin and dense tunneling oxide silicon layer to avoid the penetration of the metal electrode through the first tunneling oxide silicon layer, but the carrier transport efficiency is not high, which makes it difficult to significantly improve the photoelectric conversion efficiency of the solar cell.
[0004] Therefore, how to significantly improve the carrier transport efficiency of the solar cell and improve the photoelectric conversion efficiency of the solar cell is a technical problem to be solved. Utility model content
[0005] In view of the deficiencies of the prior art, the purpose of the utility model is to provide a solar cell. In the battery structure provided by the utility model, the distribution of the metal particle layer and the metal microcrystal layer helps to avoid the destruction of the passivation effect of the tunneling layer by large-size metal particles, and the local metal microcrystal layer is electrically connected to the silicon substrate and the external metal grid line layer, which significantly reduces the loss of carrier lateral transport and the carrier concentration between the silicon substrate and the tunneling layer interface, significantly improves the carrier transport efficiency, and helps to greatly improve the photoelectric conversion efficiency of the solar cell.
[0006] To achieve the purpose of the utility model, the utility model adopts the following technical solutions:
[0007] The utility model provides a solar cell, solar cell includes:
[0008] Silicon substrate.
[0009] Tunneling layer, the tunneling layer is located at the back of silicon substrate, and has a plurality of notches.
[0010] Crystalline conductive layer, the crystalline conductive layer is located on the side surface of the tunneling layer away from the silicon substrate.
[0011] Back passivation film, the back passivation film is located on the side surface of the crystalline conductive layer away from the silicon substrate.
[0012] Metal electrode, the metal electrode is located at the back of solar cell, the metal electrode includes metal grid line layer, metal particle layer and metal microcrystal layer;Wherein, the metal grid line layer penetrates the back passivation film, the metal particle layer is located in the crystalline conductive layer and does not contact tunneling layer, the metal microcrystal layer is contacted with the silicon substrate.
[0013] The solar cell provided by the utility model, the distribution of the metal particle layer and the metal microcrystal layer helps to avoid the damage of large-size metal particles to the passivation effect of the tunneling layer, and the local metal microcrystal layer is electrically connected with the silicon substrate and the external metal grid line layer, which significantly reduces the loss of carrier transverse transmission, reduces the carrier concentration between the silicon substrate and the tunneling layer interface, significantly improves the carrier transmission efficiency, and helps to greatly improve the photoelectric conversion efficiency of the solar cell.
[0014] Preferably, the size of the metal particle layer is 0.5-100 μm.
[0015] Preferably, the size of the metal microcrystal layer is less than 200 nm.
[0016] Preferably, the metal microcrystal layer is contacted with the silicon substrate through the notch of the tunneling layer;Or, the interface between the tunneling layer notch and the silicon substrate is distributed with the metal microcrystal layer.
[0017] Preferably, the width of the notch is less than 200 nm.
[0018] Preferably, a part of the crystalline conductive layer extends into the notch and is contacted with the silicon substrate.
[0019] Preferably, the silicon substrate is an n-type silicon substrate or a p-type silicon substrate.
[0020] Preferably, the crystalline conductive layer is an n-type crystalline conductive layer or a p-type crystalline conductive layer.
[0021] Preferably, the silicon substrate and the crystalline conductive layer are of the same or opposite conductive type.
[0022] Preferably, the tunneling layer is any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer.
[0023] Preferably, the thickness of the tunneling layer is denoted as d1, and 1 nm < d1 ≤ 7 nm.
[0024] Preferably, the crystalline conductive layer is a polysilicon layer or a silicon carbide layer.
[0025] Preferably, the thickness of the crystalline conductive layer is denoted as d2, and 50 nm ≤ d2 ≤ 170 nm.
[0026] Preferably, the thickness of the tunneling layer satisfies: 2 nm < d1 ≤ 5 nm.
[0027] Preferably, the thickness of the crystalline conductive layer satisfies: 60 nm ≤ d2 ≤ 100 nm.
[0028] Preferably, the back surface passivation film is a single-layer back surface passivation film or at least two layers of back surface passivation films.
[0029] Preferably, the at least two layers of back surface passivation films include a plurality of back surface passivation layers and a plurality of back surface anti-reflection layers arranged in a stack.
[0030] Preferably, the back surface passivation layer is a silicon oxynitride layer.
[0031] Preferably, the back surface anti-reflection layer is a hydrogenated silicon nitride anti-reflection layer and / or a silicon oxynitride anti-reflection layer.
[0032] Preferably, the thickness of the back surface passivation layer is less than the thickness of the anti-reflection layer.
[0033] Preferably, the back surface anti-reflection layer includes a hydrogenated silicon nitride anti-reflection layer and a silicon oxynitride anti-reflection layer arranged in a stack in a direction away from the back surface of the silicon substrate.
[0034] Preferably, the thickness of the back surface passivation layer is less than or equal to 10 nm.
[0035] Preferably, in the back surface anti-reflection layer, the thickness of the hydrogenated silicon nitride anti-reflection layer is 30-70 nm.
[0036] Preferably, in the back surface anti-reflection layer, the thickness of the silicon oxynitride anti-reflection layer is 20-60 nm.
[0037] Preferably, the front surface of the silicon substrate is provided with an emitter region, and the conductive type of the emitter region is p-type.
[0038] Preferably, the emitter region is located inside or outside the front surface of the silicon substrate.
[0039] Preferably, the solar cell further comprises a front passivation film disposed on the emitter region.
[0040] Preferably, the front passivation film comprises a front passivation layer and a front anti-reflective layer disposed in a stack along a direction away from the front surface of the silicon substrate.
[0041] Preferably, the front passivation layer is an aluminum oxide layer.
[0042] Preferably, the front anti-reflective layer is any one or a combination of at least two of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a magnesium fluoride layer.
[0043] Preferably, the solar cell further comprises a light-receiving surface metal electrode in contact with the emitter region through the front passivation film.
[0044] Preferably, the light-receiving surface metal electrode is any one or a combination of at least two of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode.
[0045] Preferably, the crystalline conductive layer comprises n-type and p-type crystalline conductive layers arranged apart from each other along a horizontal plane of the silicon substrate, and an isolation region is disposed between adjacent n-type and p-type crystalline conductive layers, the isolation region being covered with the back passivation film.
[0046] Preferably, the metal electrode comprises a positive electrode and a negative electrode, the positive electrode being in contact with the p-type crystalline conductive layer through the back passivation film, and the negative electrode being in contact with the n-type crystalline conductive layer through the back passivation film.
[0047] Preferably, the positive and negative electrodes are each independently any one or a combination of at least two of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode.
[0048] Preferably, the back surface of the silicon substrate is provided with a plurality of n-type and p-type conductive regions arranged apart from each other along a horizontal direction of the back surface of the silicon substrate and forming a height difference along a vertical direction of the back surface of the silicon substrate.
[0049] Preferably, the tunneling layer and the crystalline conductive layer are disposed in the n-type conductive regions.
[0050] Preferably, the back passivation film is further disposed on the back surface of the silicon substrate of the p-type conductive regions, and covers the sidewalls of the tunneling layer and the crystalline conductive layer.
[0051] Preferably, the p-type conductive region is provided with an aluminum electrode, which includes an aluminum gate line layer and an aluminum-silicon alloy layer, the aluminum gate line layer is located on the surface of the p-type conductive region and penetrates the back passivation film, and the aluminum-silicon alloy layer is in contact with the silicon substrate.
[0052] Preferably, the crystalline conductive layer includes a first crystalline conductive layer and a second crystalline conductive layer which are stacked along the direction away from the back surface of the silicon substrate.
[0053] Preferably, a buffer layer is arranged between the first crystalline conductive layer and the second crystalline conductive layer.
[0054] Preferably, the buffer layer is any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer.
[0055] Preferably, the buffer layer has a plurality of notches, and the density of the notches in the buffer layer is greater than the density of the notches in the tunneling layer.
[0056] Preferably, the metal particle layer is a metal alloy layer, and the metal microcrystal layer is a metal element layer.
[0057] Preferably, the metal electrode is any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode, or a combination of at least two thereof.
[0058] The numerical range of the utility model not only includes the point values listed above, but also includes any point values between the above numerical ranges that are not listed, limited by the length and for the sake of simplicity, the utility model will not exhaustively list the specific point values included in the range.
[0059] Compared with the prior art, the utility model has the following beneficial effects:
[0060] In the battery structure provided by the utility model, the distribution of the metal particles and the metal microcrystals helps to avoid the destruction of the passivation effect of the tunneling layer by large-size metal particles, and the local metal microcrystals are electrically connected to the silicon substrate and the external metal gate line, which significantly reduces the loss of carrier transverse transmission and the carrier concentration between the silicon substrate and the tunneling layer interface, significantly improves the carrier transmission efficiency, and helps to significantly improve the photoelectric conversion efficiency of the solar cell. BRIEF DESCRIPTION OF DRAWINGS
[0061] Figure 1 The structure diagram of the solar cell provided for example 1 is shown.
[0062] Figure 2 The top view of the tunneling silicon oxide layer in the solar cell provided for example 1 is shown.
[0063] Figure 3A distribution diagram of the back passivation film in the solar cell provided for Example 1.
[0064] Figure 4 A structure diagram of the solar cell provided for Example 2.
[0065] Figure 5 A structure diagram of the solar cell provided for Example 3.
[0066] Figure 6 A structure diagram of the solar cell provided for Example 4.
[0067] Wherein, 100-n type silicon substrate; 101-tunneling silicon oxide layer; 102-n type polycrystalline silicon back field layer; 103-back passivation film; 103a-back passivation layer; 103b-hydrogenated silicon nitride anti-reflection layer; 103c-silicon oxynitride anti-reflection layer; 104-notch; 105-back silver electrode; 105a-back silver grid line layer; 105b-back silver particle layer; 105c-back silver microcrystalline layer; 106-light-receiving surface silver-aluminum electrode; 107-front anti-reflection layer; 108-front passivation layer; 109-p type emitter region; 200-n type silicon wafer; 201-tunneling SiO2 layer; 202a-p type doped polycrystalline silicon layer; 202b-n type doped polycrystalline silicon layer; 203-back passivation protective film; 204-window; 205-back negative electrode; 205a-back grid line layer; 205b-back particle layer; 205c-back microcrystalline layer; 206-back positive electrode; 207-front anti-reflection layer; 208-front insulating layer; 209-p type doped passivation region; 300-p type silicon substrate; 301-intermittent tunneling silicon oxide layer; 302-n type polycrystalline silicon emitter layer; 303-interface passivation film; 304-opening; 305-local back silver electrode; 305a-local back silver grid line layer; 305b-local back silver particle layer; 305c-local back silver microcrystalline layer; 306-local back aluminum electrode; 306a-local aluminum grid line layer; 306b-aluminum-silicon alloy layer; 307-front anti-reflection layer; 308-front passivation layer; 309-n type doped passivation region; 102a-first n type polycrystalline silicon back field layer; 102b-second n type polycrystalline silicon back field layer; 400-buffer layer. DETAILED DESCRIPTION
[0068] It should be understood that, in the description of the present application, the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features limited by "first", "second" and the like can explicitly or implicitly include one or more of the features. In the description of the present application, "a plurality of" means two or more, unless otherwise specified.
[0069] It should be noted that, in the description of the present application, unless otherwise specified and limited, the terms "provided", "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be connected inside two elements. For ordinary skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0070] The technical scheme of the present application is further illustrated by the specific embodiments.
[0071] In one embodiment, the present application provides a solar cell, comprising:
[0072] Silicon substrate.
[0073] Tunneling layer, the tunneling layer is located on the back surface of the silicon substrate, and has a plurality of notches.
[0074] Crystalline conductive layer, the crystalline conductive layer is arranged on the side surface of the tunneling layer away from the silicon substrate.
[0075] Back surface passivation film, the back surface passivation film is arranged on the side surface of the crystalline conductive layer away from the silicon substrate.
[0076] Metal electrode, the metal electrode is located on the back surface of the solar cell, the metal electrode comprises a metal grid line layer, a metal particle layer and a metal microcrystalline layer; wherein the metal grid line layer penetrates the back surface passivation film, the metal particle layer is located in the crystalline conductive layer and does not contact the tunneling layer, and the metal microcrystalline layer is in contact with the silicon substrate.
[0077] The metal particle layer and the metal microcrystal layer are distributed in the solar cell, which helps to avoid the damage of large-size metal particles to the passivation effect of the tunneling layer, and the local metal microcrystal layer is electrically connected with the silicon substrate and the metal gate line layer outside, which significantly reduces the loss of carrier transverse transmission, reduces the carrier concentration between the silicon substrate and the tunneling layer interface, significantly improves the carrier transmission efficiency, and helps to greatly improve the photoelectric conversion efficiency of the solar cell.
[0078] In the utility model, metal electrode can adopt silk screen printing metal paste sintering or laser induced sintering mode to form, and metal electrode burns through back passivation film and crystalline conductive layer ohmic contact in sintering process, and through controlling sintering temperature and depth, metal electrode can form metal particle layer and metal microcrystal layer in crystalline conductive layer.
[0079] In the utility model, crystalline conductive layer is prepared by PECVD (plasma enhanced chemical vapor deposition) process, and in-situ doping process is used to realize n-type or p-type.
[0080] Further, the size of the metal particle layer is 0.5-100 μm, for example, it can be 1 μm, 5 μm, 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm, etc.
[0081] Further, the size of the metal microcrystal layer is less than 200 nm, for example, it can be 1 nm, 2.5 nm, 5 nm, 10 nm, 15 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, 140 nm, 160 nm or 180 nm, etc.
[0082] It should be noted that the physical boundary of the metal gate line layer and the metal particle layer in the metal electrode can not be obvious, because the metal gate line layer itself is composed of multiple conductive particles of the paste at the microscopic level, and the size of the conductive particles of the paste is usually similar to the size of the metal particles. The part outside the crystalline conductive layer defined in the utility model belongs to the metal gate line layer, which is mainly used for penetrating the insulating passivation film to conduct electricity, and does not react with the crystalline conductive layer. The main part is the fusion bonding between the conductive particles of the paste. The metal particle layer is a metal alloy particle (for example, metal-silicon alloy) formed by eutectic reaction with the crystalline conductive layer (for example, polysilicon layer) during high-temperature treatment, which is a key part of reducing contact resistance, but large-size metal particles need to avoid contacting the tunneling layer to prevent the increase of saturation current density. The metal microcrystal layer is mainly a metal single layer recrystallized and precipitated, and when the smaller metal microcrystals are diffused to the silicon substrate, the balance of saturation current density and contact resistance can be achieved.
[0083] Further, the metal microcrystal layer is in contact with the silicon substrate through the aperture of the tunneling layer; or, the interface between the aperture of the tunneling layer and the silicon substrate is distributed with the metal microcrystal layer.
[0084] In the utility model, the metal microcrystal layer is in contact with the silicon substrate through the aperture of the tunneling layer, or the interface between the aperture and the silicon substrate is distributed with the metal microcrystal layer, which can avoid that the large-size metal particles damage the passivation effect of the tunneling layer, and the local metal microcrystal layer electrically connects the silicon substrate and the external metal gate line layer, thereby significantly reducing the loss of carrier transverse transmission.
[0085] Further, the width of the aperture is less than 200nm, for example, can be 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 120nm, 140nm, 160nm or 180nm, etc.
[0086] In the utility model, the aperture with the appropriate width forms an electric transmission channel and allows the backside carriers to pass through.
[0087] Further, a part of the crystalline conductive layer extends into the aperture and is in contact with the silicon substrate.
[0088] In the utility model, part of the photo-generated carriers enters the crystalline conductive layer due to the tunneling effect, and part of the photo-generated carriers is collected by the metal grains at the aperture, thereby improving the carrier transmission efficiency; and due to the current crowding effect, the carrier concentration at the interface between the tunneling layer and the silicon substrate is reduced, and the carrier recombination probability is reduced.
[0089] In the utility model, the crystalline conductive layer can recrystallize and extend into the aperture in the heat treatment such as annealing process, so as to realize the contact between the crystalline conductive layer and the silicon substrate through the aperture.
[0090] Further, the silicon substrate is an n-type silicon substrate or a p-type silicon substrate.
[0091] In the utility model, when the silicon substrate is a p-type silicon substrate, the crystalline conductive layer can be a p-type crystalline conductive layer (i.e. a backside layer) or an n-type crystalline conductive layer (i.e. an emitter); when the silicon substrate is an n-type silicon substrate, the crystalline conductive layer can be an n-type crystalline conductive layer (i.e. a backside layer) or a p-type crystalline conductive layer (i.e. an emitter).
[0092] Further, the crystalline conductive layer is an n-type crystalline conductive layer or a p-type crystalline conductive layer.
[0093] It should be noted that if the crystalline conductive layer is an n-type crystalline conductive layer, the doped element in the n-type crystalline conductive layer can be phosphorus element.
[0094] Further, the silicon substrate and the crystalline conductive layer have the same or opposite conductive types.
[0095] Further, the tunneling layer is any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer, and is preferably a silicon oxide layer.
[0096] In the utility model, the silicon oxide layer as the tunneling layer is beneficial to the selective tunneling of carriers.
[0097] Further, the thickness of the tunneling layer is d1, and 1nm < d1 ≤ 7nm, for example, 2nm, 2.5nm, 3nm, 3.2nm, 3.5nm, 4nm, 5nm, 6nm, or 7nm, etc.
[0098] Further, the crystalline conductive layer is a polysilicon layer or a silicon carbide layer.
[0099] Further, the thickness of the crystalline conductive layer is d2, and 50nm ≤ d2 ≤ 170nm, for example, 50nm, 70nm, 90nm, 100nm, 110nm, 130nm, 150nm, or 170nm, etc.
[0100] In the utility model, if d2 is less than 50nm, the electrode burn-through degree is deepened, and the silicon substrate is damaged; if d2 is greater than 170nm, the optical performance of the back surface is seriously affected.
[0101] Further, the thickness of the tunneling layer satisfies 2nm < d1 ≤ 5nm, for example, 2.5nm, 3nm, 3.2nm, 3.5nm, 4nm, or 5nm, etc.
[0102] In the utility model, if d1 is less than 2nm, the interface passivation effect is poor; if d1 is greater than 5nm, the carrier transmission is seriously blocked, and the efficiency is obviously reduced.
[0103] Further, the thickness of the crystalline conductive layer satisfies 60nm ≤ d2 ≤ 100nm, for example, 60nm, 70nm, 80nm, 90nm, or 100nm, etc.
[0104] Further, the back surface passivation film is a single-layer back surface passivation film or at least 2 layers of back surface passivation films, for example, 2 layers, 3 layers, 4 layers, or 5 layers, etc.
[0105] Further, the at least 2 layers of back surface passivation films include a back surface passivation layer and a back surface anti-reflection layer which are stacked.
[0106] Further, the back surface passivation layer is a silicon oxynitride layer.
[0107] The silicon oxynitride layer has fixed positive charges, and the presence of oxygen atoms can adjust the electrical properties of the back passivation film, reduce the n-type surface state density, and reduce the carrier recombination.
[0108] Further, the backside antireflection layer is a hydrogenated silicon nitride antireflection layer and / or a silicon oxynitride antireflection layer.
[0109] Further, the thickness of the backside passivation layer is less than the thickness of the antireflection layer.
[0110] In the utility model, the thickness of backside passivation layer is less than the thickness of antireflection layer, and this is conducive to adjusting the antireflection effect.
[0111] Further, the backside antireflection layer comprises a hydrogenated silicon nitride antireflection layer and a silicon oxynitride antireflection layer which are sequentially stacked in a direction away from the backside of the silicon substrate.
[0112] In the utility model, the hydrogenated silicon nitride antireflection layer contains high-concentration hydrogen, and after heat treatment, the hydrogen diffuses to the silicon oxynitride antireflection layer and the silicon substrate, and the surface defects are passivated.
[0113] Further, the thickness of the backside passivation layer is less than or equal to 10 nm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm or 9 nm, etc.
[0114] In the utility model, the thickness of the backside passivation layer is less than or equal to 10 nm, which is conducive to the diffusion of hydrogen atoms in the hydrogenated silicon nitride antireflection layer, and further improves the passivation effect.
[0115] Further, in the backside antireflection layer, the thickness of the hydrogenated silicon nitride antireflection layer is 30-70 nm, for example, it can be 30 nm, 40 nm, 50 nm, 60 nm or 70 nm, etc.
[0116] Further, in the backside antireflection layer, the thickness of the silicon oxynitride antireflection layer is 20-60 nm, for example, it can be 20 nm, 30 nm, 40 nm, 50 nm or 60 nm, etc.
[0117] In the utility model, if the thickness of the silicon oxynitride antireflection layer in the backside antireflection layer is less than 20 nm, the passivation effect is poor, and if the thickness of the silicon oxynitride antireflection layer is greater than 60 nm, it will cause the optical performance to decrease.
[0118] Further, the front side of the silicon substrate is provided with an emitter region, and the conductivity type of the emitter region is p-type.
[0119] It should be noted that the silicon substrate is n-type, and the conductivity type of the emitter region is p-type, which is formed by diffusing p-type dopants into the silicon substrate, such as boron dopants.
[0120] Further, the emitter region is located inside or outside the front surface of the silicon substrate.
[0121] Further, the solar cell further comprises a front surface passivation film, which is arranged on the emitter region.
[0122] Further, the front surface passivation film comprises a front surface passivation layer and a front surface anti-reflection layer arranged in a stack along a direction away from the front surface of the silicon substrate.
[0123] Further, the front surface passivation layer is an aluminum oxide layer.
[0124] It should be noted that the front surface passivation layer comprises an aluminum oxide layer with high-density surface-fixed negative charges.
[0125] Further, the front surface anti-reflection layer is any one or a combination of at least two of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer or a magnesium fluoride layer.
[0126] Further, the solar cell further comprises a light-receiving surface metal electrode, which is in contact with the emitter region through the front surface passivation film.
[0127] Further, the light-receiving surface metal electrode is any one or a combination of at least two of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode or a palladium electrode, preferably a silver-aluminum electrode.
[0128] In the utility model, the silver-aluminum electrode is in contact with the emitter region (for example, the silver-aluminum electrode is in contact with the p-type emitter region to form a p+ doped region), and the contact resistance can be reduced.
[0129] Further, the crystalline conductive layer comprises n-type crystalline conductive layers and p-type crystalline conductive layers arranged at intervals along the horizontal plane of the silicon substrate, and the isolation region between adjacent n-type crystalline conductive layers and p-type crystalline conductive layers is covered with the back surface passivation film.
[0130] Further, the metal electrode comprises a positive electrode and a negative electrode, the positive electrode is in contact with the p-type crystalline conductive layer through the back surface passivation film, and the negative electrode is in contact with the n-type crystalline conductive layer through the back surface passivation film.
[0131] In the utility model, the solar cell back surface structure defined above sets the positive and negative electrodes of the cell on the back surface of the cell, and the light-shielding area of the front surface of the cell can be reduced.
[0132] Further, the positive and negative electrodes are each independently any one or a combination of at least two of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode or a palladium electrode.
[0133] Further, the back surface of the silicon substrate is provided with a plurality of n-type conductive regions and a plurality of p-type conductive regions, the plurality of n-type conductive regions and the plurality of p-type conductive regions are arranged at intervals along the horizontal direction of the back surface of the silicon substrate, and form a height difference along the vertical direction of the back surface of the silicon substrate.
[0134] In the utility model, the n-type conductive region and the p-type conductive region form a height difference isolation, which is beneficial to industrial production.
[0135] In the utility model, the n-type conductive region is originally covered on the back surface of the silicon substrate by the whole tunneling layer and crystalline conductive layer, then the local removal is carried out by adopting laser technology or mask etching mode, so as to form the alternating arrangement opening on the back surface of the silicon substrate, the opening exposes the silicon substrate to form the p-type conductive region naturally, and the p-type conductive region and the n-type conductive region form a height difference isolation, which is beneficial to industrial production.
[0136] Further, the tunneling layer and the crystalline conductive layer are arranged in the n-type conductive region.
[0137] Further, the back passivation film is also arranged on the back surface of the silicon substrate of the p-type conductive region, and covers the sidewall of the tunneling layer and the crystalline conductive layer.
[0138] Further, the p-type conductive region is provided with an aluminum electrode, the aluminum electrode includes an aluminum gate line layer and an aluminum silicon alloy layer, the aluminum gate line layer is located on the surface of the p-type conductive region and penetrates the back passivation film, and the aluminum silicon alloy layer is in contact with the silicon substrate.
[0139] In the utility model, the aluminum silicon alloy is sintered into the silicon substrate by the aluminum electrode, reacts with the silicon substrate to form the aluminum silicon alloy, has the heavy doping effect of p+, can realize ohmic contact, is beneficial to reducing the contact resistance, improves the carrier transport rate, and the cost is also lower.
[0140] It should be noted that the p-type conductive region does not have a tunneling layer and a tunneling layer notch, but the back passivation film of the p-type conductive region is provided with an opening, and the opening can be a laser opening or an aluminum paste sintering penetration back passivation film.
[0141] Further, the crystalline conductive layer includes a first crystalline conductive layer and a second crystalline conductive layer arranged in layers along the direction away from the back surface of the silicon substrate.
[0142] Further, a buffer layer is arranged between the first crystalline conductive layer and the second crystalline conductive layer.
[0143] The buffer layer is arranged to buffer and avoid over-diffusion of the doping elements in the second crystalline conductive layer to the first crystalline conductive layer, and reduce over-diffusion of the doping elements in the silicon substrate.
[0144] Further, the buffer layer is any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or an aluminum oxide layer.
[0145] Further, the buffer layer has a plurality of notches, and the density of the notches in the buffer layer is greater than the density of the notches in the tunneling layer.
[0146] In the utility model, the density of the notches in the buffer layer is greater than the density of the notches in the tunneling layer, that is, the compactness of the buffer layer is less than the compactness of the tunneling layer.
[0147] It should be noted that, since the crystalline conductive layer needs high conductivity, the second crystalline conductive layer has high defect tolerance, which is conducive to industrialized manufacturing.
[0148] Further, the doping concentration of the doping elements in the first crystalline conductive layer is less than the doping concentration of the doping elements in the second crystalline conductive layer. This design is conducive to forming a back high-low junction structure.
[0149] Further, the metal particle layer is a metal alloy layer, and the metal microcrystal layer is a metal single layer.
[0150] Further, the metal electrode is any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode or a palladium electrode, or a combination of at least two thereof, preferably a silver electrode.
[0151] In the utility model, the silver powder in the silver paste has high sintering activity, the silver atoms diffuse quickly at high temperature, and are dissolved in the glass phase region near the silver particles, and the glass phase region is easily recrystallized to precipitate silver microcrystals during the cooling process. The silver microcrystals penetrate the glass phase during the recrystallization process, and diffuse and contact the silicon substrate.
[0152] Embodiment 1
[0153] The embodiment provides a solar cell, a structure diagram of which is shown in Figure 1 , comprising:
[0154] An n-type silicon substrate 100.
[0155] A tunneling silicon oxide layer 101 is located on the back surface of the n-type silicon substrate 100, and has a plurality of notches 104, as shown in Figure 2 ; the thickness d1 of the tunneling silicon oxide layer 101 is 2-5 nm, the thickness of the tunneling silicon oxide layer 101 at the notch 104 is less than 1 nm, and the width of the notch 104 is less than 200 nm.
[0156] n-type polysilicon back field layer 102 is arranged on the side surface of the tunneling silicon oxide layer 101 away from the n-type silicon substrate 100; the thickness d2 of the n-type polysilicon back field layer 102 is 60-100 nm; a part of the n-type polysilicon back field layer 102 extends into the notch 104 and contacts the n-type silicon substrate 100.
[0157] back surface passivation film 103 is arranged on the side surface of the n-type polysilicon back field layer 102 away from the n-type silicon substrate 100, and a distribution diagram thereof is shown in Figure 3 The back surface passivation film 103 includes a back surface passivation layer 103a and a back surface anti-reflection layer arranged in layers; the back surface passivation layer 103a is a silicon oxynitride layer with a thickness of 1-10 nm; the back surface anti-reflection layer includes a hydrogenated silicon nitride anti-reflection layer 103b and a silicon oxynitride anti-reflection layer 103c arranged in layers in turn away from the back surface of the n-type silicon substrate 100; the thickness of the hydrogenated silicon nitride anti-reflection layer 103b is 30-70 nm, and the thickness of the silicon oxynitride anti-reflection layer 103c is 20-60 nm.
[0158] The back surface silver electrode 105 is divided into a back surface silver grid line layer 105a, a back surface silver particle layer 105b and a back surface silver microcrystal layer 105c; the back surface silver grid line layer 105a is located on the back surface of the solar cell and penetrates the back surface passivation film 103; the back surface silver particle layer 105b is located in the n-type polysilicon back field layer 102 and does not contact the tunneling silicon oxide layer 101; the back surface silver microcrystal layer 105c contacts the n-type silicon substrate 100 through the notch 104 of the tunneling silicon oxide layer 101, so that the back surface silver microcrystal layer 105c is distributed at the interface between the notch 104 and the n-type silicon substrate 100; the size of the back surface silver particle layer 105b is 1-100 μm, and the size of the back surface silver microcrystal layer 105c is less than 200 nm.
[0159] The p-type emitter region 109 is arranged on the outer side of the front surface of the n-type silicon substrate 100.
[0160] The front surface passivation film includes a front surface passivation layer 108 and a front surface anti-reflection layer 107 arranged in layers away from the front surface of the n-type silicon substrate 100; the front surface passivation layer 108 is an aluminum oxide layer, and the front surface anti-reflection layer 107 is a silicon nitride layer.
[0161] The light-receiving surface silver-aluminum electrode 106 contacts the p-type emitter region 109 through the front surface passivation film to form a p+ doped region.
[0162] The solar cell provided in the embodiment allows nanoscale silver microcrystals to contact the silicon substrate through the tunneling layer, thereby reducing the contact resistance; and avoids micron-scale silver particles from contacting the tunneling layer, thereby reducing the saturation current of the back surface of the cell, and thus improving the fill factor and conversion efficiency of the solar cell.
[0163] Embodiment 2
[0164] The embodiment provides a solar cell, a structural schematic diagram of which is shown in the figure, comprising: Figure 4
[0165] An n-type silicon substrate, also referred to as an n-type silicon wafer 200.
[0166] A tunneling SiO2 layer 201 is located on the back surface of the n-type silicon wafer 200 and has a plurality of notches, also referred to as windows 204; the thickness d1 of the tunneling SiO2 layer 201 is 2-5 nm, the thickness of the tunneling SiO2 layer 201 at the window 204 is less than 1 nm, and the width of the window 204 is less than 200 nm.
[0167] An n-type doped polysilicon layer 202b and a p-type doped polysilicon layer 202a are arranged at intervals and are arranged on the side surface of the tunneling SiO2 layer 201 away from the n-type silicon wafer 200; the thicknesses of the n-type doped polysilicon layer 202b and the p-type doped polysilicon layer 202a are both 60-100 nm; a part of the n-type doped polysilicon layer 202b and the p-type doped polysilicon layer 202a extends into different windows 204 and is in contact with the n-type silicon wafer 200.
[0168] A back passivation protective film 203 is arranged on the side surface of the n-type doped polysilicon layer 202b and the p-type doped polysilicon layer 202a away from the n-type silicon wafer 200, and the isolation area between adjacent n-type doped polysilicon layers 202b and p-type doped polysilicon layers 202a is covered with the back passivation protective film 203; the back passivation protective film 203 comprises a back passivation layer and a back anti-reflection layer arranged in layers, the back passivation layer is a silicon oxynitride layer with a thickness of 1-10 nm, and the back anti-reflection layer comprises a hydrogenated silicon nitride anti-reflection layer and a silicon oxynitride anti-reflection layer arranged in layers in the direction away from the back surface of the n-type silicon substrate, the thickness of the hydrogenated silicon nitride anti-reflection layer is 30-70 nm, and the thickness of the silicon oxynitride anti-reflection layer is 20-60 nm.
[0169] The back positive electrode 206 and the back negative electrode 205, the back positive electrode 206 contacts the p-type doped polysilicon layer 202a through the back passivation protection film 203, and the back negative electrode 205 contacts the n-type doped polysilicon layer 202b through the back protection film; wherein the back positive electrode 206 is an aluminum electrode, which is divided into a back aluminum gate line layer, a back aluminum particle layer and a back aluminum microcrystal layer, the back aluminum gate line layer is located on the back of the solar cell and penetrates the back passivation protection film 203, the back aluminum particle layer is located in the p-type doped polysilicon layer 202a and does not contact the tunneling SiO2 layer 201, the back aluminum microcrystal layer contacts the n-type silicon wafer 200 through the window 204 of the tunneling SiO2 layer 201, so that the back aluminum microcrystal layer is distributed at the interface between the window 204 and the n-type silicon wafer 200, the size of the back aluminum particle layer is 1-100 μm, and the size of the back aluminum microcrystal layer is less than 200 nm; the back negative electrode 205 is a silver electrode, which is divided into a back gate line layer 205a, a back particle layer 205b and a back microcrystal layer 205c; wherein the back gate line layer 205a is located on the back of the solar cell and penetrates the back passivation protection film 203, the back particle layer 205b is located in the n-type doped polysilicon layer 202b and does not contact the tunneling SiO2 layer 201, and the back microcrystal layer 205c contacts the n-type silicon wafer 200 through the window 204 of the tunneling SiO2 layer 201, so that the back microcrystal layer 205c is distributed at the interface between the window 204 and the n-type silicon wafer 200; the size of the back particle layer 205b is 1-100 μm, and the size of the back microcrystal layer 205c is less than 200 nm.
[0170] The p-type doped passivation region 209 is arranged outside the front surface of the n-type silicon wafer 200.
[0171] The front passivation film includes a front insulating layer 208 and a front anti-reflection layer 207 arranged in a stack along a direction away from the front surface of the n-type silicon wafer 200; wherein the front insulating layer 208 is an aluminum oxide layer, and the front anti-reflection layer 207 is a silicon nitride layer.
[0172] Compared with the solar cell of the embodiment 1, the positive electrode and the negative electrode of the solar cell provided in the embodiment are arranged on the back of the solar cell, so that the light shielding area of the front surface of the solar cell can be reduced; in addition, the isolation region can avoid the contact between the p-type doped polysilicon layer and the n-type doped polysilicon layer on the back of the solar cell, so that the carrier recombination is reduced.
[0173] Embodiment 3
[0174] The solar cell provided in the embodiment has a structure as shown in the structural schematic diagram Figure 5 , and includes:
[0175] The p-type silicon substrate 300 has a plurality of n-type conductive regions and a plurality of p-type conductive regions on the back surface thereof, and the plurality of n-type conductive regions and the plurality of p-type conductive regions are arranged horizontally and spaced apart from each other on the back surface of the p-type silicon substrate 300, and a height difference is formed between the plurality of n-type conductive regions and the plurality of p-type conductive regions.
[0176] The discontinuous tunneling silicon oxide layer 301 is located in the n-type conductive region on the back surface of the p-type silicon substrate 300, and has a plurality of notches, which are also referred to as openings 304; the thickness d1 of the discontinuous tunneling silicon oxide layer 301 is 2-5 nm, the thickness of the discontinuous tunneling silicon oxide layer 301 at the openings 304 is less than 1 nm, and the width of the openings 304 is less than 200 nm.
[0177] The n-type polysilicon emitter layer 302 is arranged on the side surface of the discontinuous tunneling silicon oxide layer 301 away from the p-type silicon substrate 300; the thickness d2 of the n-type polysilicon emitter layer 302 is 60-100 nm; and a part of the n-type polysilicon emitter layer 302 extends into the openings 304 to contact the p-type silicon substrate 300.
[0178] The interface passivation film 303 is arranged on the side surface of the n-type polysilicon emitter layer 302 away from the p-type silicon substrate 300, is also arranged on the back surface of the p-type silicon substrate 300 in the p-type conductive region, and covers the side walls of the tunneling layer and the n-type polysilicon emitter layer 302; the interface passivation film 303 comprises a back surface passivation layer and a back surface anti-reflection layer arranged in layers; the back surface passivation layer is a silicon oxynitride layer with a thickness of 1-10 nm; the back surface anti-reflection layer comprises a hydrogenated silicon nitride anti-reflection layer and a silicon oxynitride anti-reflection layer arranged in layers in the direction away from the back surface of the n-type silicon substrate; the thickness of the hydrogenated silicon nitride anti-reflection layer is 30-70 nm, and the thickness of the silicon oxynitride anti-reflection layer is 20-60 nm.
[0179] The local back surface silver electrode 305 is divided into a local back surface silver grid line layer 305a, a local back surface silver particle layer 305b, and a local back surface silver microcrystal layer 305c; the local back surface silver grid line layer 305a is located on the back surface of the solar cell and penetrates the interface passivation film 303, the local back surface silver particle layer 305b is located in the n-type polysilicon emitter layer 302 and does not contact the discontinuous tunneling silicon oxide layer 301, and the local back surface silver microcrystal layer 305c contacts the p-type silicon substrate 300 through the openings 304 of the discontinuous tunneling silicon oxide layer 301, so that the local back surface silver microcrystal layer 305c is distributed at the interface between the openings 304 and the p-type silicon substrate 300; the size of the local back surface silver particle layer 305b is 1-100 μm, and the size of the local back surface silver microcrystal layer 305c is less than 200 nm.
[0180] The local backside aluminum electrode 306, provided on the p-type conductive region, comprises a local aluminum grid line layer 306a and an aluminum-silicon alloy layer 306b. The local aluminum grid line layer 306a is located on the surface of the p-type silicon substrate 300 and penetrates the interface passivation film 303. The aluminum-silicon alloy layer 306b is located inside the p-type silicon substrate 300.
[0181] The n-type doped passivation region 309 is provided on the outer side of the front surface of the p-type silicon substrate 300.
[0182] The front passivation film comprises a front passivation layer 308 and a front anti-reflection layer 307 arranged in a stack along a direction away from the front surface of the p-type silicon substrate 300. The front passivation layer 308 is an aluminum oxide layer, and the front anti-reflection layer 307 is a silicon nitride layer.
[0183] Compared with the solar cell of Embodiment 2, the solar cell of the present embodiment has a local n-type polysilicon layer as the n-type region and a local p-type silicon substrate as the p-type region on the back surface of the cell, and an aluminum electrode is used to contact the p-type region to form a p-type back field. Therefore, no additional back field manufacturing process is needed, and the manufacturing process is relatively simple.
[0184] Embodiment 4
[0185] The solar cell provided in the present embodiment has a structure as shown in Figure 6 The difference between the present embodiment and Embodiment 1 is that the n-type polysilicon back field layer of the present embodiment comprises a first n-type polysilicon back field layer 102a and a second n-type polysilicon back field layer 102b arranged in a stack along a direction away from the back surface of the n-type silicon substrate. The phosphorus doping concentration of the second n-type polysilicon back field layer 102b is greater than that of the first n-type polysilicon back field layer 102a. A buffer layer 400 is provided between the first n-type polysilicon back field layer 102a and the second n-type polysilicon back field layer 102b. The buffer layer 400 is a silicon oxide layer, has a plurality of gaps, and has a higher density of gaps than the tunneling silicon oxide layer. The thickness of the buffer layer 400 is 1-5 nm. The backside silver particle layer is located in the first n-type polysilicon back field layer 102a and the second n-type polysilicon back field layer 102b and does not contact the tunneling silicon oxide layer.
[0186] The remaining structure is consistent with that of Embodiment 1.
[0187] In the solar cell provided in the present embodiment, the added buffer layer can reduce the excessive diffusion of the polysilicon layer in the silicon substrate and improve the doping concentration distribution of the polysilicon layer to form a high-low junction, thereby further improving the carrier transport efficiency.
[0188] The applicant states that the process method of the utility model is illustrated by the above-mentioned embodiments, but the utility model is not limited to the above-mentioned process steps, namely, it does not mean that the utility model must rely on the above-mentioned process steps to be implemented. The skilled in the art should understand that any improvement of the utility model, equivalent replacement of the raw materials selected by the utility model and addition of auxiliary components, selection of specific modes and the like all fall within the protection scope and the disclosure scope of the utility model.
Claims
1. A solar cell, characterized by, The solar cell comprises: a silicon substrate; a tunneling layer located on the back surface of the silicon substrate and having a plurality of notches; a crystalline conductive layer provided on the side surface of the tunneling layer away from the silicon substrate; a back surface passivation film provided on the side surface of the crystalline conductive layer away from the silicon substrate; a metal electrode located on the back surface of the solar cell, the metal electrode comprising a metal grid layer, a metal particle layer and a metal microcrystal layer; wherein the metal grid layer penetrates through the back surface passivation film, the metal particle layer is located in the crystalline conductive layer and does not contact the tunneling layer, and the metal microcrystal layer contacts the silicon substrate.
2. The solar cell according to claim 1, characterized in that, The particle size of the metal particle layer is 0.5-10 μm; The microcrystal size of the metal microcrystal layer is less than 200 nm.
3. The solar cell according to claim 1, characterized in that, The metal microcrystal layer contacts the silicon substrate through the notches of the tunneling layer; or the interface between the notches of the tunneling layer and the silicon substrate is distributed with the metal microcrystal layer.
4. The solar cell of claim 1, wherein The width of the notches is less than 200 nm; A part of the crystalline conductive layer extends into the notches and contacts the silicon substrate.
5. The solar cell of claim 1, wherein The silicon substrate is an n-type silicon substrate or a p-type silicon substrate; The crystalline conductive layer is an n-type crystalline conductive layer or a p-type crystalline conductive layer; The silicon substrate and the crystalline conductive layer have the same or opposite conductive types.
6. The solar cell of claim 1, wherein The tunneling layer is any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or an aluminum oxide layer; The thickness of the tunneling layer is d1, and 1 nm < d1 ≤ 7 nm; The crystalline conductive layer is a polycrystalline silicon layer or a silicon carbide layer; The thickness of the crystalline conductive layer is d2, and 50 nm ≤ d2 ≤ 170 nm.
7. The solar cell according to claim 6, characterized in that, The thickness of the tunneling layer satisfies 2 nm < d1 ≤ 5 nm; The thickness of the crystalline conductive layer satisfies 60 nm ≤ d2 ≤ 100 nm.
8. The solar cell of claim 1, wherein, The back surface passivation film is a single-layer back surface passivation film or at least two layers of back surface passivation films; The at least two layers of back surface passivation films comprise a back surface passivation layer and a back surface anti-reflection layer which are stacked; The back surface passivation layer is a silicon oxynitride layer; The back surface anti-reflection layer is a hydrogenated silicon nitride anti-reflection layer and / or a silicon oxynitride anti-reflection layer.
9. The solar cell of claim 8, wherein, The thickness of the back surface passivation layer is less than the thickness of the anti-reflection layer; The back surface anti-reflection layer comprises a hydrogenated silicon nitride anti-reflection layer and a silicon oxynitride anti-reflection layer which are sequentially stacked away from the back surface of the silicon substrate; The thickness of the back surface passivation layer is less than or equal to 10 nm; In the back surface anti-reflection layer, the thickness of the hydrogenated silicon nitride anti-reflection layer is 30-70 nm; In the back surface anti-reflection layer, the thickness of the silicon oxynitride anti-reflection layer is 20-60 nm.
10. The solar cell of claim 1, wherein, The front surface of the silicon substrate is provided with an emitter region, and the conductive type of the emitter region is p-type; The emitter region is located inside or outside the front surface of the silicon substrate; The solar cell further comprises a front surface passivation film provided on the emitter region; The front surface passivation film comprises a front surface passivation layer and a front surface anti-reflection layer which are stacked away from the front surface of the silicon substrate; The front surface passivation layer is an aluminum oxide layer; The front anti-reflective layer is any one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a magnesium fluoride layer, or a combination of at least two thereof.
11. The solar cell of claim 10, wherein, The solar cell further comprises a light-receiving surface metal electrode in contact with the emitter region through the front passivation film. The light-receiving surface metal electrode is any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode.
12. The solar cell of claim 1, wherein, The crystalline conductive layer comprises n-type and p-type crystalline conductive layers arranged at intervals along the horizontal plane of the silicon substrate, and an isolation region is arranged between adjacent n-type and p-type crystalline conductive layers, and the isolation region is covered with the back passivation film. The metal electrode comprises a positive electrode and a negative electrode, the positive electrode is in contact with the p-type crystalline conductive layer through the back passivation film, and the negative electrode is in contact with the n-type crystalline conductive layer through the back passivation film.
13. The solar cell of claim 1, wherein, The back surface of the silicon substrate is provided with a plurality of n-type conductive regions and a plurality of p-type conductive regions, which are arranged at intervals along the horizontal direction of the back surface of the silicon substrate and form a height difference along the vertical direction of the back surface of the silicon substrate. The tunneling layer and the crystalline conductive layer are arranged in the n-type conductive region. The back passivation film is also arranged on the back surface of the silicon substrate of the p-type conductive region, and covers the sidewalls of the tunneling layer and the crystalline conductive layer.
14. The solar cell of claim 13, wherein, The p-type conductive region is provided with an aluminum electrode, which comprises an aluminum gate line layer and an aluminum-silicon alloy layer, the aluminum gate line layer is located on the surface of the p-type conductive region and penetrates through the back passivation film, and the aluminum-silicon alloy layer is in contact with the silicon substrate.
15. The solar cell of claim 1, wherein, The crystalline conductive layer comprises a first crystalline conductive layer and a second crystalline conductive layer arranged in layers along the direction away from the back surface of the silicon substrate. A buffer layer is arranged between the first and second crystalline conductive layers.
16. The solar cell of claim 15, wherein, The buffer layer is any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer. The buffer layer has a plurality of notches, and the density of the notches in the buffer layer is greater than the density of the notches in the tunneling layer.
17. The solar cell of claim 1, wherein, The metal particle layer is a metal alloy layer, and the metal microcrystal layer is a metal elemental layer.
18. The solar cell of claim 1, wherein, The metal electrode is any one of a silver electrode, an aluminum electrode, a copper electrode, a nickel electrode, a platinum electrode, a gold electrode, or a palladium electrode, or a combination of at least two thereof.