Semiconductor device

Abstract

The vertically stacked semiconductor device provided by the embodiment of the utility model comprises an intermediate redistribution circuit layer connecting pad positioned below a plurality of bump structures. The intermediate redistribution layer pad is located between the first semiconductor substrate and the plurality of bump structures. The bump structure includes a metal layer and a barrier layer having lower solder wettability between the metal layer and the intermediate redistribution layer pad. The barrier layer may limit solder wetting along sidewalls of the bump structure to minimize solder bridging and other defects. In some embodiments, the intermediate redistribution layer pads may have relatively low solder wettability to minimize solder defects. Characteristics of the intermediate redistribution layer pads and the bump structures may be controlled to improve flatness characteristics of the bump structures.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] The semiconductor industry continues to develop due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.).

[0003] In addition to smaller electronic components, improvements to component packaging have also been developed in an effort to provide smaller packages that occupy less area than previous packages. Example approaches include quad flat package (QFP), pin gate array (PGA), ball gate array (BGA), flip chip (FC), three-dimensional integrated circuit (3DIC), wafer level package (WLP), package on package (PoP), system on chip (SoC), or system integrated circuit (SoC) devices. Some of these three-dimensional devices are fabricated by placing chips on chips. These three-dimensional devices provide improved integration density and other advantages due to the reduced interconnect length between stacked chips. However, there are also many challenges associated with three-dimensional devices. SUMMARY

[0004] A semiconductor device includes a first device structure and a second device structure. The first device structure includes a first semiconductor substrate, an intermediate redistribution layer pad, and a plurality of bump structures electrically connected to the intermediate redistribution layer pad, wherein the intermediate redistribution layer pad is between the first semiconductor substrate and the plurality of bump structures. Each of the plurality of bump structures includes a metal layer and a barrier layer, wherein the barrier layer is between the metal layer and the intermediate redistribution layer pad, and a solder wetting property of the metal layer is greater than a solder wetting property of the barrier layer. The second device structure includes a second semiconductor substrate and a plurality of second bonding structures. A plurality of solder joints are between the metal layer of the plurality of bump structures of the first device structure and the plurality of second bonding structures of the second device structure.

[0005] The semiconductor device of this embodiment includes a first device structure and a second device structure. The first device structure includes: a first semiconductor substrate; an intermediate redistribution layer pad; and a plurality of bump structures electrically connected to the intermediate redistribution layer pad, wherein the intermediate redistribution layer pad is located between the first semiconductor substrate and the plurality of bump structures, each of the plurality of bump structures includes a metal layer, and the solder wettability of the metal layer of each of the plurality of bump structures is greater than the solder wettability of the intermediate redistribution layer pad. The second device structure includes a second semiconductor substrate and a plurality of second bonding structures. A plurality of solder joints are located between the metal layers of the plurality of bump structures of the first device structure and the plurality of second bonding structures of the second device structure. Attached Figure Description

[0006] This disclosure can be better understood when read in conjunction with the accompanying drawings in the following detailed description. It should be emphasized that, according to industry standard practice, the features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion. Furthermore, it should be emphasized that the drawings only show typical embodiments of the present invention and should not be considered as limiting the scope of the claim, as the present invention can be equally applied to other embodiments.

[0007] Figure 1A This is a top view of a first semiconductor device structure according to various embodiments of the present disclosure.

[0008] Figure 1B It is along Figure 1A The vertical cross-sectional view of the semiconductor device structure taken by line A-A' in the figure.

[0009] Figure 1C This is a top view of a second semiconductor device structure according to various embodiments of the present disclosure.

[0010] Figure 1D It is along Figure 1C The vertical cross-sectional view of the second semiconductor device structure taken by line B-B' in the figure.

[0011] Figure 1E This is a vertical cross-sectional view showing a second semiconductor device structure aligned on a first semiconductor device structure according to various embodiments of the present disclosure.

[0012] Figure 1F This is a vertical cross-sectional view of a vertically stacked semiconductor device according to various embodiments of the present disclosure.

[0013] Figure 2A This is a vertical cross-sectional view showing a second semiconductor device structure aligned on a first semiconductor device structure according to another embodiment of the present disclosure.

[0014] Figure 2B is a vertical cross-sectional view of a vertically stacked semiconductor device according to another embodiment of the present disclosure.

[0015] Figure 3A is a vertical cross-sectional view showing a second semiconductor device structure aligned on a first semiconductor device structure according to another embodiment of the present disclosure.

[0016] Figure 3B is a vertical cross-sectional view of a vertically stacked semiconductor device according to another embodiment of the present disclosure.

[0017] Figure 4A is a vertical cross-sectional view showing a second semiconductor device structure aligned on a first semiconductor device structure according to another embodiment of the present disclosure.

[0018] Figure 4B is a vertical cross-sectional view of a vertically stacked semiconductor device according to another embodiment of the present disclosure.

[0019] Figure 5A is a top view of a first semiconductor device structure according to various embodiments of the present disclosure.

[0020] Figure 5B is a vertical cross-sectional view of the first semiconductor device structure taken along line C-C’ in Figure 5A

[0021] is a flowchart showing a method of fabricating a vertically stacked semiconductor device according to an embodiment of the present disclosure. Figure 6

[0022] is a flowchart showing a method of fabricating a vertically stacked semiconductor device according to another embodiment of the present disclosure. Figure 7

[0023] is a flowchart showing a method of fabricating a vertically stacked semiconductor device according to another embodiment of the present disclosure. Figure 8

[0024] is a flowchart showing a method of fabricating a bonding structure including an intermediate re-distribution layer pad and a bump structure according to an embodiment of the present disclosure. Figure 9 DETAILED DESCRIPTION

[0025] ​The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the present application. Specific examples of components and configurations are described herein in order to provide a thorough description of the illustrative embodiments. It will be apparent, however, to one skilled in the art that the application can be practiced without the specific details presented herein. In other instances, well-known components or methods are not described in detail in order to avoid obscuring the present application. For example, in the following description, forming a first feature over or on a second feature can include embodiments in which the first feature and the second feature are formed in direct contact, and can also include embodiments in which additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not be in direct contact. In addition, the present disclosure can repeat reference numerals and / or letters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0026] In addition, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Unless otherwise noted, each component having a same reference numeral has a same material composition and a thickness within a same range of thicknesses.

[0027] Various embodiments disclosed herein are related to semiconductor devices, and in particular, to vertically stacked semiconductor devices including at least one semiconductor die stacked on and bonded to a second device structure. The second device structure can be, for example, another semiconductor die or semiconductor wafer. The at least one semiconductor die can be vertically stacked in, for example, a system on integrated circuit (SoIC), chip on wafer on substrate (CoWoS), chip on wafer (CoW), etc. architecture. Such vertically stacked semiconductor devices can increase device density that can occupy a given planar area or "footprint."

[0028] A semiconductor die can include a semiconductor material substrate, such as a silicon substrate. The semiconductor material substrate can have a plurality of circuitry members and components formed on and / or within the semiconductor material. Semiconductor dies are typically fabricated by sequentially depositing materials for insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate (e.g., a wafer), patterning each material layer using photolithography to form integrated circuits, and separating each die from the substrate, for example, by sawing (e.g., dicing) along a dicing line between integrated circuits.

[0029] A vertically stacked semiconductor device can be formed by placing a semiconductor device structure on another semiconductor device structure. The semiconductor device structure can be, for example, a semiconductor die, a semiconductor wafer, or a combination thereof (e.g., a semiconductor die on a semiconductor wafer). A bonding process can be used to bond a bonding structure on one semiconductor device structure to a corresponding bonding structure on another semiconductor device structure to form the vertically stacked semiconductor device.

[0030] In some embodiments, micro-bump bonding techniques can be used to bond semiconductor device structures to form a vertically stacked semiconductor device. In such bonding techniques, an array of micro-bump structures, which can include metal (e.g., Cu) pillars with a cap, can be formed on a semiconductor device structure. The semiconductor device structure including the micro-bump structures can then be aligned with another semiconductor device structure, and the two semiconductor device structures can be brought into contact such that the micro-bump structures can contact corresponding bonding structures (e.g., metal pillars or bonding pads) on the other semiconductor device structure. An electrical and mechanical bond between the two device structures can then be formed using a reflow process.

[0031] In many cases, a vertically stacked semiconductor device will include different types of interconnects between the corresponding semiconductor device structures. For example, a vertically stacked semiconductor device can include one or more first sets of interconnects to provide die-to-die (D2D) communication bandwidth between the semiconductor device structures, and one or more second sets of interconnects for power delivery between the semiconductor device structures. These different types of interconnects can require different sizes (i.e., critical dimensions (CD)) and / or different spacing (i.e., pitch) between the bonding structures used to bond the semiconductor device structures. Accordingly, a “hybrid” micro-bump technique can be used in which micro-bump structures with different critical dimensions (CD) and / or pitch to support the different types of interconnects can be formed on the semiconductor device structures. However, a disadvantage of this approach is that simultaneously forming different types of micro-bump structures (e.g., through an electro-deposition process) can result in micro-bump structures with low degree of co-planarity, which can lead to poor bonding margins. Alternatively, separate deposition processes can be used to form the different types of micro-bump structures. This can help to improve the co-planarity issue, but can increase cost.

[0032] Another approach to a "hybrid" micro-bump technology is to form an intermediate redistribution layer (RDL) landing on the semiconductor device structure, where the intermediate RDL landing has a desired pattern (e.g., different critical dimensions and / or pitches) to support various types of interconnects between the semiconductor device structures in a vertically stacked semiconductor device. Then, an array of micro-bump structures with uniform critical dimensions and / or pitches can be formed on the intermediate RDL landing. This approach can help improve coplanarity issues while also providing lower cost. However, it has been found that the use of an intermediate RDL landing can still result in poor joint yield due to solder bridging, necking, and other defects. For example, a tendency for solder collapse and under- RDL landing wetting has been found to occur during the bonding process, which can result in solder bridging between adjacent micro-bump structures. It has also been found that micro-bump structures formed on an intermediate RDL landing can have insufficient planarity.

[0033] Various embodiments disclosed herein seek to overcome these deficiencies and can include vertically stacked semiconductor devices and methods of forming vertically stacked semiconductor devices. Various embodiments disclosed herein can use a "hybrid" micro-bump bonding structure, including an intermediate redistribution layer (RDL) landing under a plurality of bump structures, which can provide improved bonding characteristics and device yield.

[0034] In some embodiments, a plurality of intermediate RDL landings can be formed on a first semiconductor device structure, and at least one bump structure can be formed on each of the intermediate RDL landings. The bump structures can have uniform dimensions and shapes. The intermediate RDL landings can have variable dimensions and / or shapes, and the number of bump structures that electrically contact different intermediate RDL landings can vary. Accordingly, such embodiments can facilitate the transmission of different types of signals (e.g., power transmission, data transmission, etc.) between the first semiconductor device structure and a second semiconductor device structure in a vertically stacked semiconductor device. Each bump structure can include a metal layer and a barrier layer between the metal layer and an underlying intermediate RDL landing. The composition of the metal layer can be different than the composition of the barrier layer, where the solder wettability of the metal layer can be greater than the solder wettability of the barrier layer. The relatively lower solder wettability of the barrier layer can limit solder wetting along the sidewalls of the bump structure. Such an architecture can help minimize solder collapse and bridging defects during a bonding process for bonding the bump structures to corresponding bonding structures on the second semiconductor device structure. In some embodiments, additional barrier layers can be utilized in the bonding structures of the second semiconductor device structure to inhibit solder bridging on the second semiconductor device structure. In some embodiments, the metal layers in the bump structures and / or the intermediate RDL landings can include copper, and the barrier layers can include nickel, iron, and / or tungsten.

[0035] In some embodiments, the bump structure and the intermediate redistribution line pad can be formed of different materials, where the material of the intermediate redistribution line pad can have a smaller solder wettability than the material of the bump structure. This can limit solder wetting along the surface of the intermediate redistribution line pad, thereby minimizing solder bridging defects between the bump structures on the first semiconductor device structure.

[0036] In some embodiments, the width of the second bonding structure on the second semiconductor device structure can be greater than the width of the metal layer of the bump structure on the first semiconductor device structure. This can provide a relatively larger surface area on the second bonding structure that solder material can contact during a bonding process, which can help minimize solder wetting along the sidewalls of the bump structure and possible solder collapse.

[0037] In yet another embodiment, various characteristics of the intermediate redistribution line pad and the bump structure can be controlled to improve the planarity characteristics of the upper surface of the bump structure.

[0038] Figure 1A is a top-down view of a first semiconductor device structure 101 according to various embodiments of the present disclosure. Figure 1B is a vertical cross-sectional view of the semiconductor device structure 101 taken along the line A-A’ in Figure 1A Figure 1A and 1B The first semiconductor device structure 101 can include a first semiconductor substrate 102, which can include elemental semiconductors such as silicon or germanium and / or compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, gallium nitride, or indium phosphide. Other semiconductor substrate materials are within the intended scope of the present disclosure. In some embodiments, the first semiconductor substrate 102 can be a silicon-on-insulator (SOI) substrate.

[0039] The first semiconductor substrate 102 can include a first major surface (i.e., a frontside surface 131) and a second major surface (i.e., a backside surface 132). Figure 1A and 1B is shown in an inverted architecture such that the frontside surface 131 of the first semiconductor substrate 102 faces downward and the backside surface 132 of the first semiconductor substrate 102 faces upward. In some embodiments, a plurality of devices (not shown) can be formed in the first semiconductor substrate 102, such as transistors, capacitors, resistors, and other devices. Figure 1B ​(Not shown) may be disposed on, on, and / or within the front surface 131 of the first semiconductor substrate 102. The device may include, for example, an active device, a passive device, or a combination thereof. In some embodiments, the device disposed on, on, and / or within the front surface 131 of the first semiconductor substrate 102 may include an integrated circuit device. The integrated circuit device may include, for example, a transistor (e.g., a field-effect transistor (FET)), a capacitor, a resistor, a diode, a photodiode, a fuse device, or other similar devices. In some embodiments, the integrated circuit device may include a gate electrode, a source / drain region, a spacer, an isolation trench, etc.

[0040] The first semiconductor device structure 101 may further include an interconnect structure on the front surface 131 of the first semiconductor substrate 102. The interconnect structure may include metallic features (e.g., metal lines, vias, bonding pads, etc.) formed in a dielectric material (e.g., one or more interlayer dielectric (ILD) layers and / or intermetallic dielectric (IMD) layers) that can provide connections to and / or between devices located on, on, and / or within the front surface 131 of the first semiconductor substrate 102.

[0041] In some embodiments, the first semiconductor device structure 101 may be a semiconductor die (i.e., a "chip"). For example, the first semiconductor device structure 101 may be a processor die, such as a system-on-a-chip (SoC), application-specific integrated circuit (ASIC) die, central processing unit die, and / or graphics processing unit chip. In some embodiments, the first semiconductor device structure 101 may be a "chiplet" die configured to perform specific, limited processing functions. In some embodiments, the first semiconductor device structure 101 may be a memory die, such as a high-bandwidth memory (HBM) die and / or dynamic random access memory (DRAM) die.

[0042] refer to Figure 1B The first semiconductor device structure 101 may include a plurality of substrate through-holes (TSVs) 112 extending through the first semiconductor substrate 102. The TSVs 112 may provide electrical connections between devices and / or interconnect structures on the front surface 131 and the back surface 132 of the first semiconductor substrate 102.

[0043] A plurality of first bonding structures can be formed on the backside surface 132 or the first semiconductor substrate 102. The first bonding structures can include a plurality of middle redistribution layer (RDL) pads 103 on the middle RDL pads 103 and a plurality of bump structures 106. Each of the middle RDL pads 103 can cover one or more TSVs 112 extending through the first semiconductor substrate 102 and can be electrically coupled to the one or more TSVs 112. The plurality of middle RDL pads 103 can have non-uniform sizes and / or shapes. As shown, for example, one or more first middle RDL pads 103a can have different sizes and / or shapes than one or more second middle RDL pads 103b. In some embodiments, a width dimension (i.e., a dimension within a plane containing the first horizontal direction hd1 and the second horizontal direction hd2) of the one or more first middle RDL pads 103a can be greater than a respective width dimension of the one or more second middle RDL pads 103b. In some embodiments, a horizontal cross-sectional area of the one or more first middle RDL pads 103a can be greater than a horizontal cross-sectional area of the one or more second middle RDL pads 103b. In some embodiments, an array of middle RDL pads 103 can be formed on the backside surface 132 of the first semiconductor substrate 102, where portions of the array of middle RDL pads 103 can include the first middle RDL pads 103a and portions of the array of middle RDL pads 103 can include the second middle RDL pads 103b. In some embodiments, the array can include additional middle RDL pads 103 (e.g., third middle RDL pads, fourth middle RDL pads, etc.) that can have different sizes and / or shapes than the first middle RDL pads 103a and the second middle RDL pads 103b. Figure 1A and 1B In some embodiments, a width dimension (i.e., a dimension within a plane containing the first horizontal direction hd1 and the second horizontal direction hd2) of the one or more first middle RDL pads 103a can be greater than a respective width dimension of the one or more second middle RDL pads 103b. In some embodiments, a horizontal cross-sectional area of the one or more first middle RDL pads 103a can be greater than a horizontal cross-sectional area of the one or more second middle RDL pads 103b. In some embodiments, an array of middle RDL pads 103 can be formed on the backside surface 132 of the first semiconductor substrate 102, where portions of the array of middle RDL pads 103 can include the first middle RDL pads 103a and portions of the array of middle RDL pads 103 can include the second middle RDL pads 103b. In some embodiments, the array can include additional middle RDL pads 103 (e.g., third middle RDL pads, fourth middle RDL pads, etc.) that can have different sizes and / or shapes than the first middle RDL pads 103a and the second middle RDL pads 103b. Figure 1A In some embodiments, a width dimension (i.e., a dimension within a plane containing the first horizontal direction hd1 and the second horizontal direction hd2) of the one or more first middle RDL pads 103a can be greater than a respective width dimension of the one or more second middle RDL pads 103b. In some embodiments, a horizontal cross-sectional area of the one or more first middle RDL pads 103a can be greater than a horizontal cross-sectional area of the one or more second middle RDL pads 103b. In some embodiments, an array of middle RDL pads 103 can be formed on the backside surface 132 of the first semiconductor substrate 102, where portions of the array of middle RDL pads 103 can include the first middle RDL pads 103a and portions of the array of middle RDL pads 103 can include the second middle RDL pads 103b. In some embodiments, the array can include additional middle RDL pads 103 (e.g., third middle RDL pads, fourth middle RDL pads, etc.) that can have different sizes and / or shapes than the first middle RDL pads 103a and the second middle RDL pads 103b.

[0044] In some embodiments, a width dimension (i.e., a dimension within a plane containing the first horizontal direction hd1 and the second horizontal direction hd2) of the one or more first middle RDL pads 103a can be greater than a respective width dimension of the one or more second middle RDL pads 103b. In some embodiments, a horizontal cross-sectional area of the one or more first middle RDL pads 103a can be greater than a horizontal cross-sectional area of the one or more second middle RDL pads 103b. In some embodiments, an array of middle RDL pads 103 can be formed on the backside surface 132 of the first semiconductor substrate 102, where portions of the array of middle RDL pads 103 can include the first middle RDL pads 103a and portions of the array of middle RDL pads 103 can include the second middle RDL pads 103b. In some embodiments, the array can include additional middle RDL pads 103 (e.g., third middle RDL pads, fourth middle RDL pads, etc.) that can have different sizes and / or shapes than the first middle RDL pads 103a and the second middle RDL pads 103b. Figure 1A and 1BThe width dimensions (i.e., the dimensions along hd1 and hd2) of each of the intermediate redistribution layer pads 103b (first intermediate redistribution layer pad 103a and second intermediate redistribution layer pad 103b) can be substantially the same, such that the error between the width dimensions of each type of intermediate redistribution layer pad 103 may be within ±5%.

[0045] The intermediate redistribution layer pad 103 can be formed of any suitable conductive material, such as copper (Cu), tungsten (W), aluminum (Al), their alloys, and combinations thereof. Other conductive materials are also within the scope of this disclosure.

[0046] See again Figure 1A and 1B A bump structure 106 may be formed on each intermediate redistribution layer pad 103. Each bump structure 106 may include a barrier layer 104 on the intermediate redistribution layer pad 103 and a metal layer 105 on the barrier layer 104. The metal layer 105 may have a different composition than the barrier layer 104, wherein the solder wettability of the metal layer 105 may be greater than that of the barrier layer 104 (e.g., determined by wetting balance analysis or similar recognized testing methods). In various embodiments, the relatively lower solder wettability of the barrier layer 104 compared to the metal layer 105 may limit solder wettability along the sidewalls of the bump structure 106, which may help minimize solder collapse and bridging defects during subsequent solder reflow processes. A solder material layer 107 may optionally be formed on the metal layer 105 of the bump structure 106.

[0047] In various embodiments, the metal layer 105 of the bump structure 106 can be formed of a suitable metallic material, such as copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof. In some embodiments, the intermediate redistribution layer pad 103 and the metal layer 105 of the bump structure 106 can be composed of the same material (e.g., copper). Alternatively, the intermediate redistribution layer pad 103 and the metal layer 105 can have different compositions. In some embodiments, the barrier layer 104 of the bump structure 106 can be formed of a suitable metallic material, such as nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof. The solder material layer 107 can be composed of a suitable solder material, such as tin-silver (SnAg), tin-copper (SnCu), tin-gold-copper (SnAuCu), tin-lead (SnPb), etc. Other suitable materials for the metal layer 105, barrier layer 104, and solder material layer 107 are also contemplated within the scope of this disclosure.

[0048] In various embodiments, each bump structure 106 formed on the first semiconductor device structure 101 can have the same critical dimension (CD). That is, the dimensions of each of the bump structures 106, including the vertical height dimension and / or the horizontal width dimension of each of the bump structures 106, can be within ±5% of each other. In various embodiments, the thickness of each barrier layer 104 can be between about 0.5 pm and about 6 pm, such as between about 1 pm and about 3 pm (e.g., about 2 pm). The thickness of each metal layer 105 can be between about 1 pm and about 8 pm, such as between about 2 pm and about 4 pm (e.g., about 3 pm). In some embodiments, the thickness of the metal layer 105 can be greater than the thickness of the barrier layer 104. In some embodiments, the thickness of the intermediate redistribution line landing pad 103 can be greater than the thickness of the metal layer 105. In some embodiments, the thickness of the solder material layer 107 can be between about 1 pm and about 10 pm, such as between about 5 pm and about 7 pm (e.g., about 6 pm). In some embodiments, the thickness of the solder material layer 107 can be greater than the thickness of the intermediate redistribution line landing pad 103, the barrier layer 104, and the metal layer 105.

[0049] In some embodiments, the width dimension of the metal layer 105 (i.e., within the horizontal plane containing hd1 and hd2) can be between about 10 pm and about 20 pm, such as between about 14 pm and about 18 pm (e.g., about 16 pm). In some embodiments, the width dimension of the barrier layer 104 can be greater than the width dimension of the metal layer 105, as shown. Figure 1B In some embodiments, the width dimension of the solder material layer 107 can be greater than the width dimension of the metal layer 105.

[0050] In various embodiments, the intermediate redistribution layer pad 103, barrier layer 104, metal layer 105, and solder material layer 107 can be formed using suitable deposition processes (e.g., physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or combinations thereof). In some embodiments, the intermediate redistribution layer pad 103, barrier layer 104, metal layer 105, and / or solder material layer 107 can be formed using an electrochemical deposition process. For example, a first mask layer can be formed on the back surface 132 of the first semiconductor substrate 102, and the first mask layer can be patterned using photolithography to remove portions of the first mask layer and form a patterned mask. Openings formed through the mask can correspond to the size, shape, and position of the subsequently formed intermediate redistribution layer pad 103. Then, an electrodeposition process (e.g., electroplating, electrodeposition, etc.) can be used to deposit a metal material (e.g., Cu) within the openings through the mask to form intermediate redistribution layer pads 103. After depositing the intermediate redistribution layer pads 103, the mask can be selectively removed. This process of forming and patterning the mask and depositing material within the openings through the mask can be repeated once or multiple times to form a barrier layer 104 on the intermediate redistribution layer pads 103, a metal layer 105 on the barrier layer 104, and / or a solder material layer 107 on the metal layer.

[0051] Figure 1C This is a top view of a second semiconductor device structure 201 according to various embodiments of the present disclosure. Figure 1D It is along Figure 1C The image shows a vertical cross-sectional view of the second semiconductor device structure 201, taken along line B-B'. (See reference.) Figure 1C and 1D The second semiconductor device structure 201 may include a second semiconductor substrate 202. The second semiconductor substrate 202 may include a suitable semiconductor material as described with reference to the first semiconductor substrate 102. In some embodiments, the second semiconductor substrate 202 may be made of the same material as the first semiconductor substrate 101. Alternatively, the second semiconductor substrate 202 and the first semiconductor substrate 102 may be made of different materials. The second semiconductor substrate 202 may include a second main surface (i.e., front surface 231) and a third main surface (i.e., back surface 232). In some embodiments, multiple devices (in...) Figure 1DDevices (not shown) can be located on, on, and / or in the front side surface 231 of the second semiconductor substrate 202. The devices can for example include active devices, passive devices, or a combination thereof. In some embodiments, the devices located on, on, and / or in the front side surface 231 of the second semiconductor substrate 202 can include integrated circuit devices. The integrated circuit devices can for example include transistors (e.g., field effect transistors (FETs)), capacitors, resistors, diodes, photodiodes, fuse devices, or other similar devices. In some embodiments, the integrated circuit devices can include gate electrodes, source / drain regions, spacers, isolation trenches, etc.

[0052] The second semiconductor device structure 201 can additionally include an interconnect structure on the front side surface 231 of the second semiconductor substrate 202. The interconnect structure can include metal features (e.g., metal lines and vias) embedded within dielectric material (e.g., one or more interlayer dielectric (ILD) layers and / or intermetal dielectric (IMD) layers), which can provide connections to and / or between various devices on, on, and / or in the front side surface 231 of the second semiconductor substrate 202.

[0053] In some embodiments, the second semiconductor device structure 201 can be a semiconductor die (i.e., a “chip”). For example, the second semiconductor device structure 201 can be a processor die, such as a system on a chip (SoC), an application specific integrated circuit (ASIC) die, a central processing unit die, and / or a graphics processing unit chip. In some embodiments, the second semiconductor device structure 201 can be a “chiplet” die configured to perform a specific, limited processing function. In some embodiments, the second semiconductor device structure 201 can be a memory die, such as a high bandwidth memory (HBM) die and / or a dynamic random access memory (DRAM) die. The first semiconductor device structure 101 and the second semiconductor device structure 201 can be the same type of die (e.g., a processor die, a memory die, etc.) or they can be different types of dies. In one non-limiting embodiment, the first semiconductor device structure 101 can be a chiplet and the second semiconductor device structure 201 can be a processor die, such as a SoC die.

[0054] Referring again to Figure 1C and 1D , an upper portion of the interconnect structure formed on the front side surface 231 of the second semiconductor substrate 202 is shown, including a plurality of dielectric material layers 206, metal features (e.g., vias 203, 204, metal features 208a, 208b) located within the dielectric material layers 206, and an array of second bonding structures 205 located on the dielectric material layers 206. It should be understood that the interconnect structure can include additional structures, including additional metal features, additional dielectric material layers, etc. located on, on, and / or in the front side surface 231 of the second semiconductor substrate 202. Figure 1C and1D additional dielectric layers and metal features between the upper portion of the interconnect structure shown in FIG. 2B and the front side surface 231 of the second semiconductor substrate 202. Referring again to Figure 1C and 1D metal features (e.g., vias 203, 204, metal features 208a, 208b) and second bonding structures 205 can be used to transmit different types of electronic signals to and / or from the second semiconductor device structure 201. For example, a first subset of metal features and second bonding structures 205 can be used to transmit electrical power to and / or from the second semiconductor device structure 201, and a second subset of metal features and second bonding structures 205 can be used to transmit data signals (e.g., die-to-die (D2D) communication signals) to and / or from the second semiconductor device structure 201. Different types of electronic signals can have different requirements in terms of current and / or voltage carrying capacity of the interconnect structures used to transmit the signals. For example, as shown in FIG. 2B, first vias 203 can be used to carry electrical power to and / or from the second semiconductor device structure 201, and second vias 204 can be used to carry data signals to and / or from the second semiconductor device structure 201. The first vias 203 can have a larger diameter than the second vias 204 to accommodate the different current and / or voltage characteristics of power signals as compared to data signals. Figure 1D

[0055] In various embodiments, it can be advantageous to form the second bonding structures 205 with a common critical dimension (CD) and, optionally, with a same spacing (pitch) between adjacent second bonding structures 205. For example, as noted above, forming bonding structures with different critical dimensions and / or pitches for different types of signals transmitted to and / or from the second semiconductor device structure 201 can result in poor coplanarity characteristics and / or increased cost. Thus, in various embodiments, an array of second bonding structures 205 with uniform dimensions and, optionally, uniform pitch can be formed. A first set of metal features 208a (e.g., metal lines and / or vias) can be used to connect the first vias 203 to a first set of one or more second bonding structures 205, and a second set of metal features 208b (e.g., metal lines and / or vias) can be used to connect the second vias 204 to a second set of one or more second bonding structures 205. In Figure 1C and 1D ​In the illustrated embodiment, each first via 203 can be electrically coupled to a plurality of second bonding structures 205 by a first set of metal features 208a, and each second via 204 can be electrically coupled to a single second bonding structure 205 by a second set of metal features 208b. Thus, a first type of signal (e.g., a power signal) can be transmitted to or from the second semiconductor device structure 201 on a plurality of second bonding structures 205 connected in parallel, while a second type of signal (e.g., a data signal) can be transmitted to or from the second semiconductor device structure 201 on a single bonding structure 205.

[0056] Referring again to Figure 1C and 1D The dielectric material layer 206 can be formed of a suitable dielectric material, such as silicon oxide, silicon nitride, silicon carbide, etc. Other dielectric materials are also within the contemplated scope of the present disclosure. The dielectric material layer 206 can be deposited using a suitable deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high-density plasma CVD (HDPCVD) process, a low-pressure CVD process, a metal-organic CVD (MOCVD) process, a plasma-enhanced CVD (PECVD) process, a sputtering process, laser ablation, etc. The metal features (vias 203, 204, metal features 208a, 208b) can be formed within the dielectric material layer 206, such as by a damascene or dual damascene process. The metal features (vias 203, 204, metal features 208a, 208b) can include a suitable conductive material, such as copper (Cu), tungsten (W), aluminum (Al), etc. The metal features (vias 203, 204, metal features 208a, 208b) can be formed using a suitable deposition process, such as physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), electrochemical deposition (e.g., electroplating), or combinations thereof.

[0057] The second bonding structures 205 can be formed on the dielectric material layer 206 and can be electrically coupled to the metal features (vias 203, 204, metal features 208a, 208b) located within the dielectric material layer 206. The second bonding structures 205 can be formed of a suitable metal material, such as copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof. In some embodiments, the second bonding structures 205 can be formed of the same material as the metal layer 105 of the bump structures 106 on the first semiconductor device structure 101. As described above, a suitable deposition process can be used to form the second bonding structures 205. In some embodiments, as described above, the second bonding structures 205 can be formed by an electrochemical deposition process (e.g., an electroplating process). Thus, each second bonding structure 205 can include at least one metal portion. In Figure 1C and 1D In the embodiment shown, the entirety of the second bonding structures 205 can include metal portions.

[0058] In various embodiments, the second bonding structures 205 can have the same critical dimension (CD). In some embodiments, the width dimension of the second bonding structures 205 can be equal to or substantially equal to the width dimension of the metal layer 105 of the bump structures 106 on the first semiconductor device structure 101. Alternatively, as will be described in further detail below, the width dimension of the second bonding structures 205 can be different from the width dimension of the metal layer 105 of the bump structures 106. The second bonding structures 205 on the second semiconductor device structure 201 can form an array of second bonding structures 205 having a pattern and layout corresponding to the pattern and layout of the bump structures 106 on the first semiconductor device structure 201.

[0059] Figure 1E is a vertical cross-sectional view showing the second semiconductor device structure 201 aligned on the first semiconductor device structure 101 according to various embodiments of the present disclosure. Referring to Figure 1E , the second semiconductor device structure 201 can be inverted (i.e., flipped) with respect to the orientation shown in Figure 1C and 1D such that the front side surface 231 of the second semiconductor substrate 202 faces downward and the back side surface 232 of the second semiconductor substrate 102 faces upward. The second semiconductor device structure 201 can be aligned on the first semiconductor device structure 101 such that each second bonding structure 205 of the second semiconductor device structure 201 can be aligned with a corresponding bump structure 106 of the first semiconductor device structure 101. Although Figure 1EThe second semiconductor device structure 201 is shown aligned on the first semiconductor device structure 101, but it should be understood that in other embodiments, the first semiconductor device structure 101 can be aligned on the second semiconductor device structure 201.

[0060] Referring again to Figure 1E The metal layer 105 of the bump structure 106 can have a thickness T1, the second bonding structure 205 can have a thickness T2, and the solder material layer 107 can have a thickness T3. In various embodiments, the thickness T2 of the second bonding structure 205 can be between about 3 pm and about 15 pm, such as between about 5 pm and about 10 pm (e.g., about 8 pm). In some embodiments, the thickness of the metal layer 105 can be greater than the thickness of the barrier layer 104. In some embodiments, the thickness T2 of the second bonding structure 205 can be greater than the thickness of the intermediate redistribution line layer pad 103, the barrier layer 104, the metal layer 105, the solder material layer 107. In some embodiments, 2x(T1+T2) > T3. That is, the combined thickness of the metal layer 105 and the second bonding structure 205 can be equal to or greater than half of the thickness of the solder material layer 107. This can help facilitate sufficient intermetallic compound (IMC) formation during a subsequent solder reflow process used to bond the first semiconductor device structure 101 to the second semiconductor device structure 201, and can also help reduce or eliminate solder bridging defects (e.g., when there is too much solder material) and / or solder necking defects (e.g., when there is not enough solder material).

[0061] Figure 1F is a vertical cross-sectional view of a vertically stacked semiconductor device 150 according to various embodiments of the present disclosure. Referring to Figure 1FThe second semiconductor device structure 201 can be brought into contact with the first semiconductor device structure 101 such that the layer of solder material 107 can be located between and bring into contact the bump structures 106 of the first semiconductor device structure 101 and the respective second bonding structures 205 of the second semiconductor device structure 201. A reflow process can then be performed, which includes subjecting the assembly including the first semiconductor device structure 101 and the second semiconductor device structure 201 to a high temperature above the melting point of the layer of solder material 107. This can cause at least partial melting and formation of a liquid phase in the layer of solder material 107. The molten solder material can create a metallurgical bond between the metal layer 105 of the bump structures 106 on the first semiconductor device structure 101 and the second bonding structures 205 on the second semiconductor device structure 201. The assembly can then be cooled, causing the solder material to solidify and form solder joints 109 that physically and electrically couple each of the metal layer 105 or bump structures 106 on the first semiconductor device structure 101 to the respective second bonding structures 205 on the second semiconductor device structure 201.

[0062] In some embodiments, the reflow process can induce formation of an intermetallic compound (IMC) layer. The IMC layer can form at the interface between the molten solder material and the metal layer 105 of the bump structures 106, as well as between the molten solder material and the second bonding structures 205. The IMC layer can selectively form at the interface between the molten solder material and the barrier layer 104, and in some cases, between the molten solder material and the intermediate redistribution line pad 103. In some embodiments, the IMC layer can include tin as well as one or more of copper, nickel, iron, and tungsten.

[0063] As described above, the relatively low solder wettability of the barrier layer 104 of the bump structures 106 can inhibit wettability of the solder along the sidewalls of the bump structures 106. As a result, solder wetting of the underlying intermediate redistribution line pad 103 can be reduced or eliminated, which can reduce the incidence of solder bridging between multiple bump structures 106.

[0064] Referring again to Figure 1FThe vertical stacked semiconductor device 150 includes the first semiconductor device structure 101 bonded with the second semiconductor device structure 201 by the plurality of solder joints 109. A first type of signal (e.g., a power signal) can be transmitted between the first semiconductor device structure 101 and the second semiconductor device structure 201 by a first signal path that includes the first via 203, a first set of the plurality of second bonding structures 205, the plurality of solder joints 109, the plurality of bump structures 106, and the first intermediate redistribution layer land pad 103a. The first signal path can also include at least one TSV 112 that passes through the first semiconductor substrate 102 of the first semiconductor device structure 101 beneath the first intermediate redistribution layer land pad 103a. A second type of signal (e.g., a data signal) can be transmitted between the first semiconductor device structure 101 and the second semiconductor device structure 201 by a second signal path that includes the second via 204, a second set of the metal features 208b, the single second bonding structure 205, the single solder joint 109, the single bump structure 106, and the second intermediate redistribution layer land pad 103b. The second signal path can also include at least one TSV 112 that passes through the first semiconductor substrate 102 of the first semiconductor device structure 101 beneath the second intermediate redistribution layer land pad 103b.

[0065] Figure 1F The illustrated vertical stacked semiconductor device 150 includes the first semiconductor device structure 101 bonded with the second semiconductor device structure 201 such that the front side surface 231 of the second semiconductor substrate 202 and the back side surface 131 of the first semiconductor substrate 102 face each other. Thus, the vertical stacked semiconductor device 150 can have a front-to-back architecture. However, it should be understood that other embodiments of the vertical stacked semiconductor device 150 can have different architectures, such as a front-to-front architecture or a back-to-back architecture.

[0066] Furthermore, while Figure 1E and 1F bonding process, it should be understood that the orientation of the vertical stacked semiconductor device 150 can be reversed such that the first semiconductor device structure 101 can be the "top" structure in the vertical stacked semiconductor device 150 and the second semiconductor device structure 201 can be the "bottom" structure.

[0067] Figure 2Ais a vertical cross-sectional view showing the second semiconductor device structure 201 aligned on the first semiconductor device structure 101 according to another embodiment of the present disclosure. Figure 2A The first semiconductor device structure 101 and the second semiconductor device structure 201 shown can be similar to the first semiconductor device structure 101 and the second semiconductor device structure 201 described above with reference to Figures 1A-1F . Thus, repeated discussion of similar devices is omitted for brevity. Figure 2A The embodiment shown in Figures 1A-1F differs from the embodiment shown in Figure 2A in that each of the second bonding structures 205 of the second semiconductor device structure 201 includes a multi-layer structure, which can include a first metal portion 211, a barrier layer 212, and a second metal portion 213. Each first metal portion 211 can be formed on the dielectric material layer 206 and can be electrically coupled to a metal feature (via 203, 204, metal feature 208a, 208b) located within the dielectric material layer 206. The barrier layer 212 can be formed on the first metal portion 211. The second metal portion 213 can be formed on the barrier layer 212. A solder material layer 214 can be optionally formed on the second metal portion 213. The second semiconductor device structure 201 can then be inverted (i.e., flipped) and aligned on the first semiconductor device structure 101, as shown in Figure 2A .

[0068] In various embodiments, the barrier layer 212 can have a different composition than the first metal portion 211 and the second metal portion 213. The solder wettability of the barrier layer 212 can be lower than the solder wettability of the first metal portion 211 and the second metal portion 213. In various embodiments, the first metal portion 211 and the second metal portion 213 can be formed of suitable metal materials, such as copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof. In some embodiments, the first metal portion 211, the second metal portion 213, and the metal layer 105 of the bump structure 106 can all be composed of the same material. Alternatively, the first metal portion 211, the second metal portion 213, and / or the metal layer 105 can have different compositions. In some embodiments, the barrier layer 212 can be formed of suitable metal materials, such as nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof. The solder material layer 214 can be composed of suitable solder materials, such as tin-silver (SnAg), tin-copper (SnCu), tin-gold-copper (SnAuCu), tin-lead (SnPb), and the like. In some embodiments, the solder material layer 214 can have the same composition as the solder material layer 107 located on the metal layer 105 of the bump structure 106. Alternatively, the solder material layer 214 and the solder material layer 107 can have different compositions.

[0069] In various embodiments, the thickness T6 of the first metal portion 211 can be between about 1 μm and about 8 μm, for example, between about 2 μm and about 4 μm (e.g., about 3 μm). The thickness T7 of the barrier layer 212 can be between about 0.5 μm and about 6 μm, for example, between about 1 μm and about 3 μm (e.g., about 2 μm). The thickness T8 of the second metal portion 213 can be between about 1 μm and about 8 μm, for example, between about 2 μm and about 4 μm (e.g., about 3 μm). In some embodiments, the thickness T9 of the solder material layer 214 can be between about 0.5 μm and about 7 μm, for example, between about 2 μm and about 4 μm (e.g., about 3 μm).

[0070] Figure 2A The illustrated embodiments and Figures 1A-1F The difference in the illustrated embodiment may also be that the thickness T5 of the solder material layer 107 on the metal layer 105 of the bump structure 106 on the first semiconductor device structure 101 may be less than Figures 1A-1E The thickness of the solder material layer 107 in the illustrated embodiment. In some embodiments, the thickness T4 of the barrier layer 104 on the metal layer 105 of the bump structure 106 may be at least the same as the thickness T7 of the barrier layer 212 on the second metal portion 213 of the second bonding structure 205 (i.e., T4 ≥ T7). In some embodiments, twice the combined thickness of the first metal portion 211 and the second metal portion 213 may be at least as large as the combined thickness of the solder material layers 107 and 214 (i.e., 2 × (T6 + T8) ≥ (T5 + T9)).

[0071] In some embodiments, such as Figure 2A As shown, the width of the barrier layer 212 may be greater than the width of the first and second metal portions 211 and 213. In some embodiments, the width of the solder material layer 214 may be greater than the width of the first and second metal portions 211 and 213.

[0072] Figure 2B This is a vertical cross-sectional view of a vertically stacked semiconductor device 150 according to another embodiment of this disclosure. Reference Figure 2B The second semiconductor device structure 201 can contact the first semiconductor device structure 101, such that the solder material layer 107 on the first semiconductor device structure 101 contacts the solder material layer 214 on the second semiconductor device structure 201. This can be referred to as... Figure 1FThe reflow process is performed to form a solder joint 109 extending between each of the bump structures 106 on the first semiconductor device structure 101 and a corresponding second bonding structure 205 on the second semiconductor device structure 201. The relatively low degree of solder wetability of the barrier layers 104, 212 in the bump structures 106 of the first semiconductor device structure 101 and the second bonding structures 205 of the second semiconductor device structure 201 can help limit solder wetability on sidewalls of the bump structures 106 and the second bonding structures 205. This can help suppress solder bridging defects from occurring on the first semiconductor device structure 101 and the second semiconductor device structure 201, which can provide improved yield for the vertically stacked semiconductor device 150.

[0073] Figure 3A is a vertical cross-sectional view showing the second semiconductor device structure 201 aligned on the first semiconductor device structure 101 according to another embodiment of the disclosure. Figure 3A The first semiconductor device structure 101 and the second semiconductor device structure 201 shown can be similar to the first semiconductor device structure 101 and the second semiconductor device structure 201 described above with reference to Figures 1A-1F . Thus, repeated discussion of similar devices is omitted for brevity. Figure 3A The embodiment shown differs from the embodiment shown in Figures 1A-1F in that the barrier layer 104 is omitted from the bump structures 106 of the first semiconductor device structure 101. Thus, each bump structure 106 includes the metal layer 105 described above on the intermediate redistribution line landing 103. The solder material layer 107 described above can optionally be located on the metal layer 105. In addition, the first intermediate redistribution line landing 103a and the second intermediate redistribution line landing 103b can be formed of a material having a lower degree of wetability than the material of the metal layer 105. In some embodiments, the first intermediate redistribution line landing 103a and the second intermediate redistribution line landing 103b can be formed of a suitable metal material, such as nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof. The metal layer 105 can be formed of a suitable metal material, such as copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof.

[0074] In the embodiment shown in Figure 3A , the relatively low degree of solder wetability of the intermediate redistribution line landing 103 can help suppress solder bridging defects from occurring between adjacent bump structures 106 during a subsequent bonding process. Figure 3A The embodiment shown differs from the embodiment shown in Figures 1A-1F in that the intermediate redistribution line landing 103 of the embodiment shown in Figure 3A may have a thickness that is greater than the thickness of the intermediate redistribution line landing 103 of the embodiment shown in Figures 1A-1FThe thickness of the middle redistribution line via pads 103 of the illustrated embodiment. In one non-limiting embodiment, the thickness of each of the middle redistribution line via pads 103 of the embodiment of FIG. 3 can be between about 2 pm and about 15 pm, such as between about 5 pm and about 9 pm (e.g., about 7 pm). The relatively large thickness of the middle redistribution line via pads 103 can compensate for the lack of a barrier layer in the bump structures 106, such that a desired vertical gap between the backside surface 132 of the first semiconductor substrate 102 and the subsequently formed solder joints can be maintained.

[0075] Figure 3B is a vertical cross-sectional view of a vertical stack semiconductor device 150 according to another embodiment of the disclosure. Reference is made to Figure 3B The second semiconductor device structure 201 can be contacted with the first semiconductor device structure 101 such that the layer of solder material 107 on the first semiconductor device structure 101 contacts the second bonding structures 205 on the second semiconductor device structure 201. The reflow process can be performed as described above with reference to Figure 1F to form the solder joints 109 extending between each of the bump structures 106 on the first semiconductor device structure 101 and the respective second bonding structures 205 on the second semiconductor device structure 201. Although the embodiments shown in Figure 3A and 3B illustrate the second bonding structures 205 as including a single metal layer, it is understood that the second bonding structures 205 on the second semiconductor device structure 201 can include a multi-layer structure as described with reference to Figure 2A and 2B .

[0076] Figure 4A is a vertical cross-sectional view illustrating the second semiconductor device structure 201 aligned on the first semiconductor device structure 101 according to another embodiment of the disclosure. Figure 4A The first and second semiconductor device structures 101, 201 illustrated can be similar to the first and second semiconductor device structures 101, 201 described above with reference to Figures 1A-1F . Accordingly, repeated discussion of similar devices is omitted for the sake of brevity. Figure 4A The illustrated embodiment differs from the embodiment illustrated in Figures 1A-1F in that the width dimension of each of the second bonding structures 205 of the second semiconductor device structure 201 is greater than the width dimension of the metal layer 105 of the bump structures 106 of the first semiconductor device structure 101. In various embodiments, the width dimension of the second bonding structures 205 can be at least 10% greater, such as at least 12% greater, than the width dimension of the metal layer 105. In some embodiments, the width dimension of the second bonding structures 106 can be at least 2 pm greater than the width dimension of the metal layer 105.

[0077] In various embodiments, the relatively larger width dimension of the second bonding structures 106 can provide a larger surface area contact for the solder material during subsequent bonding processes. This can facilitate the formation of a larger amount of IMC on the second bonding structures 205 of the second semiconductor device structure 201, which can help to minimize solder collapse along the sidewalls of the bump structures 106 and the intermediate redistribution line pads 103, thereby avoiding solder bridge defects.

[0078] Figure 4A The illustrated embodiment differs from the embodiment illustrated in Figures 1A-1F The illustrated embodiment also differs from the embodiment illustrated in Figure 4A The illustrated embodiment differs from the embodiment illustrated in Figures 1A-1F The illustrated embodiment can also differ from the embodiment illustrated in Figure 4A The thickness Tl of the metal layer 105 of the embodiment can be greater than Figures 1A-1F The thickness of the metal layer 105 of the embodiment. In one non-limiting embodiment, Figure 5A The thickness of each metal layer 105 of the embodiment can be between about 1 pm and about 10 pm, such as between about 4 pm and about 6 pm (e.g., about 5 pm). The relatively larger thickness of the metal layer 105 can compensate for the absence of a barrier layer in the bump structure 106, such that a desired vertical gap between the backside surface 132 of the first semiconductor substrate 102 and the subsequently formed solder joints can be maintained.

[0079] Figure 4B is a vertical cross-sectional view of a vertical stacked semiconductor device 150 according to another embodiment of the present disclosure. Reference is made to Figure 4B The second semiconductor device structure 201 can be brought into contact with the first semiconductor device structure 101 such that the solder material layer 107 on the first semiconductor device structure 101 contacts the second bonding structures 205 on the second semiconductor device structure 201. The reflow process can be performed as described above with reference to Figure 1F The reflow process can be performed to form solder joints 109 extending between each of the bump structures 106 on the first semiconductor device structure 101 and the corresponding second bonding structures 205 on the second semiconductor device structure 201. Although the embodiment illustrated in Figure 4A The embodiment illustrated in Figure 4B It should be appreciated that the second bonding structures 205 on the second semiconductor device structure 201 can include a single metal layer as illustrated in the embodiment illustrated in Figure 2A The embodiment illustrated in 2BThe multi-layer structure, wherein the multi-layer second bonding structure 205 can include a greater width dimension than the metal layer 105 of the bump structure 106 of the first semiconductor device structure 101. Alternatively, or in addition, the bump structure 106 of the first semiconductor device structure 101 can include a metal layer 105 as described above with reference to Figures 1A-1F The barrier layer 104 described above, and / or as described above with reference to Figure 3A and 3B The intermediate redistribution line land 103 can be composed of a material having a relatively lower solder wetting property compared to the material of the metal layer 105.

[0080] Other embodiments include bonding structures having bump structures on intermediate redistribution line lands and having improved coplanarity properties, and methods of forming the same. Figure 5A is a top-down view of a first semiconductor device structure 101 according to various embodiments of the present disclosure. Figure 5B is a vertical cross-sectional view of the first semiconductor device structure 101 taken along line C-C’ in Figure 5A Figure 5A and 5B The first semiconductor device structure 101 shown in Figures 1A-1F is similar to the first semiconductor device structure 101 described above with reference to Figure 5A and 5B The first semiconductor device structure 101 shown in Figures 1A-1F is similar to the embodiments shown in However, it should be understood that in other embodiments, the bump structure 106 can also include the barrier layer 104.

[0081] Figure 5B is a vertical cross-sectional view depicting a portion of a first semiconductor device structure 101 including a second intermediate redistribution line land 103b and a bump structure 106 including a metal layer 105 on the second intermediate redistribution line land 103b. A solder material layer 107 is on an upper surface 159 of the metal layer 105. As described above, an important consideration in improving the bonding properties and yield of a vertically stacked semiconductor device is the degree of coplanarity of the bump structure 106, particularly the coplanarity properties of the upper surface 159 of the metal layer 105 in contact with the solder material layer 107. As shown in Figure 5BAs shown, the maximum variation in the vertical height adjacent to the periphery of the upper surface 159 of the metal layer 105 can be referred to as the "flatness difference" 129 of the bump structure 106. The flatness difference 129 can be used to quantify the degree of "tilt" of the upper surface 159 of the metal layer 105 relative to the horizontal reference plane. Excessive tilt (i.e., high flatness difference 129) can lead to poor bonding formation, solder collapse, and other defects that may negatively impact device yield. In some embodiments, the flatness difference 129 of the bump structure 106 can be ≤0.8 μm to provide effective bonding.

[0082] However, as Figure 5A and 5B As shown, maintaining a flatness difference of 0.8 μm or less in the bump structure 106 can be difficult. This may be partly attributed to variations in the thickness of the intermediate redistribution layer pads 103 on which the bump structure 106 is formed. Figure 5B As shown in the cross-sectional view, the intermediate redistribution layer pad 103 (in this example, the second intermediate redistribution layer pad 103b) includes a lower surface 161 and a flat upper surface 162. The width dimension 121 of the lower surface 161 of the intermediate redistribution layer pad 103 is greater than the width dimension 123 of the flat upper surface 162 of the intermediate redistribution layer pad 103. Therefore, as Figure 5B As shown, a portion of the sidewall extending between the lower surface 161 and the flat upper surface 162 may taper inward between the lower surface 161 and the flat upper surface 162. The shape of the intermediate redistribution layer pad 103, including the relatively wide lower surface 161 and the narrower flat upper surface 162, may be at least in part due to the deposition process (e.g., electroplating) and process parameters used to form the intermediate redistribution layer pad 103.

[0083] See again Figure 5BThe width dimension 125 of the metal layer 105 of the bump structure 106 may be smaller than the width dimension 121 of the lower surface 161 of the intermediate redistribution layer pad 103. A target enclosure distance 127 may be offset between the peripheral edge of the metal layer 105 and the peripheral edge of the intermediate redistribution layer pad 103. In some embodiments, the target enclosure distance 127 may be ≥2.5 μm. To provide a high degree of coplanarity and minimize the flatness difference 129 of the bump structure 106, the metal layer 105 may be located on the flat upper surface 162 of the intermediate redistribution layer pad 103 rather than on the inclined portion of the intermediate redistribution layer pad 103. Therefore, providing a width dimension 121 of the flat upper surface 162 that is relatively large relative to the overall width dimension 123 of the intermediate redistribution layer pad 103 can help increase coplanarity and minimize the flatness difference 129. In some embodiments, the width dimension 121 of the flat upper surface 162 may be at least as large as the width dimension 125 of the metal layer 105. In some embodiments, the width dimension 121 of the flat upper surface 162 may be at least 2% larger than the width dimension 125 of the metal layer 105, including at least 5% larger, for example, at least 6% larger. In some embodiments, the width dimension 121 of the flat upper surface 162 may be partially controlled by controlling the deposition rate of the intermediate redistribution layer pad 103. In a non-limiting example, the intermediate redistribution layer pad 103 may be deposited at a rate of at least about 3 A / dm. 2 (For example, about 3 to about 5 A / dm) 2 Electroplating is performed at a deposition rate of at least about 4 A / dm² to form the deposit. 2 This provides a relatively wide, flat upper surface 162 for the intermediate redistribution layer pad 103.

[0084] Figure 6 This is a flowchart illustrating a method 300 for manufacturing a vertically stacked semiconductor device 150 according to an embodiment of this disclosure. (See also:) Figure 1A , 1B In step 301 of method 300, the intermediate redistribution layer (RDL) pad 103 may be formed on the back surface 132 of the first semiconductor substrate 102 of the first semiconductor device structure 101. (See reference 6.) Figure 1A , 1B In step 303 of method 300, a plurality of bump structures 106 may be formed on the intermediate redistribution layer pad 103, wherein each bump structure 106 may include a barrier layer 104 on the intermediate redistribution layer pad 103 and a metal layer 105 on the barrier layer 104, and the barrier layer 104 is formed of a material having a lower solder wettability than the material of the metal layer 105. (See reference...) Figure 1E , 2Aand 6, in step 305 of method 300, first semiconductor device structure 101 can be aligned with second semiconductor device structure 201 such that each bump structure 106 is aligned with a respective second bonding structure 205 of second semiconductor device structure 201, and solder material 107, 214 is located between and in contact with metal layer 105 of bump structure 106 and respective second bonding structure 205. Reference is made to FIG. 3B. Figure 1F 、 2B and 6, in step 307 of method 300, a reflow process can be performed to form a plurality of solder joints 109 extending between bump structure 106 and respective second bonding structure 205 of second semiconductor device structure 201.

[0085] Figure 7 is a flowchart illustrating a method 400 of fabricating a vertically stacked semiconductor device 150 according to another embodiment of the present disclosure. Reference is made to FIG. 4A. Figure 3A and 7 In step 401 of method 400, an intermediate redistribution layer (RDL) pad 103 can be formed on backside surface 132 of first semiconductor substrate 102 of first semiconductor device structure 101. Reference is made to FIG. 4B. Figure 3A and 7 In step 403 of method 400, a plurality of bump structures 106 can be formed on intermediate redistribution layer pad 103, where each bump structure 106 includes a metal layer 105 on intermediate redistribution layer pad 103, and intermediate redistribution layer pad 103 is composed of a material having a smaller solder wettability than a material of metal layer 105. Reference is made to FIG. 4C. Figure 3A and 7 In step 405 of method 400, first semiconductor device structure 101 can be aligned with second semiconductor device structure 201 such that each bump structure 106 is aligned with a respective second bonding structure 205 of second semiconductor device structure 201, and solder material 107 is located between and in contact with metal layer 105 of bump structure 106 and respective second bonding structure 205. Reference is made to FIG. 4D. Figure 3B and 7 In step 407 of method 500, a reflow process can be performed to form a plurality of solder joints 109 extending between bump structure 106 and respective second bonding structure 205 of second semiconductor device structure 201.

[0086] Figure 8 is a flowchart illustrating a method 500 of fabricating a vertically stacked semiconductor device 150 according to another embodiment of the present disclosure. Reference is made to FIG. 5A. Figure 4A and 8In step 501 of the method 500, an intermediate redistribution layer (RDL) pad 103 can be formed on the backside surface 132 of the first semiconductor substrate 102 of the first semiconductor device structure 101. Referring to FIG. 1, the intermediate redistribution layer pad 103 can be formed on the backside surface 132 of the first semiconductor substrate 102 of the first semiconductor device structure 101. Figure 4A and 8 In step 503 of the method 500, a plurality of bump structures 106 can be formed on the intermediate redistribution layer pad 103, wherein each bump structure 106 includes a metal layer 105 on the intermediate redistribution layer pad 103. Referring to FIG. 1, the plurality of bump structures 106 can be formed on the intermediate redistribution layer pad 103 of the first semiconductor device structure 101. Figure 4A and 8 In step 505 of the method 400, the first semiconductor device structure 101 can be aligned with the second semiconductor device structure 201 such that each bump structure 106 is aligned with a respective second bonding structure 205 of the second semiconductor device structure 201, and the solder material 107 is located between and in contact with the metal layer 105 of the bump structure 106 and the respective second bonding structure 205, wherein a width dimension of each of the second bonding structure 205 is greater than a width dimension of the metal layer 105 of the bump structure 106. Referring to FIG. 1, the first semiconductor device structure 101 can be aligned with the second semiconductor device structure 201 such that each bump structure 106 is aligned with a respective second bonding structure 205 of the second semiconductor device structure 201, and the solder material 107 is located between and in contact with the metal layer 105 of the bump structure 106 and the respective second bonding structure 205, wherein a width dimension of each of the second bonding structure 205 is greater than a width dimension of the metal layer 105 of the bump structure 106. Figure 4B and 8 In step 507 of the method 500, a reflow process can be performed to form a plurality of solder joints 109 extending between the bump structures 106 and the respective second bonding structures 205 of the second semiconductor device structure 201. Referring to FIG. 1, a reflow process can be performed to form a plurality of solder joints 109 extending between the bump structures 106 and the respective second bonding structures 205 of the second semiconductor device structure 201.

[0087] Figure 9 is a flowchart illustrating a method 600 of fabricating a bonding structure according to another embodiment of the present disclosure. Referring to FIG. 6, the method 600 can include the following steps. Figure 5A 、 5B and 9, in step 601 of the method 600, an intermediate redistribution layer (RDL) pad 103 can be formed on a backside surface of a first semiconductor substrate 102 of a first semiconductor device structure 101, wherein the intermediate redistribution layer pad 103 has a lower surface 161 and a planar upper surface 162, and a width dimension 121 of the lower surface 161 is greater than a width dimension 123 of the planar upper surface 162. Referring to FIG. 6, the intermediate redistribution layer pad 103 can be formed on the backside surface of the first semiconductor substrate 102 of the first semiconductor device structure 101. Figure 5A 、 5B and 9, in step 603 of the method 600, a bump structure 106 can be formed on the planar upper surface 162 of the intermediate redistribution layer pad 103, wherein the bump structure 106 includes a metal layer 105 on the intermediate redistribution layer pad 103, a width dimension 123 of the planar upper surface 162 is equal to or greater than a width dimension 125 of the metal layer 105, a peripheral edge of the metal layer 105 is offset from a peripheral edge of the intermediate redistribution layer pad 103 by a target encroachment distance 127 of at least 2.5 pm, and a maximum variation in a vertical height alongside a peripheral edge of an upper surface 159 of the metal layer 105 is 0.8 pm or less. Referring to FIG. 6, the bump structure 106 can be formed on the planar upper surface 162 of the intermediate redistribution layer pad 103.

[0088] Referring to all the drawings and in accordance with various embodiments of the present disclosure, a semiconductor device 150 includes a first device structure 101 including a first semiconductor substrate 102, an intermediate redistribution layer (RDL) land 103, and a plurality of bump structures 106 electrically connected to the intermediate RDL land 103, wherein the intermediate RDL land 103 is located between the first semiconductor substrate 102 and the plurality of bump structures 106, each of the bump structures 106 includes a metal layer 105 and a barrier layer 104 located between the metal layer 105 and the intermediate RDL land 103, and a solder wetting property of the metal layer 105 is greater than a solder wetting property of the barrier layer 105, a second device structure 201 includes a second semiconductor substrate 202 and a second bonding structure 205, and a plurality of solder joints 109 are located between the metal layer 105 of the bump structure 106 of the first device structure 101 and the second bonding structure 205 of the second device structure 201.

[0089] In one embodiment, the first device structure 101 includes a plurality of through-substrate vias (TSVs) 112 extending through the first semiconductor substrate 102, and the intermediate RDL land 103 is located on a backside surface 132 of the first semiconductor substrate 102 and electrically contacts at least one of the TSVs 112.

[0090] In another embodiment, the intermediate RDL land 103 includes a first intermediate RDL land 103a, and the first device structure 102 further includes a second intermediate RDL land 103b located on the backside surface 132 of the first semiconductor substrate 102 and electrically contacts at least one of the TSVs 112, and at least one of the bump structures 106 electrically contacts the second intermediate RDL land 103b and is coupled to a corresponding second bonding structure 205 of the second device structure 201 through the solder joint 109, wherein at least one of a size and a shape of the first intermediate RDL land 103a is different from a corresponding size or shape of the second intermediate RDL land 103b, a total number of the bump structures 106 electrically contacting the first intermediate RDL land 103a is different from a total number of the bump structures 106 electrically contacting the second intermediate RDL land 103b, and the plurality of bump structures 106 electrically contacting the first intermediate RDL land 103a and the at least one of the bump structures 106 electrically contacting the second intermediate RDL land 103b have a same critical dimension.

[0091] In another embodiment, wherein the plurality of bump structures 106 electrically contacting the first intermediate RDL land 103a transmit a first type of signal between the first device structure 101 and the second device structure 201, and the at least one of the bump structures 106 electrically contacting the second intermediate RDL land 103b transmits a second type of signal between the first device structure 101 and the second device structure 201.

[0092] In another embodiment, the first type of signal includes a power signal, and the second type of signal includes a data signal.

[0093] In another embodiment, the metal layer 105 of each of the plurality of bump structures 106 includes at least one of copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof, and the barrier layer 104 of the plurality of bump structures 106 includes at least one of nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof.

[0094] In another embodiment, the metal layer 105 of each of the plurality of bump structures 106 and the metal layer of the intermediate redistribution line pad 103 are formed of the same material.

[0095] In another embodiment, a width dimension of the barrier layer 104 of each of the plurality of bump structures 106 is greater than a width dimension of the metal layer 105 of each of the plurality of bump structures 106.

[0096] In another embodiment, each of the plurality of second bonding structures 205 includes a barrier layer 212 between a pair of metal portions 211, 213, and in the plurality of second bonding structures 205, a solder wettability of the pair of metal portions 211, 213 is greater than a solder wettability of the barrier layer 212.

[0097] In another embodiment, a thickness of the barrier layer 104 of each of the plurality of bump structures 106 is equal to or greater than a thickness of the barrier layer 212 of the second bonding structure 205.

[0098] In another embodiment, each of the plurality of second bonding structures 205 includes a metal portion, and a width dimension of the metal portion of the plurality of second bonding structures 205 is greater than a width dimension of the metal layer 105 of each of the plurality of bump structures 106.

[0099] In another embodiment, the metal layer 105 of each of the plurality of bump structures 106 includes an upper surface 159 that contacts the solder joint 109, and a maximum variation in a vertical height around a perimeter of the upper surface 159 of each of the plurality of bump structures 106 is 0.8 pm or less.

[0100] Another embodiment illustrates a semiconductor device 150, where the first device structure 101 includes a first semiconductor substrate 102, an intermediate redistribution layer (RDL) landing pad 103, and a plurality of bump structures 106 electrically connected with the intermediate redistribution layer landing pad 103, where the intermediate redistribution layer landing pad 103 is between the first semiconductor substrate 102 and the plurality of bump structures 106, each of the plurality of bump structures 106 includes a metal layer 105, and a solder wettability of the metal layer 105 of each of the plurality of bump structures 106 is greater than a solder wettability of the intermediate redistribution layer landing pad 103, the second device structure 201 includes a second semiconductor substrate 202 and a second bonding structure 205, and a plurality of solder joints 109 is between the metal layer 105 of the plurality of bump structures 106 of the first device structure 101 and the second bonding structure 205 of the second device structure 201.

[0101] In one embodiment, the metal layer of each of the plurality of bump structures 106 includes at least one of copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof, and the intermediate redistribution layer landing pad 103 includes at least one of nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof.

[0102] In another embodiment, each of the plurality of bump structures 106 includes a barrier layer 104 between the metal layer 105 and the intermediate redistribution layer landing pad 103, and a composition of the barrier layer 104 is different from a composition of the metal layer 105.

[0103] Another embodiment illustrates a method of fabricating a vertically stacked semiconductor device 150, including forming an intermediate redistribution layer (RDL) landing pad 103 on a backside surface 132 of a first semiconductor substrate 102 of a first semiconductor device structure 101; forming a plurality of bump structures 106 on the intermediate redistribution layer landing pad 103, where each of the plurality of bump structures 106 includes a barrier layer 104 on the intermediate redistribution layer landing pad 103 and a metal layer 105 on the barrier layer 104, and a solder wettability of a material of the barrier layer 104 is less than a solder wettability of a material of the metal layer 105; aligning the first semiconductor device structure 101 with a second semiconductor device structure 201 such that each of the plurality of bump structures 106 is aligned with a respective one of a plurality of second bonding structures 205 of the second semiconductor device structure 201, and a solder material 107 is between the metal layer 105 of each of the plurality of bump structures 106 and the respective one of the plurality of second bonding structures 205; and performing a reflow process to form a plurality of solder joints 109 extending between each of the plurality of bump structures 106 and the respective one of the plurality of second bonding structures 205 of the second semiconductor device structure 201.

[0104] In one embodiment, the method further includes providing a layer of solder material 107 on the metal layer 105 of each of the plurality of bump structures 106, wherein when each of the plurality of second bonding structures 205 includes a metal portion, aligning the first semiconductor device structure 101 with the second semiconductor device structure 201 includes bringing the layer of solder material 107 and the metal portion of the plurality of second bonding structures 205 into contact with each other, and the metal layer 105 of each of the plurality of bump structures 106 has a first thickness Tl, the metal portion of the plurality of second bonding structures 205 has a second thickness T2, the layer of solder material 107 has a third thickness T3, and the sum of the first thickness Tl and the second thickness T2 is equal to or greater than one-half of the third thickness T3.

[0105] In another embodiment, the method further includes providing a first layer of solder material 107 on the metal layer 105 of each of the plurality of bump structures 106, and providing a second layer of solder material 214 on each of the plurality of second bonding structures 205, and wherein each of the plurality of second bonding structures 205 includes a barrier layer 212 located between a pair of metal portions 211, 213, aligning the first semiconductor device structure 101 with the second semiconductor device structure 201 includes bringing the first layer of solder material 107 and the second layer of solder material 214 into contact with each other, the sum of the combined thicknesses of the metal portions 211, 213 in the second bonding structure 205 is equal to or greater than one-half of the combined thicknesses of the first layer of solder material 107 and the second layer of solder material 214, and the thickness of the barrier layer 104 of the plurality of bump structures 106 is equal to or greater than the thickness of the barrier layer 212 of the second bonding structure 205.

[0106] In another embodiment, a plurality of intermediate redistribution layer pads 103 having different sizes or shapes are formed on the backside surface 132 of the first semiconductor substrate 102, and at least one bump structure 106 is formed on each of the intermediate redistribution layer pads 103, and all of the bump structures 106 formed on the intermediate redistribution layer pads 103 have the same size and shape.

[0107] In another embodiment, each of the intermediate redistribution layer pads 103 and the bump structures 106 are formed by electroplating.

[0108] In one embodiment, a semiconductor device includes a first device structure and a second device structure. The first device structure includes a first semiconductor substrate, an intermediate redistribution layer pad, and a plurality of bump structures electrically connected to the intermediate redistribution layer pad, wherein the intermediate redistribution layer pad is between the first semiconductor substrate and the plurality of bump structures. Each of the plurality of bump structures includes a metal layer and a barrier layer, wherein the barrier layer is between the metal layer and the intermediate redistribution layer pad, and a solder wetting property of the metal layer is greater than a solder wetting property of the barrier layer. The second device structure includes a second semiconductor substrate and a plurality of second bonding structures. A plurality of solder joints are between the metal layer of the plurality of bump structures of the first device structure and the plurality of second bonding structures of the second device structure.

[0109] In one embodiment, wherein the first device structure includes a plurality of through-substrate vias (TSVs) extending through the first semiconductor substrate, the intermediate redistribution layer pad is on a backside surface of the first semiconductor substrate and electrically contacts at least one of the through-substrate vias.

[0110] In one embodiment, wherein the intermediate redistribution layer pad includes a first intermediate redistribution layer pad, and the first device structure further includes a second intermediate redistribution layer pad on the backside surface of the first semiconductor substrate and electrically contacting at least one of the through-substrate vias, and at least one bump structure electrically contacting the second intermediate redistribution layer pad and coupled to a respective one of the plurality of second bonding structures of the second device structure by a solder joint, wherein at least one of a size or a shape of the first intermediate redistribution layer pad is different from a respective size or shape of the second intermediate redistribution layer pad, a total number of the plurality of bump structures electrically contacting the first intermediate redistribution layer pad is different from a total number of the at least one bump structure electrically contacting the second intermediate redistribution layer pad, and the plurality of bump structures electrically contacting the first intermediate redistribution layer pad and the at least one bump structure electrically contacting the second intermediate redistribution layer pad have a same critical dimension.

[0111] In one embodiment, wherein the plurality of bump structures electrically contacting the first intermediate redistribution layer pad transmit a first type of signal between the first device structure and the second device structure, and the at least one bump structure electrically contacting the second intermediate redistribution layer pad transmits a second type of signal between the first device structure and the second device structure.

[0112] In one embodiment, wherein the first type of signal includes a power signal, and the second type of signal includes a data signal.

[0113] In one embodiment, wherein the metal layer of each of the plurality of bump structures comprises at least one of copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof, and the barrier layer of the plurality of bump structures comprises at least one of nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof.

[0114] In one embodiment, wherein the metal layer of each of the plurality of bump structures and the metal layer of the middle redistribution layer pad are formed of the same material.

[0115] In one embodiment, wherein a width dimension of the barrier layer of each of the plurality of bump structures is greater than a width dimension of the metal layer of each of the plurality of bump structures.

[0116] In one embodiment, wherein each of the plurality of second bonding structures comprises a barrier layer between a pair of metal portions, and in the plurality of second bonding structures, a solder wettability of the pair of metal portions is greater than a solder wettability of the barrier layer.

[0117] In one embodiment, wherein a thickness of the barrier layer of each of the plurality of bump structures is equal to or greater than a thickness of the barrier layer of the plurality of second bonding structures.

[0118] In one embodiment, wherein each of the plurality of second bonding structures comprises a metal portion, and a width dimension of the metal portion of the plurality of second bonding structures is greater than a width dimension of the metal layer of each of the plurality of bump structures.

[0119] In one embodiment, wherein the metal layer of each of the plurality of bump structures comprises an upper surface that contacts the solder joint, and a maximum variation in a vertical height along a perimeter of the upper surface of each of the plurality of bump structures is 0.8 pm or less.

[0120] In one embodiment, a semiconductor device comprises a first device structure and a second device structure. The first device structure comprises a first semiconductor substrate, a middle redistribution layer pad, and a plurality of bump structures electrically connected to the middle redistribution layer pad, wherein the middle redistribution layer pad is between the first semiconductor substrate and the plurality of bump structures, each of the plurality of bump structures comprises a metal layer, and a solder wettability of the metal layer of each of the plurality of bump structures is greater than a solder wettability of the middle redistribution layer pad. The second device structure comprises a second semiconductor substrate and a plurality of second bonding structures. A plurality of solder joints are between the metal layer of the plurality of bump structures of the first device structure and the plurality of second bonding structures of the second device structure.

[0121] In one embodiment, wherein the metal layer of each of the plurality of bump structures comprises at least one of copper (Cu), palladium (Pd), rhodium (Rh), gold (Au), silver (Ag), alloys thereof, and combinations thereof, and the intermediate redistribution line landing pad comprises at least one of nickel (Ni), iron (Fe), tungsten (W), alloys thereof, and combinations thereof.

[0122] In one embodiment, wherein each of the plurality of bump structures comprises a barrier layer between the metal layer and the intermediate redistribution line landing pad, and a composition of the barrier layer is different from a composition of the metal layer.

[0123] In one embodiment, a method of manufacturing a vertically stacked semiconductor device includes the following steps. An intermediate redistribution line landing pad is formed on a backside surface of a first semiconductor substrate of a first semiconductor device structure. A plurality of bump structures is formed on the intermediate redistribution line landing pad, wherein each of the plurality of bump structures comprises a barrier layer on the intermediate redistribution line landing pad and a metal layer on the barrier layer, and a solder wettability of a material of the barrier layer is less than a solder wettability of a material of the metal layer. The first semiconductor device structure is aligned with a second semiconductor device structure such that each of the plurality of bump structures is aligned with a respective one of a plurality of second bonding structures of the second semiconductor device structure, and a solder material is located between the metal layer of each of the plurality of bump structures and the respective one of the plurality of second bonding structures. A reflow process is performed to form a plurality of solder joints extending between each of the plurality of bump structures and the respective one of the plurality of second bonding structures of the second semiconductor device structure.

[0124] In one embodiment, the method further includes: providing a solder material layer on the metal layer of each of the plurality of bump structures, wherein: each of the plurality of bump structures comprises a metal portion; aligning the first semiconductor device structure with the second semiconductor device structure includes bringing the solder material layer and the metal portions of the plurality of second bonding structures into contact with each other; and the metal layer of each of the plurality of bump structures has a first thickness, the metal portions of the plurality of second bonding structures have a second thickness, the solder material layer has a third thickness, and a sum of the first thickness and the second thickness is equal to or greater than one-half of the third thickness.

[0125] In one embodiment, the method further includes: providing a first solder material layer on the metal layer of each of the plurality of bump structures; and providing a second solder material layer on each of the plurality of second bonding structures, wherein: each of the plurality of second bonding structures includes a barrier layer between a pair of metal portions, aligning the first semiconductor device structure with the second semiconductor device structure includes bringing the first semiconductor device structure and the second semiconductor device structure into contact with each other such that the first solder material layer contacts the second solder material layer, a sum of a combined thickness of the metal portions of the plurality of second bonding structures is equal to or greater than one-half of a combined thickness of the first solder material layer and the second solder material layer, and a thickness of the barrier layer of the plurality of bump structures is equal to or greater than a thickness of the barrier layer of the plurality of second bonding structures.

[0126] In one embodiment, wherein a plurality of intermediate redistribution layer pads having different sizes or shapes are formed on the backside surface of the first semiconductor substrate, and at least one bump structure is formed on each of the intermediate redistribution layer pads, and all of the bump structures formed on the intermediate redistribution layer pads have the same size and shape.

[0127] In one embodiment, wherein each of the intermediate redistribution layer pads and the plurality of bump structures are formed by electroplating.

[0128] The foregoing outlines features of several embodiments so that a person having ordinary skill in the art can better understand the aspects of the disclosure. Those of ordinary skill in the art will appreciate that they can freely combine the disclosure described herein with yet other contexts and features, and understand that such equivalents will not depart from the spirit and scope of the disclosure. Those of ordinary skill in the art will also appreciate that they can make various changes, substitutions and alterations without departing from the spirit and scope of the disclosure.

Claims

1. A semiconductor device comprising: a first device structure comprising: a first semiconductor substrate; an intermediate redistribution layer pad; and a plurality of bump structures electrically connected to the intermediate redistribution layer pad, wherein the intermediate redistribution layer pad is located between the first semiconductor substrate and the plurality of bump structures, each of the plurality of bump structures comprising: a metal layer; and a barrier layer, wherein the barrier layer is located between the metal layer and the intermediate redistribution layer pad, and a solder wetting property of the metal layer is greater than a solder wetting property of the barrier layer; a second device structure comprising a second semiconductor substrate and a plurality of second bonding structures; and a plurality of solder joints located between the metal layer of the plurality of bump structures of the first device structure and the plurality of second bonding structures of the second device structure.

2. The semiconductor device of claim 1, wherein the first device structure comprises a plurality of substrate vias extending through the first semiconductor substrate, the intermediate redistribution layer pad is located on a backside surface of the first semiconductor substrate and electrically contacts at least one of the substrate vias.

3. The semiconductor device of claim 2, wherein the intermediate redistribution layer pad comprises a first intermediate redistribution layer pad, and the first device structure further comprises: a second intermediate redistribution layer pad located on the backside surface of the first semiconductor substrate and electrically contacts at least one of the substrate vias; and at least one bump structure electrically contacts the second intermediate redistribution layer pad and is coupled to a respective one of the plurality of second bonding structures of the second device structure by a solder joint, wherein: at least one of a size or a shape of the first intermediate redistribution layer pad is different from a respective size or shape of the second intermediate redistribution layer pad; a total number of the plurality of bump structures electrically contacting the first intermediate redistribution layer pad is different from a total number of the at least one bump structure electrically contacting the second intermediate redistribution layer pad; and a critical dimension of the plurality of bump structures electrically contacting the first intermediate redistribution layer pad and the at least one bump structure electrically contacting the second intermediate redistribution layer pad is the same.

4. The semiconductor device of claim 3, wherein the plurality of bump structures electrically contacting the first intermediate redistribution layer pad transmit a first type of signal between the first device structure and the second device structure, and the at least one bump structure electrically contacting the second intermediate redistribution layer pad transmits a second type of signal between the first device structure and the second device structure.

5. The semiconductor device of claim 4, wherein the first type of signal comprises a power signal, and the second type of signal comprises a data signal.

6. The semiconductor device of claim 1, wherein a width dimension of the barrier layer of each of the plurality of bump structures is greater than a width dimension of the metal layer of each of the plurality of bump structures. ​ 7. The semiconductor device of claim 1, wherein each of the plurality of second bonding structures includes a barrier layer between a pair of metal portions, and among the plurality of second bonding structures, a solder wettability of the pair of metal portions is greater than a solder wettability of the barrier layer.

8. The semiconductor device of claim 1, wherein a thickness of the barrier layer of each of the plurality of bump structures is equal to or greater than a thickness of the barrier layer of the plurality of second bonding structures.

9. The semiconductor device of claim 1, wherein each of the plurality of second bonding structures includes a metal portion, and a width dimension of the metal portion of the plurality of second bonding structures is greater than a width dimension of the metal layer of each of the plurality of bump structures.

10. A semiconductor device, comprising: a first device structure, comprising: a first semiconductor substrate; an intermediate redistribution layer pad; and a plurality of bump structures electrically connected to the intermediate redistribution layer pad, wherein the intermediate redistribution layer pad is between the first semiconductor substrate and the plurality of bump structures, each of the plurality of bump structures includes a metal layer, and a solder wettability of the metal layer of each of the plurality of bump structures is greater than a solder wettability of the intermediate redistribution layer pad; a second device structure, comprising a second semiconductor substrate and a plurality of second bonding structures; and a plurality of solder joints between the metal layer of the plurality of bump structures of the first device structure and the plurality of second bonding structures of the second device structure.

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