Narrow high-performance memory bank board

Abstract

The utility model discloses a narrow-strip high-performance memory strip board which comprises a memory strip board circuit board, a first BGA particle, a second BGA particle, a third BGA particle and a fourth BGA particle are arranged on the front face of the memory strip board circuit board, and a fifth BGA particle, a sixth BGA particle, a seventh BGA particle and an eighth BGA particle are arranged on the back face of the memory strip board circuit board. The board width of the memory strip board circuit board is smaller than or equal to 28 mm, the number of layers of the memory strip board circuit board is eight, L1, L3, L6 and L8 are wiring layers, and L2, L4, L5 and L7 are a power supply layer and a grounding layer. Particles are distributed on the front face and the back face, the board width is reduced, the number of wiring layers is reduced, the cost is reduced, meanwhile, the signal transmission path is shortened, address lines are in cross connection through L3 / L6 layers, data lines are in layered wiring, signal delay and attenuation are remarkably reduced, the copper foil fully covers the power supply layer, stable power supply is ensured, electromagnetic interference is reduced, and the signal-to-noise ratio is improved.

Description

TECHNICAL FIELD

[0001] The utility model belongs to the technical field of memory bank, specifically relates to a narrow strip high -performance memory bank board. BACKGROUND

[0002] As Figures 4-6 As shown in the figure, the conventional standard width of DDR5 generation SODIMM memory bank product is 30mm, adopts single eight particles ten layers board, is suitable for notebook computer and the like small -size equipment.

[0003] The address line and data line need to be connected to the particle pad through multilayer wiring, which results in long signal transmission time, low efficiency, high delay, and frequency usually being 4800-5600MHz, and the overclocking performance is limited. UTILITY MODEL CONTENTS

[0004] The utility model discloses a narrow strip high -performance memory bank board to solve the technical defects of the existing memory bank, such as many layers, wide board surface, long signal transmission time, low efficiency and high frequency limitation.

[0005] To achieve the above object, the utility model adopts the following technical scheme:

[0006] A narrow strip high -performance memory bank board, comprising a memory bank circuit board, the front of the memory bank circuit board is provided with a first BGA particle, a second BGA particle, a third BGA particle and a fourth BGA particle, and the back of the memory bank circuit board is provided with a fifth BGA particle, a sixth BGA particle, a seventh BGA particle and an eighth BGA particle.

[0007] The board width of the memory bank circuit board is ≤28mm, and the number of layers is eight, wherein L1, L3, L6 and L8 are wiring layers, L4 and L5 are power layers, and L2 and L7 are ground layers.

[0008] As a preferred scheme of the utility model, the address lines CA0_A-CA12_A and CA0_B-CA12_B on the memory bank circuit board are led out from the golden finger, pass through the L1 or L8 layer wiring and via hole, and are connected to the corresponding particle pads on the front and back through the L3 and L6 layers.

[0009] As a preferred scheme of the utility model, the data lines DQ0_A-DQ31_A and DQ0_B-DQ31_B on the memory bank circuit board are led out from the golden finger, pass through the L1 or L8 layer wiring and via hole, and are connected to the corresponding particle pads on the front and back through the L3 and L6 layers.

[0010] As the preferred scheme of the utility model, the perpendicular distance difference of the BGA particle on the double sides of the memory strip board circuit board to the data line of the golden finger is less than or equal to 2.0 mm.

[0011] As the preferred scheme of the utility model, L2, L4, L5 and L7 layers adopt copper foil full coverage.

[0012] As the further preferred scheme of the utility model, the support frequency range of the narrow strip high performance memory strip board is 5200-6400 MHz, and the signal transmission delay is less than or equal to 1.2 ns.

[0013] Compared with the prior art, the utility model has the following beneficial effects;

[0014] 1. Double-sided layout and layer number optimization: the particles are distributed on the double sides and the board width is reduced to less than or equal to 28 mm, the number of wiring layers is reduced, the cost is reduced, and the signal transmission path is shortened.

[0015] 2. Layered wiring and cross connection: the address line is cross connected through L3 / L6 layers, and the data line is layered through L3 / L6 layers, which significantly reduces signal delay and attenuation.

[0016] 3. Power and signal integrity: copper foil full coverage power layer ensures stable power supply, reduces electromagnetic interference and improves signal-to-noise ratio.

[0017] 4. Balanced transmission path: the perpendicular distance difference of the positive and negative particles to the golden finger is less than or equal to 2.0 mm, which eliminates synchronization error and improves multi-channel efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical scheme of the embodiments of the utility model, the drawings needed in the embodiments will be briefly introduced below, and obviously, the drawings in the following description are only one case of the embodiments of the utility model, and those skilled in the art can obtain other drawings according to these drawings without creating creative labor.

[0019] Figure 1 It is the front structure schematic view of the embodiment of the utility model;

[0020] Figure 2 It is the back structure schematic view of the embodiment of the utility model;

[0021] Figure 3 It is the layer structure schematic view of the embodiment of the utility model;

[0022] Figure 4 It is the front structure schematic view of the memory strip board in the prior art;

[0023] Figure 5It is a rear view structure schematic diagram of the memory strip board in the prior art.

[0024] Figure 6 It is a layer structure schematic diagram of the memory strip board in the prior art.

[0025] Reference signs:

[0026] 1, first BGA particle; 2, second BGA particle; 3, third BGA particle; 4, fourth BGA particle; 5, fifth BGA particle; 6, sixth BGA particle; 7, seventh BGA particle; 8, eighth BGA particle; 9, memory strip board circuit board. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical scheme and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0028] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "front", "rear", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the embodiments of the present application.

[0029] In the description of the embodiments of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, integrally connected, or detachably connected; it can be the communication inside two elements; it can be directly connected, or indirectly connected through an intermediate medium; for those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0030] Referring to the drawings Figures 1-3 The embodiments of the present application are a kind of narrow strip high-performance memory strip board, including memory strip board circuit board 9, the front of memory strip board circuit board 9 is arranged with first BGA particle 1, second BGA particle 2, third BGA particle 3 and fourth BGA particle 4, and the back of memory strip board circuit board 9 is arranged with fifth BGA particle 5, sixth BGA particle 6, seventh BGA particle 7 and eighth BGA particle 8.

[0031] The board width of memory strip board circuit board 9 is ≤28mm, and the number of layers is eight, wherein L1, L3, L6, L8 are trace layers, L4, L5 are power layers, and L2, L7 are ground layers.

[0032] The memory strip board circuit board 9 is a double-sided particle layout, that is, the first BGA particle 1 corresponds to the fifth BGA particle 5, the second BGA particle 2 corresponds to the sixth BGA particle 6, the third BGA particle 3 corresponds to the seventh BGA particle 7, and the fourth BGA particle 4 corresponds to the eighth BGA particle 8. The double-sided layout shortens the signal transmission path, reduces the number of board layers and width, and reduces the cost. The eight-layer structure optimizes the power and ground layer distribution, improves signal integrity, the memory strip board circuit board 9 has a board width ≤ 28 mm, the board width is reduced, the overall performance of the product is improved, and the cost is reduced.

[0033] The address lines CA0_A-CA12_A and CA0_B-CA12_B on the memory strip board circuit board 9 are led out from the gold finger, pass through the L1 or L8 layer traces and vias, are connected to the corresponding particle pads on the front and back surfaces through the L3 and L6 layers, and the address lines CA0_A-CA12_A and CA0_B-CA12_B are connected to the front and back particles through the L3 / L6 layers, so that the address line transmission delay is reduced, the front and back particle address line paths are symmetrical, and the timing consistency is improved.

[0034] Specifically, the address lines CA0_A, CA1_A, CA2_A, CA4_A, CA6_A, CA8_A, CA10_A, and CA12_A are arranged on the front surface and connected to the L3 or L6 layer traces through the L1 layer traces and vias. The traces pass under the second BGA particle 2 and the fourth BGA particle 4, then pass under the first BGA particle 1 and the third BGA particle 3, are connected to the pads of the second BGA particle 2 and the fourth BGA particle 4 through the vias and surface traces, and are connected to the pads of the first BGA particle 1 and the third BGA particle 3 through the vias and surface traces.

[0035] The address lines CA3_A, CA5_A, CA7_A, CA9_A, and CA11_A are arranged on the back surface L8 layer, are connected to the L3 or L6 layer traces through the L8 layer traces and vias, pass under the second BGA particle 2 and the fourth BGA particle 4, then pass under the first BGA particle 1 and the third BGA particle 3, are connected to the pads of the second BGA particle 2 and the fourth BGA particle 4 through the vias and surface traces, and are connected to the pads of the first BGA particle 1 and the third BGA particle 3 through the vias and surface traces.

[0036] The address line CA11_B, CA9_B, CA7_B, CA5_B, CA3_B finger pin is arranged on the front face, is connected to the L3 or L6 layer wire through the L1 layer wire and the hole, and the wire passes through the third BGA particle 3 and the seventh BGA particle 7 below in turn, then passes through the fourth BGA particle 4 and the eighth BGA particle 8 below, is connected to the pad of the third BGA particle 3 and the seventh BGA particle 7 through the via hole and the surface layer wire, and is connected to the pad of the fourth BGA particle 4 and the eighth BGA particle 8 through the hole and the surface layer wire.

[0037] The address line CA12_B, CA10_B, CA8_B, CA6_B, CA4_B, CA2_B, CA1_B, CA0_B pin is arranged on the back L8 layer, is connected to the L3 or L6 layer wire through the L8 layer wire and the hole, and the wire passes through the third BGA particle 3 and the seventh BGA particle 7 below in turn, then passes through the fourth BGA particle 4 and the eighth BGA particle 8 below, is connected to the pad of the third BGA particle 3 and the seventh BGA particle 7 through the via hole and the surface layer wire, and is connected to the pad of the fourth BGA particle 4 and the eighth BGA particle 8 through the hole and the surface layer wire.

[0038] After the data line DQ0_A-DQ31_A and DQ0_B-DQ31_B on the memory stick board circuit board 9 is led out from the gold finger, the data line is transmitted vertically at a distance of ≤14.2mm through the L1 or L8 layer wire and the via hole, the L3 and L6 layer layered wire, the data line DQ0_A-DQ31_A / B is transmitted vertically at a distance of ≤14.2mm through the L3 / L6 layer layered wire, the signal attenuation is reduced, the frequency is supported to be promoted to 6400MHz, the layered wire reduces crosstalk, and the data stability is improved.

[0039] Specifically, the data line DQ0_A, DQ2_A, DQ4_A, DQ6_A, DQ8_A, DQ10_A, DQ12_A and DQ14_A are arranged on the front gold finger, are connected to the L3 or L6 wire through the L1 layer wire and the hole, and are connected to the corresponding line PAD of the first BGA particle 1 and the fifth BGA particle 5 through the hole.

[0040] The data line DQ1_A, DQ3_A, DQ5_A, DQ7_A, DQ9_A, DQ11_A, DQ13_A and DQ15_A are arranged on the back gold finger, are connected to the L3 or L6 wire through the L8 wire and the hole, and are connected to the corresponding line PAD of the first BGA particle 1 and the fifth BGA particle 5 through the hole.

[0041] Data lines DQ16_A, DQ18_A, DQ20_A, DQ22_A, DQ24_A, DQ26_A, DQ28_A, DQ30_A are designed on the front side of the gold finger, connected to the lines of L3 or L6 through the L1 layer of the lines and the holes, and then connected to the corresponding lines PAD of the second BGA particle 2 and the sixth BGA particle 6 through the holes.

[0042] Data lines DQ17_A, DQ19_A, DQ21_A, DQ23_A, DQ25_A, DQ27_A, DQ29_A, DQ31_A are designed on the back side of the gold finger, connected to the lines of L3 or L6 through the L8 layer of the lines and the holes, and then connected to the corresponding lines PAD of the second BGA particle 2 and the sixth BGA particle 6 through the holes.

[0043] Data lines DQ0_B, DQ2_B, DQ4_B, DQ6_B, DQ8_B, DQ10_B, DQ12_B, DQ14_B are designed on the front side of the gold finger, connected to the lines of L3 or L6 through the L1 layer of the lines and the holes, and then connected to the corresponding lines PAD of the third BGA particle 3 and the seventh BGA particle 7 through the holes.

[0044] Data lines DQ1_B, DQ3_B, DQ5_B, DQ7_B, DQ9_B, DQ11_B, DQ13_B, DQ15_B are designed on the back side of the gold finger, connected to the lines of L3 or L6 through the L8 layer of the lines and the holes, and then connected to the corresponding lines PAD of the third BGA particle 3 and the seventh BGA particle 7 through the holes.

[0045] Data lines DQ16_B, DQ18_B, DQ20_B, DQ22_B, DQ24_B, DQ26_B, DQ28_B, DQ30_B are designed on the front side of the gold finger, connected to the lines of L3 or L6 through the L1 layer of the lines and the holes, and then connected to the corresponding lines PAD of the fourth BGA particle 4 and the eighth BGA particle 8 through the holes.

[0046] Data lines DQ17_B, DQ19_B, DQ21_B, DQ23_B, DQ25_B, DQ27_B, DQ29_B, DQ31_B are designed on the back side of the gold finger, connected to the lines of L3 or L6 through the L8 layer of the lines and the holes, and then connected to the corresponding lines PAD of the fourth BGA particle 4 and the eighth BGA particle 8 through the holes.

[0047] The vertical distance difference between the BGA particles on the front and back surfaces of the memory strip circuit board 9 and the data lines of the gold finger is less than or equal to 2.0 mm, the vertical distance difference between the front and back particles and the data lines of the gold finger is less than or equal to 2.0 mm, the signal delay difference between the front and back surfaces is balanced, the data synchronization error is less than or equal to 0.5 ns, and the multi-channel parallel transmission efficiency is improved.

[0048] The L2, L4, L5 and L7 layers adopt a copper foil full coverage design, reduce power impedance, reduce voltage fluctuation (fluctuation range is less than or equal to 5%), shield external electromagnetic interference, and improve signal-to-noise ratio by 15 dB.

[0049] The narrow strip high-performance memory strip board supports a frequency range of 5200-6400 MHz, signal transmission delay is less than or equal to 1.2 ns, overclocking performance is improved by 30%, frequency stability reaches an industry leading level, and low delay design meets high-performance computing requirements.

[0050] In the use of the embodiment of the utility model, the signal transmission path is optimized: after the address line is led out from the gold finger, it is connected to the front and back particles through the L3 / L6 layers, and the cross connection reduces the cross-layer wiring. The data line adopts layered wiring (L3 / L6 layers), which shortens the physical distance to less than or equal to 14.2 mm and reduces transmission delay. In the process of power supply and grounding, the L2, L4, L5 and L7 layers are fully covered with copper foil, which provides a low-impedance power supply loop, stabilizes power supply and shields interference. The front and back particle signal path lengths are balanced, timing consistency is ensured through simulation calibration, and high-frequency stable operation is supported.

[0051] In summary, the double-sided layout and layer optimization of the narrow strip high-performance memory strip board of the embodiment of the utility model reduce the number of wiring layers, reduce costs, shorten signal transmission paths, significantly reduce signal delay and attenuation through layered wiring and cross connection, ensure power stability through power and signal integrity, reduce electromagnetic interference, improve signal-to-noise ratio, balance transmission paths, eliminate synchronization errors, and improve multi-channel efficiency.

[0052] The above shows and describes the basic principles of the present application, the above is only the preferred embodiment of the present application, and does not limit the present application, the above embodiment and the description in the specification only illustrate the principles of the present application, any modification, equivalent replacement and improvement made within the scope and spirit of the present application should be included in the protection scope of the present application.

Claims

1. A narrow high performance memory riser board comprising a memory riser board circuit board (9) characterized by: The front of the memory strip board circuit board (9) is arranged with a first BGA particle (1), a second BGA particle (2), a third BGA particle (3) and a fourth BGA particle (4), and the back of the memory strip board circuit board (9) is arranged with a fifth BGA particle (5), a sixth BGA particle (6), a seventh BGA particle (7) and an eighth BGA particle (8); The board width of the memory strip board circuit board (9) is ≤28mm, and the number of layers is eight, wherein L1, L3, L6 and L8 are trace layers, L4 and L5 are power layers, and L2 and L7 are ground layers.

2. The narrow high performance memory ribbon board of claim 1, wherein: The address lines CA0_A-CA12_A and CA0_B-CA12_B on the memory strip board circuit board (9) are led out from the gold finger, and then are connected to the corresponding particle pads on the front and back surfaces through L1 or L8 layer traces and vias, and L3 and L6 layer cross connection.

3. The narrow high performance memory ribbon board of claim 1, wherein: The data lines DQ0_A-DQ31_A and DQ0_B-DQ31_B on the memory strip board circuit board (9) are led out from the gold finger, and then are connected to the corresponding particle pads on the front and back surfaces through L1 or L8 layer traces and vias, and L3 and L6 layer cross connection.

4. The narrow high performance memory ribbon board of claim 1, wherein: The vertical distance difference between the BGA particles on the front and back surfaces of the memory strip board circuit board (9) and the data lines of the gold finger is ≤2.0mm.

5. The narrow high performance memory ribbon board of claim 1, wherein: The L2, L4, L5 and L7 layers are fully covered with copper foil.

6. The narrow high performance memory board of any of claims 1-5, wherein: The support frequency range of the narrow strip high-performance memory strip board is 5200-6400MHz, and the signal transmission delay is ≤1.2ns.

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