SIP radio frequency surface-mounted BPSK modulator

Abstract

The utility model discloses an SIP radio frequency surface-mounted BPSK modulator, which relates to the technical field of semiconductor radio frequency devices, and comprises a substrate and a phase-locked loop circuit arranged on the substrate, the phase-locked loop circuit is connected with a power divider and a differential buffer output unit, the power divider and the differential buffer output unit are connected with a modulation multiplier, and the modulation multiplier is connected with an SIP radio frequency surface-mounted BPSK modulator. The modulation multiplier is connected with a baseband processing unit and a first filter, the baseband processing unit is connected with a first signal input end, the first filter is connected with a switch modulation unit, the switch modulation unit is connected with a second signal input end and a second filter, and the second filter is connected with a signal output end. The device provided by the utility model has the advantages of small size, integration, multiple functions and good modulation effect.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor radio frequency device technology, specifically to a SIP radio frequency surface-mount BPSK modulator. Background Technology

[0002] Traditional SIP (System-in-Package) surface-mount BPSK (Binary Phase Shift Keying) modulators primarily employ two architectures. The first is a discrete component architecture: composed of independent components. While it can achieve IQ quadrature modulation, it suffers from severe carrier leakage (typically -40dBc to -50dBc), amplitude-phase imbalance, and limited functionality. Furthermore, the combination of multiple components leads to circuit complexity and high power consumption, making it difficult to meet the signal purity requirements of high-frequency communication. The second is a modular architecture: offering higher integration but with a larger size (typically exceeding 30×30×10mm). 3 While partial integration reduces carrier leakage, its large size makes surface-mount integration difficult, failing to meet the high-density design requirements of compact devices. Therefore, this architecture has significant shortcomings in carrier suppression, size, and functional scalability, limiting its application in compact RF systems. Utility Model Content

[0003] To address the shortcomings of existing technologies, this invention provides a SIP RF surface-mount BPSK modulator.

[0004] A surface-mount BPSK modulator for radio frequency (SIP) includes a substrate and a phase-locked loop (PLL) circuit disposed on the substrate. The PLL circuit is connected to a power divider and a differential buffer output unit. The power divider and differential buffer output unit are connected to a modulation multiplier. The modulation multiplier is connected to a baseband processing unit and a first filter. The baseband processing unit is connected to a first signal input terminal. The first filter is connected to a switching modulation unit. The switching modulation unit is connected to a second signal input terminal and a second filter. The second filter is connected to a signal output terminal. The first signal input terminal is used to input a first input signal to the baseband processing unit. The baseband processing unit is used to generate a baseband signal based on the first input signal and input the baseband signal to the modulation multiplier. The PLL circuit is used to receive an external reference signal and generate an initial carrier signal based on the external reference signal. The phase-locked loop circuit is also used to input the initial carrier signal to the power divider and differential buffer output unit. The power divider and differential buffer output unit are used to distribute the initial carrier signal and form the carrier signal to be processed. The power divider and differential buffer output unit are also used to input the carrier signal to be processed to the modulation multiplier. The modulation multiplier is used to form a modulation signal based on the baseband signal and the carrier signal to be processed and input the modulation signal to the first filter. The first filter is used to output the filtered modulation signal to the switching modulation unit. The second signal input terminal is used to input the second input signal to the switching modulation unit. The switching modulation unit is used to perform on-off modulation based on the second input signal and thereby complete the switching modulation. The second filter is used to filter the modulation signal passing through the switching modulation unit and input the filtered modulation signal to the signal output terminal.

[0005] Optionally, the phase-locked loop circuit includes a third signal input terminal, an LLP, a PFD, an LLCP, and an N-fold down-converting unit connected in sequence. The N-fold down-converting unit is connected to the power divider and the differential buffer output unit. The PFD is connected to a current-type charge pump, which is connected to a VCO. The VCO is connected to the power divider and the differential buffer output unit. The third signal input terminal is used to input an external reference signal to the LLP.

[0006] Optionally, a first diode is disposed between the modulation multiplier and the first filter, with the cathode of the first diode connected to the modulation multiplier and the anode of the first diode connected to the first filter.

[0007] Optionally, a second diode is provided between the second filter and the signal output terminal, with the cathode of the second diode connected to the second filter and the anode of the first diode connected to the signal output terminal.

[0008] Optionally, the switching modulation unit includes a nanosecond-level radio frequency switch made of gallium arsenide, which responds to level control of a second input signal.

[0009] Optionally, the N-fold down-frequency unit includes an integer frequency divider and a fractional frequency divider.

[0010] Optionally, the substrate is a multilayer ceramic substrate, and the package size is 16×16×4mm. 3 .

[0011] The beneficial effects of this utility model are reflected in:

[0012] The entire SIP RF surface-mount BPSK modulator achieves high integration and miniaturization. The SIP package enables the miniaturized integration of multi-functional modules (frequency synthesis, modulation, and filtering), reducing the size by 90% compared to traditional modules. It can be directly soldered onto PCBs, making it compatible with compact devices such as IoT terminals. At the same time, it achieves flexible scalability, allowing configuration of modulation modes, frequency bands, and switching logic via serial communication, supporting BPSK / QPSK switching, frequency hopping communication, and other scenarios, breaking through the functional limitations of traditional solutions. Finally, the entire process of chip design, tape-out, and packaging and testing is domestically produced, solving the risk of supply chain bottlenecks and ensuring independent control in sensitive fields such as military and satellite industries. Attached Figure Description

[0013] To more clearly illustrate the specific embodiments of this utility model or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0014] Figure 1 This is a connection diagram of the SIP RF surface-mount BPSK modulator of this utility model;

[0015] Figure 2 The BPSK modulation waveform of the SIP RF surface-mount BPSK modulator of this utility model is shown below.

[0016] Figure 3 This is the circuit schematic diagram of the SIP RF surface-mount BPSK modulator of this utility model.

[0017] Figure label:

[0018] 1-Phase-locked loop circuit, 11-Third signal input terminal, 2-Power divider and differential buffer output unit, 3-Modulation multiplier, 4-Baseband processing unit, 5-First filter, 6-First signal input terminal, 7-Switch modulation unit, 8-Second signal input terminal, 9-Second filter, 10-Signal output terminal, 12-First diode, 13-Second diode. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, not all embodiments. The components of the embodiments of this utility model described and shown in the accompanying drawings can typically be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] like Figure 1 , Figure 2 and Figure 3As shown, a SIP (Surface Mount BPSK) modulator is provided, including a substrate and a phase-locked loop (PLL) circuit disposed on the substrate. The PLL circuit is connected to a power divider and a differential buffer output unit. The power divider and the differential buffer output unit are connected to a modulation multiplier. The modulation multiplier is connected to a baseband processing unit and a first filter. The baseband processing unit is connected to a first signal input terminal. The first filter is connected to a switching modulation unit. The switching modulation unit is connected to a second signal input terminal and a second filter. The second filter is connected to a signal output terminal. The first signal input terminal is used to input a first input signal to the baseband processing unit. The baseband processing unit is used to generate a baseband signal based on the first input signal and input the baseband signal to the modulation multiplier. The PLL circuit is used to receive an external reference signal and generate an initial carrier signal based on the external reference signal. The phase-locked loop circuit is further configured to input the initial carrier signal to the power divider and differential buffer output unit, which are used to distribute the initial carrier signal and form a carrier signal to be processed. The power divider and differential buffer output unit are also configured to input the carrier signal to be processed to the modulation multiplier. The modulation multiplier is configured to form a modulation signal based on the baseband signal and the carrier signal to be processed and input the modulation signal to the first filter. The first filter is configured to output the filtered modulation signal to the switching modulation unit. The second signal input terminal is configured to input the second input signal to the switching modulation unit. The switching modulation unit is configured to perform on / off modulation based on the second input signal and thereby complete the switching modulation. The second filter is configured to filter the modulation signal passing through the switching modulation unit and input the filtered modulation signal to the signal output terminal.

[0023] In this embodiment, it should be noted that the phase-locked loop circuit achieves frequency-locked output. By reasonably selecting chip specifications, the initial carrier signal frequency can be output up to 4GHz. The initial carrier signal output is evenly distributed to the three output terminals through the power divider and differential buffer output unit, realizing the formation and output of the carrier signal to be processed, thus achieving the purpose of multi-functionality of the chip. One of the carrier signals to be processed after power division is input to the modulation multiplier.

[0024] The baseband signal and carrier signal of the modulation multiplier achieve 0° and 180° phase modulation in the modulator. The principle is described as follows: In this invention, the baseband processing unit is used to form a baseband signal based on the first input signal and input the baseband signal to the modulation multiplier. The baseband signal is a pseudo-random TTL level code (M+ and M- timing combination pair), where the high level of M+ is 1 and the low level is 0. This low level is guided to -1 after passing through the negative voltage buffer inside the multiplier. The local oscillator carrier is Acoswt. When the baseband signal is high: M output waveform = 1 × Acoswt = Acoswt, the phase and amplitude are consistent with the carrier; when the baseband signal is low: M output waveform = -1 × Acoswt = -Acoswt = Acos(wt+π), the amplitude is consistent with the carrier, and the phase deviates from the carrier by 180°; the above theoretical analysis realizes BPSK modulation.

[0025] Furthermore, after amplification, the modulated signal is filtered out by the first filter to remove harmonics and spurious signals, achieving a spurious signal suppression of 60dBc. The filtered modulated signal then passes through a switching modulation unit for switching modulation. This switching modulation, controlled by the second input signal (pseudo-random code M-), achieves on / off modulation of the switch. When M- is high (at which point there is no modulation signal in the pairing logic timing M+), the switch is in the off state, suppressing carrier transmission and achieving carrier leakage suppression. When M- is low, corresponding to the M+ modulation signal segment, the switch is in the on state, and the modulated waveform achieves low insertion loss transmission. The above theoretical and logical relationships achieve carrier leakage suppression, up to 83dBc. Finally, the modulated signal passes through the second filter for spectrum filtering and spurious signal suppression, ultimately completing the output.

[0026] In summary, this invention utilizes System-in-Package (SIP) technology to highly integrate core modules such as a phase-locked loop (PLL), modulation multiplier, high-speed RF switch, and filter onto a ceramic substrate, forming a surface-mount BPSK modulator. The specific process is as follows: Carrier generation and distribution: The PLL receives an external reference signal, generates a high-frequency carrier, and distributes it evenly into multiple signals via a power divider; one carrier is input to the modulation multiplier, while the other is reserved or used for feedback calibration to ensure carrier frequency stability. Example: In satellite communication scenarios, the PLL generates a C-band carrier, which is then distributed to the modulator and monitoring circuit by the power divider to achieve real-time carrier calibration and avoid signal distortion caused by frequency offset. BPSK Modulation and Leakage Suppression: The baseband processing unit converts the input pseudo-random code (such as M+ / M-) into a balanced differential signal, which is then multiplied by the carrier in the modulation multiplier to generate a BPSK modulated signal with a 0° or 180° phase. After the modulated signal is filtered to remove noise by the first filter, it is input to the high-speed RF switch. The switch is controlled by another baseband code (M-): when M- is high, the carrier path is closed to suppress leakage; when M- is low, the signal is turned on, allowing the modulated signal to pass through, and finally output after being purified by the second filter. Example: In 5G base stations, the baseband code controls the switch and modulator to be strictly synchronized, improving the carrier leakage suppression capability to 83dBc, significantly reducing adjacent channel interference, and meeting the requirements of high-density networking.

[0027] Therefore, the entire SIP RF surface-mount BPSK modulator achieves high integration and miniaturization. The SIP package enables the miniaturized integration of multi-functional modules (frequency synthesis, modulation, and filtering), reducing the size by 90% compared to traditional modules. It can be directly soldered onto PCBs and is compatible with compact devices such as IoT terminals. At the same time, it achieves flexible scalability, allowing configuration of modulation modes, frequency bands, and switching logic via serial communication, supporting BPSK / QPSK switching, frequency hopping communication, and other scenarios, breaking through the functional limitations of traditional solutions. Finally, the entire process of chip design, tape-out, and packaging and testing is domestically produced, solving the risk of supply chain bottlenecks and ensuring independent control in sensitive fields such as military and satellite industries.

[0028] In one embodiment, the phase-locked loop circuit includes a third signal input terminal, an LLP, a PFD, an LLCP, and an N-fold down-converting unit connected in sequence. The N-fold down-converting unit is connected to the power divider and the differential buffer output unit. The PFD is connected to a current-type charge pump, which is connected to a VCO. The VCO is connected to the power divider and the differential buffer output unit. The third signal input terminal is used to input an external reference signal to the LLP.

[0029] In this embodiment, it should be noted that the phase-locked loop (PLL) circuit is the core module of the entire modulator, used to generate a high-frequency carrier signal and ensure its frequency stability. Its architecture includes a reference signal input, a low-pass filter (LLP), a phase-frequency discriminator (PFD), a loop divider filter (LLCP), a charge pump (CP), a voltage-controlled oscillator (VCO), and an N-fold down-conversion unit. The external reference signal, after being filtered by the LLP, is input to the PFD and compared in phase with the feedback signal after frequency division from the VCO output. The resulting error signal is converted into a voltage by the CP, adjusting the VCO output frequency until it is locked. The N-fold down-conversion unit controls the output frequency range through the division ratio, while the power divider evenly distributes the carrier to the modulator and feedback path, achieving synchronous output of multiple signals.

[0030] In satellite communication scenarios, a phase-locked loop (PLL) receives a high-precision reference clock (such as a temperature-controlled crystal oscillator output) and dynamically adjusts the division ratio N to generate a C-band or Ku-band carrier. For example, when frequency-hopping communication is required, the PLL quickly switches the division ratio to achieve seamless carrier frequency switching. Simultaneously, the power divider distributes the carrier to the modulator and monitoring module, and the frequency offset is calibrated in real time through the feedback path to ensure extremely low signal phase noise and prevent communication link interruptions due to frequency deviation. Furthermore, the VCO's low-jitter design, combined with multi-stage filtering using LLP and LLCP, effectively suppresses power supply noise and external interference, ensuring carrier purity and meeting the high reliability requirements of complex electromagnetic environments.

[0031] In one embodiment, a first diode is disposed between the modulation multiplier and the first filter, with the cathode of the first diode connected to the modulation multiplier and the anode of the first diode connected to the first filter.

[0032] In this embodiment, it should be noted that the first diode, acting as a unidirectional conducting element, is used to suppress reverse interference of the modulation signal. When the BPSK signal output from the modulation multiplier is amplified, the diode transmits the signal to the first filter when forward-biased and blocks harmonic reflections when reverse-biased, thus preventing the modulator from self-oscillating. For example, in a radar system, this design can filter out the second harmonic generated by the modulator, ensuring the spectral purity of the transmitted signal.

[0033] In one embodiment, a second diode is disposed between the second filter and the signal output terminal, the cathode of the second diode being connected to the second filter and the anode of the first diode being connected to the signal output terminal.

[0034] In this embodiment, it should be noted that the second diode is used to isolate the output signal from reverse interference with the back-end circuitry. When the modulated signal is purified by the second filter, the diode conducts in the forward direction to output to the RF port, and blocks external noise (such as antenna reflection signals) from flowing back into the modulation link when it is reverse-biased. For example, in a 5G base station, this design can prevent signal reflection caused by antenna impedance mismatch from damaging the modulator and improve system reliability.

[0035] In one embodiment, the switching modulation unit includes a nanosecond-level radio frequency switch made of gallium arsenide, the nanosecond-level radio frequency switch responding to level control of a second input signal.

[0036] In this embodiment, it should be noted that the switching modulation unit uses a gallium arsenide (GaAs) process RF switch, whose high-speed response characteristics (nanosecond-level switching) are strictly synchronized with the baseband pseudo-random code (M-); its on-resistance is ≤1Ω, its turn-off isolation is ≥30dB, its switching time is ≤5ns, and it responds to the TTL level control of the second input signal (M-). For example, in frequency hopping communication, when M- is high, the switch is instantaneously turned off, blocking the carrier leakage path; when M- is low, it is turned on, allowing the modulation signal to pass through, achieving dynamic carrier suppression and avoiding interference from adjacent channels.

[0037] In one embodiment, the N-fold down-frequency unit includes an integer frequency divider and a fractional frequency divider.

[0038] In this embodiment, it should be noted that the N-fold down-frequency unit achieves coarse frequency band adjustment through integer frequency division, and finely adjusts the frequency step by combining fractional frequency division technology (such as Σ-Δ modulation); it supports a frequency step accuracy of ≤10Hz, and the output frequency covers 0.3GHz-3GHz. For example, in a satellite navigation terminal, integer frequency division generates an L-band carrier, and fractional frequency division finely adjusts the frequency to compensate for Doppler frequency shift, ensuring the signal tracking accuracy of the receiver in high dynamic scenarios.

[0039] In one embodiment, the substrate is a multilayer ceramic substrate, and the package size is 16×16×4mm. 3 .

[0040] In this embodiment, it should be noted that the substrate adopts a multilayer ceramic structure, and bare dies such as the phase-locked loop and modulator are integrated through gold wire bonding. Surface mount packaging allows for direct soldering to the PCB. Furthermore, the bare dies of the phase-locked loop circuit, modulation multiplier, and switching modulation unit are integrated through 0.18μm gold wire bonding technology to achieve surface mount (SMD) packaging. For example, in a drone communication module, this design integrates the traditionally separate phase-locked loop, modulator, and filter into a substrate the size of a fingernail, significantly reducing the device size and weight, and meeting the requirements of high-density integration.

[0041] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0042] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0043] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model, and they should all be covered within the scope of the claims and specification of this utility model.

Claims

1. A SIP (Surface Mount BPSK) modulator, comprising a substrate and a phase-locked loop circuit disposed on the substrate, characterized in that, The phase-locked loop circuit is connected to a power divider and a differential buffer output unit. The power divider and differential buffer output unit are connected to a modulation multiplier. The modulation multiplier is connected to a baseband processing unit and a first filter. The baseband processing unit is connected to a first signal input terminal. The first filter is connected to a switching modulation unit. The switching modulation unit is connected to a second signal input terminal and a second filter. The second filter is connected to a signal output terminal. The first signal input terminal is used to input a first input signal to the baseband processing unit, and the baseband processing unit is used to generate a baseband signal based on the first input signal and input the baseband signal to the modulation multiplier. The phase-locked loop circuit is used to receive an external reference signal and form an initial carrier signal based on the external reference signal. The phase-locked loop circuit is also used to input the initial carrier signal to the power divider and differential buffer output unit. The power divider and differential buffer output unit are used to distribute the initial carrier signal and form a carrier signal to be processed. The power divider and differential buffer output unit are also used to input the carrier signal to be processed to the modulation multiplier. The modulation multiplier is used to form a modulation signal based on the baseband signal and the carrier signal to be processed, and input the modulation signal into the first filter. The first filter is used to output the filtered modulation signal to the switching modulation unit. The second signal input terminal is used to input the second input signal to the switching modulation unit. The switching modulation unit is used to perform on / off modulation according to the second input signal and thereby complete the switching modulation. The second filter is used to filter the modulation signal passing through the switching modulation unit and input the filtered modulation signal to the signal output terminal.

2. The SIP RF surface-mount BPSK modulator according to claim 1, characterized in that, The phase-locked loop circuit includes a third signal input terminal, an LLP, a PFD, an LLCP, and an N-fold down-converting unit connected in sequence. The N-fold down-converting unit is connected to the power divider and the differential buffer output unit. The PFD is connected to a current-type charge pump, which is connected to a VCO. The VCO is connected to the power divider and the differential buffer output unit. The third signal input terminal is used to input an external reference signal to the LLP.

3. The SIP RF surface-mount BPSK modulator according to claim 1, characterized in that, A first diode is disposed between the modulation multiplier and the first filter, with the cathode of the first diode connected to the modulation multiplier and the anode of the first diode connected to the first filter.

4. The SIP RF surface-mount BPSK modulator according to claim 3, characterized in that, A second diode is provided between the second filter and the signal output terminal. The cathode of the second diode is connected to the second filter, and the anode of the first diode is connected to the signal output terminal.

5. The SIP RF surface-mount BPSK modulator according to claim 1, characterized in that, The switching modulation unit includes a nanosecond-level radio frequency switch made of gallium arsenide, which responds to level control of a second input signal.

6. The SIP RF surface-mount BPSK modulator according to claim 2, characterized in that, The N-fold down-frequency unit includes an integer frequency divider and a fractional frequency divider.

7. The SIP RF surface-mount BPSK modulator according to claim 1, characterized in that, The substrate is a multilayer ceramic substrate with a package size of 16×16×4mm. 3 .

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