Display panel and display device

Abstract

The utility model relates to the technical field of display, and provides a display panel and a display device.A pixel driving circuit in the display panel comprises a driving transistor and a first capacitor, the first electrode of the driving transistor is connected with a first power line, and the first capacitor is connected between the second electrode of the driving transistor and the grid electrode of the driving transistor; the display panel further comprises a substrate, a first conductive part, a second conductive part, a data line, a first fan-out line and a second fan-out line. At least part of the first conductive part is used for forming a first electrode of a first capacitor. The second conductive part is used for forming a second electrode of the first capacitor; the orthographic projection of the first fan-out line on the substrate is located on one side of the orthographic projection of the first conductive part on the substrate in the second direction; the second fan-out line is connected with the data line through the first fan-out line, and the orthographic projection of the second fan-out line on the substrate is located on one side of the orthographic projection of the first conductive part on the substrate in the first direction. The display panel can realize narrow frame arrangement.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, display panels need to have fan-out lines set in the bezel area, resulting in a wider bezel for the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit located in a display area, the pixel driving circuit including a driving transistor and a first capacitor, a first terminal of the driving transistor being connected to a first power supply line, and the first capacitor being connected between a second terminal of the driving transistor and the gate of the driving transistor.

[0005] The display panel also includes:

[0006] Substrate;

[0007] A first gate layer is located on one side of the substrate, and the first gate layer includes a first conductive portion, at least a portion of which is used to form a first electrode of the first capacitor.

[0008] The second gate layer is located on the side of the first gate layer away from the substrate. The second gate layer includes a second conductive portion. The orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The second conductive portion is used to form the second electrode of the first capacitor and is connected to the gate of the driving transistor.

[0009] A data line, at least partially located in the display area, the data line extending along a second direction by its orthogonal projection on the substrate, the data line being used to provide data signals to the pixel driving circuit;

[0010] The first fan-out line is at least partially located in the display area. The orthographic projection of the first fan-out line on the substrate extends along a first direction, which intersects with the second direction. The first fan-out line connects to the data line. The orthographic projection of the first fan-out line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is in the second direction.

[0011] The second fan-out line is at least partially located in the display area. The orthographic projection of the second fan-out line on the substrate extends along the second direction. The second fan-out line is connected to the data line through the first fan-out line. The orthographic projection of the second fan-out line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is in the first direction.

[0012] In an exemplary embodiment of this disclosure, the display panel includes a plurality of pixel units, the orthographic projections of the plurality of pixel units on the substrate are arrayed along the first direction and the second direction, the pixel unit includes a plurality of pixel driving circuits distributed along the first direction, and the orthographic projections of the plurality of pixel driving circuits in the display panel on the substrate are arrayed along the first direction and the second direction.

[0013] Wherein, the first direction is the row direction, the second direction is the column direction, and the orthographic projection of the first fan-out line on the substrate is located between the orthographic projections of two adjacent rows of pixel units on the substrate.

[0014] In one exemplary embodiment of this disclosure, the orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate are located between the orthographic projections of two adjacent rows of pixel units on the substrate.

[0015] In one exemplary embodiment of this disclosure, the orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate are respectively located between the orthographic projections of two adjacent rows of pixel units in different groups on the substrate.

[0016] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a driving transistor, a fifth transistor, and a seventh transistor. The first terminal of the fifth transistor is connected to a first power supply line, and the second terminal is connected to the first terminal of the driving transistor. The first terminal of the seventh transistor is connected to a second initial signal line, the second terminal is connected to a light-emitting unit, and the gate is connected to a first reset signal line.

[0017] Wherein, the orthographic projections of the first power line and the first reset signal line on the substrate extend along the first direction. In the same pixel driving circuit, the orthographic projection of the second conductive part on the substrate is located between the orthographic projections of the first power line and the first reset signal line on the substrate. The orthographic projection of the first fan-out line on the substrate is located between the orthographic projection of the first power line on the substrate in the current row of pixel driving circuit and the orthographic projection of the first reset signal line on the substrate in the adjacent previous row of pixel driving circuit.

[0018] In an exemplary embodiment of this disclosure, the display panel includes a plurality of pixel units, the orthographic projections of the plurality of pixel units on the substrate are arrayed along the first direction and the second direction, the pixel unit includes a plurality of pixel driving circuits distributed along the first direction, and the orthographic projections of the plurality of pixel driving circuits in the display panel on the substrate are arrayed along the first direction and the second direction.

[0019] Wherein, the first direction is the row direction, the second direction is the column direction, and the orthographic projection of the second fan-out line on the substrate is located between the orthographic projections of two adjacent column pixel units on the substrate.

[0020] In one exemplary embodiment of this disclosure, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are located between the orthographic projections of two adjacent columns of pixel units on the substrate.

[0021] In one exemplary embodiment of this disclosure, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are respectively located between the orthographic projections of two adjacent columns of pixel units in different groups on the substrate.

[0022] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a seventh transistor, the first terminal of which is connected to a second initial signal line, and the second terminal of which is connected to a light-emitting unit;

[0023] Each column of pixel units is provided with a second initial connection line. The orthographic projection of the second initial signal line on the substrate extends along the first direction. The orthographic projection of the second initial connection line on the substrate extends along the second direction. The second initial connection line and at least a portion of the second initial signal line intersecting with it are connected by vias.

[0024] The pixel unit includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are sequentially distributed along the first direction. The first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are used to drive light-emitting units of different colors.

[0025] The orthographic projection of the second conductive part of the third pixel driving circuit in this pixel unit on the substrate is at least partially located between the orthographic projection of the second initial connection line corresponding to this pixel unit on the substrate and the orthographic projection of the data line connected to the third pixel driving circuit in this pixel unit on the substrate.

[0026] The orthographic projection of the second fan-out line on the substrate is located between the orthographic projection of the second initial connection line corresponding to this pixel unit on the substrate and the orthographic projection of the data line connected to the first pixel driving circuit in the adjacent pixel unit on the substrate.

[0027] In an exemplary embodiment of this disclosure, the display panel includes a plurality of pixel units, the orthographic projections of the plurality of pixel units on the substrate are arrayed along the first direction and the second direction, the pixel unit includes a plurality of pixel driving circuits distributed along the first direction, and the orthographic projections of the plurality of pixel driving circuits in the display panel on the substrate are arrayed along the first direction and the second direction.

[0028] Wherein, the first direction is the row direction, the second direction is the column direction, and the orthographic projection of the second fan-out line on the substrate is located between the orthographic projections of two adjacent column pixel driving circuits in the same column pixel unit on the substrate.

[0029] In one exemplary embodiment of this disclosure, the orthographic projection of multiple second fan-out lines connected to the same column of pixel units onto the substrate lies between the orthographic projections of two adjacent columns of pixel driving circuits in the same column of pixel units onto the substrate.

[0030] In one exemplary embodiment of this disclosure, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are respectively located between the orthographic projections of two adjacent pixel driving circuits in different columns of pixel units on the substrate.

[0031] In an exemplary embodiment of this disclosure, the plurality of pixel driving circuits in the pixel unit include a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are sequentially distributed along the first direction.

[0032] In the same pixel unit, the orthographic projection of the data line connected to the second pixel driving circuit on the substrate and the orthographic projection of the data line connected to the third pixel driving circuit on the substrate are located between the orthographic projection of the second conductive part in the second pixel driving circuit on the substrate and the orthographic projection of the second conductive part in the third pixel driving circuit on the substrate.

[0033] The orthographic projection of the second fan-out line on the substrate is located between the orthographic projections of the second pixel driving circuit and the third pixel driving circuit on the substrate in the same column of pixel units;

[0034] The orthographic projection of the second fan-out line on the substrate is located between the orthographic projection of the data line connected to the second pixel driving circuit in the same column of pixel units on the substrate and the orthographic projection of the data line connected to the third pixel driving circuit on the substrate.

[0035] In one exemplary embodiment of this disclosure, the orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate are distributed at intervals in the second direction, and among the multiple first fan-out lines connected to the same column of pixel units, two adjacent first fan-out lines in the second direction are located in different conductive layers.

[0036] In one exemplary embodiment of this disclosure, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are distributed at intervals in the first direction, and among the multiple second fan-out lines connected to the same column of pixel units, adjacent second fan-out lines in the first direction are located in different conductive layers.

[0037] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a plurality of transistors, and the display panel further includes:

[0038] The first source / drain layer is located on the side of the second gate layer away from the substrate, and a portion of the structure in the first source / drain layer bridges different transistors.

[0039] The second source / drain layer is located on the side of the first source / drain layer that is away from the substrate.

[0040] The first fan-out line is located in the first source-drain layer, and the second fan-out line and data line are located in the second source-drain layer.

[0041] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a plurality of transistors, and the display panel further includes:

[0042] The first source / drain layer is located on the side of the second gate layer away from the substrate, and a portion of the structure in the first source / drain layer bridges different transistors.

[0043] The second source / drain layer is located on the side of the first source / drain layer that is away from the substrate.

[0044] The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the data line is located in the third source / drain layer;

[0045] Wherein, at least a portion of the first fan-out lines are located in the first source / drain layer and / or at least a portion of the first fan-out lines are located in the second source / drain layer.

[0046] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a plurality of transistors, and the display panel further includes:

[0047] The first source / drain layer is located on the side of the second gate layer away from the substrate, and a portion of the structure in the first source / drain layer bridges different transistors.

[0048] The second source / drain layer is located on the side of the first source / drain layer that is away from the substrate.

[0049] The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the data line is located in the third source / drain layer;

[0050] Wherein, at least a portion of the second fan-out lines are located in the second source / drain layer and / or at least a portion of the second fan-out lines are located in the third source / drain layer.

[0051] In an exemplary embodiment of this disclosure, the plurality of pixel driving circuits in the pixel unit include a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are sequentially distributed in the first direction.

[0052] The first pixel driving circuit and the second pixel driving circuit are arranged at least partially mirror-symmetrically in their orthogonal projections on the substrate, and the second pixel driving circuit and the third pixel driving circuit are arranged at least partially mirror-symmetrically in their orthogonal projections on the substrate.

[0053] In one exemplary embodiment of this disclosure, the pixel driving circuit includes one or more switching transistors. In the same pixel unit, the same type of switching transistors in the second pixel driving circuit and the third pixel driving circuit share the same conductive portion as the gate.

[0054] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a second capacitor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0055] The first electrode of the second capacitor is connected to the first electrode of the first capacitor, and the second electrode of the second capacitor is connected to the second electrode of the driving transistor;

[0056] The first terminal of the first transistor is connected to the first initial signal line, the second terminal is connected to the first electrode of the first capacitor, and the gate is connected to the third reset signal line.

[0057] The first terminal of the second transistor is connected to the first initial signal line, the second terminal is connected to the gate of the driving transistor, and the gate is connected to the second reset signal line;

[0058] The first terminal of the fourth transistor is connected to the data line, the second terminal is connected to the gate of the driving transistor, and the gate is connected to the gate line.

[0059] The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the first enable signal line.

[0060] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second enable signal line.

[0061] The first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the first reset signal line.

[0062] The first gate layer further includes a third conductive portion, which is connected to the first conductive portion in the same layer. At least a portion of the third conductive portion is used to form a first electrode of the second capacitor. The second gate layer further includes a fourth conductive portion, the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the third conductive portion on the substrate overlap at least partially. The fourth conductive portion is used to form a second electrode of the second capacitor. The orthographic projections of the second conductive portion on the substrate and the orthographic projections of the fourth conductive portion on the substrate are distributed along the column direction.

[0063] The display panel also includes:

[0064] An active layer is located on the side of the second gate layer away from the substrate. The active layer includes a first main active portion and a second main active portion. The orthographic projection of the first main active portion on the substrate and the orthographic projection of the second main active portion on the substrate extend along a second direction and are spaced apart in a first direction.

[0065] The first main active portion includes a first active portion, a second active portion, and a fourth active portion that are sequentially spaced apart along a second direction. The first active portion is used to form the channel region of the first transistor, the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor.

[0066] The second main active portion includes a sixth active portion, a third active portion, and a fifth active portion that are sequentially spaced along a second direction. The sixth active portion is used to form the channel region of a sixth transistor, the third active portion is used to form the channel region of a driving transistor, and the fifth active portion is used to form the channel region of a fifth transistor. The orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate.

[0067] In one exemplary embodiment of this disclosure, the display panel further includes:

[0068] The repair line extends along the first direction when its orthogonal projection is on the substrate.

[0069] The sixth bridging portion connects to the light-emitting unit, and the orthographic projections of the plurality of sixth bridging portions distributed in the first direction on the substrate overlap with the orthographic projections of the repair line on the substrate.

[0070] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0071] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0072] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0073] Figure 1 This is a schematic diagram of the structure of an exemplary embodiment of the display panel disclosed herein;

[0074] Figure 2 This is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein;

[0075] Figure 3 This is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein;

[0076] Figure 4 This is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein;

[0077] Figure 5 This is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein;

[0078] Figure 6 This is a schematic diagram of the structure of another exemplary embodiment of the display panel disclosed herein;

[0079] Figure 7 This is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel disclosed herein;

[0080] Figure 8 for Figure 7 The timing diagram of each node in a driving method of the pixel driving circuit shown is shown.

[0081] Figure 9 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0082] Figure 10 for Figure 9 The diagram shows the structural layout of the first gate layer in the display panel.

[0083] Figure 11 for Figure 9 The diagram shows the structural layout of the second gate layer in the display panel.

[0084] Figure 12 for Figure 9 The display panel shown contains the structural layout of the source layer;

[0085] Figure 13 for Figure 9 The diagram shows the structural layout of the third gate layer in the display panel.

[0086] Figure 14 for Figure 9 The diagram shows the structural layout of the first source / drain layer in the display panel.

[0087] Figure 15 for Figure 9 The diagram shows the structural layout of the second source / drain layer in the display panel.

[0088] Figure 16 for Figure 9 The diagram shows the structural layout of the electrode layer in the display panel;

[0089] Figure 17 for Figure 9 The diagram shows the stacked structure of the first gate layer and the second gate layer in the display panel.

[0090] Figure 18 for Figure 9 The diagram shows the stacked structure of the first gate layer, the second gate layer, and the active layer in the display panel.

[0091] Figure 19 for Figure 9 The diagram shows the stacked structure of the first gate layer, second gate layer, active layer, and third gate layer in the display panel.

[0092] Figure 20 for Figure 9 The diagram shows the stacked structure of the first gate layer, second gate layer, active layer, third gate layer, and first source / drain layer in the display panel.

[0093] Figure 21 for Figure 9 The diagram shows the stacked structure of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel.

[0094] Figure 22 for Figure 9 The diagram shows a partial cross-sectional view of the display panel cut along the dashed line AA.

[0095] Figure 23 This is a structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0096] Figure 24 for Figure 23 The diagram shows the structural layout of the second source / drain layer in the display panel.

[0097] Figure 25 for Figure 23 The diagram shows the structural layout of the third source / drain layer in the display panel.

[0098] Figure 26 for Figure 23 The diagram shows the stacked structure of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel.

[0099] Figure 27 This is a layout diagram of the stacked structure of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure.

[0100] Figure 28 This is a layout diagram of the stacked structure of the first source / drain layer and the second source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0101] Figure 29 This is a structural layout of the third source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0102] Figure 30 This is a layout diagram of the stacked structure of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure.

[0103] Figure 31 This is a layout diagram of the stacked structure of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure.

[0104] Figure 32 This is a layout diagram of the stacked structure of the first source / drain layer and the second source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0105] Figure 33 This is a structural layout of the third source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0106] Figure 34 This is a layout diagram of the stacked structure of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure.

[0107] Figure 35 This is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure.

[0108] Figure 36 This is a partial stack-up structure layout of the first source / drain layer and the second source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0109] Figure 37 This is a partial structural layout of the first source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0110] Figure 38 This is a partial structural layout of the second source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0111] Figure 39 This is a partial structural layout of the third source / drain layer in an exemplary embodiment of the display panel disclosed herein;

[0112] Figure 40 This is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in another exemplary embodiment of the display panel disclosed herein;

[0113] Figure 41 This is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in another exemplary embodiment of the display panel disclosed herein;

[0114] Figure 42 This is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in another exemplary embodiment of the display panel disclosed herein;

[0115] Figure 43 This is a partial stack-up layout of the first source / drain layer and the second source / drain layer in another exemplary embodiment of the display panel disclosed herein;

[0116] Figure 44 This is a partial stacked structure layout of the first source / drain layer and the second source / drain layer in another exemplary embodiment of the display panel disclosed herein. Detailed Implementation

[0117] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0118] The terms “a,” “one,” and “” are used to indicate the existence of one or more elements / components / etc.; the terms “include” and “have” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0119] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0120] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0121] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0122] like Figure 1The diagram shown is a structural schematic of an exemplary embodiment of the display panel of this disclosure. The display panel includes a display area AA, within which are disposed a data line Da, a first fan-out line FIPH, and a second fan-out line FIPV. The first fan-out line FIPH and the second fan-out line FIPV are located on different conductive layers. The first fan-out line FIPH extends along a first direction X, while the data line Da and the second fan-out line FIPV extend along a second direction Y. The first direction X and the second direction Y intersect, where the first direction X can be a row direction and the second direction Y can be a column direction. The first fan-out line FIPH connects the data line Da and the second fan-out line FIPV. The first fan-out line FIPH and the second fan-out line FIPV fan out the data lines located on both sides of the display panel in the first direction X near the center. Furthermore, since the first fan-out line FIPH and the second fan-out line FIPV are located in the display area, the width of the display panel bezel can be reduced.

[0123] like Figure 2 The diagram shown illustrates another exemplary embodiment of the display panel disclosed herein. The display area AA of this display panel may further include a first virtual fan-out line FIPHd and a second virtual fan-out line FIPVd, located on different conductive layers. The first virtual fan-out line FIPHd extends along a first direction X and is located in an area of ​​the display panel where no first fan-out line FIPH is provided. The second virtual fan-out line FIPVd extends along a second direction Y and is located in an area of ​​the display panel where no second fan-out line FIPV is provided. The first virtual fan-out line FIPHd and the second virtual fan-out line FIPVd enable the display panel to have approximately or uniform trace density in areas where the first fan-out line FIPH and the second fan-out line FIPV are provided and in areas where no first fan-out line FIPH and the second fan-out line FIPV are provided, thereby improving the uniformity of the display panel. The first virtual fan-out line FIPHd can be connected to the intersecting second virtual fan-out line FIPVd via to form a mesh structure. This mesh structure can connect the power lines and initial signal lines in the display panel to further improve the uniformity of the display panel.

[0124] like Figure 3The diagram shown illustrates the structure of another exemplary embodiment of the display panel disclosed herein. The display panel includes a substrate and a plurality of pixel units Pz located on one side of the substrate. The orthographic projections of the pixel units Pz onto the substrate are distributed in an array along a first direction X and a second direction Y. Each pixel unit Pz includes a plurality of pixel driving circuits. Within the same pixel unit Pz, the plurality of pixel driving circuits include a first pixel driving circuit PR, a second pixel driving circuit PG, and a third pixel driving circuit PB distributed along the first direction X. The first pixel driving circuit PR drives a red light-emitting unit, the second pixel driving circuit PG drives a green light-emitting unit, and the third pixel driving circuit PB drives a blue light-emitting unit.

[0125] like Figure 3 As shown, the display panel also has a first outgoing line FIPH and a second outgoing line FIPV within the display area. The first outgoing line FIPH is connected between the data line Da and the second outgoing line FIPV. Figure 3 As shown, the orthographic projection of the first fan-out line FIPH on the substrate lies between the orthographic projections of adjacent row pixel units Pz on the substrate, and the orthographic projections of multiple first fan-out lines connected to the same column pixel unit on the substrate lie between the orthographic projections of adjacent rows of pixel units in different groups on the substrate; the orthographic projection of the second fan-out line FIPV on the substrate lies between the orthographic projections of adjacent column pixel units Pz on the substrate, and the orthographic projections of multiple second fan-out lines connected to the same column pixel unit on the substrate lie between the orthographic projections of adjacent columns of pixel units in different groups on the substrate. Figure 3 As shown, a first fan-out line is provided between every two adjacent rows of pixel units, and a second fan-out line is provided between every two adjacent columns of pixel units. It should be understood that in other exemplary embodiments, the first fan-out line may not be provided between some adjacent rows of pixel units, and the second fan-out line may not be provided between some adjacent columns of pixel units.

[0126] It should be noted that adjacent rows of pixel units in different groups can be understood as combinations formed by two adjacent rows of pixel units that are not completely identical. For example, the group formed by the first row of pixel units and the second row of pixel units is a different group from the group formed by the second row of pixel units and the third row of pixel units. The group formed by the first row of pixel units and the second row of pixel units is also a different group from the group formed by the third row of pixel units and the fourth row of pixel units.

[0127] It should be understood that in other exemplary embodiments, the first fan-out line FIPH may also be located within the pixel unit Pz. For example, the orthographic projection of the first fan-out line FIPH on the substrate may overlap with the orthographic projection of the initial signal line or other signal lines within the pixel unit Pz on the substrate.

[0128] In other exemplary embodiments, the orthographic projection of the second fan-out line FIPV onto the substrate can be located between the orthographic projections of two adjacent columns of pixel driving circuits in the same pixel unit onto the substrate. For example, as Figure 4 The diagram shown is a structural schematic of another exemplary embodiment of the display panel of this disclosure. Figure 3 The difference in the display panel shown is that the orthographic projection of the second fan-out line FIPV on the substrate is located between the orthographic projection of the second pixel driving circuit PG on the substrate and the orthographic projection of the third pixel driving circuit PB on the substrate.

[0129] like Figure 5 The diagram shown is a structural schematic of another exemplary embodiment of the display panel of this disclosure. Figure 3 The difference in the display panel shown is that the orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate are located between the orthographic projections of two adjacent rows of pixel units on the substrate, and the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are located between the orthographic projections of two adjacent columns of pixel units on the substrate. For example... Figure 5 As shown, three first fan-out lines (FIPH) spaced apart in the second direction Y are provided between two adjacent rows of pixel units, and three second fan-out lines (FIPV) spaced apart in the first direction X are provided between two adjacent columns of pixel units. It should be understood that in other exemplary embodiments, other numbers of first fan-out lines (FIPH) may be provided between two adjacent rows of pixel units, and other numbers of second fan-out lines (FIPV) may be provided between two adjacent columns of pixel units.

[0130] like Figure 6 The diagram shown is a structural schematic of another exemplary embodiment of the display panel of this disclosure. Figure 4 The difference in the display panel shown is that the orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate lie between the orthographic projections of two adjacent rows of pixel units on the substrate. Similarly, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate lie between the orthographic projections of the second pixel driving circuit and the third pixel driving circuit within the same column of pixel units on the substrate. It should be understood that in other exemplary embodiments, other numbers of first fan-out lines (FIPH) may be provided between adjacent rows of pixel units, and other numbers of second fan-out lines (FIPV) may be provided between the second and third pixel driving circuits.

[0131] like Figure 7The diagram shown is a schematic representation of a pixel driving circuit in an exemplary embodiment of the display panel disclosed herein. This pixel driving circuit is used to drive a light-emitting unit to emit light. The pixel driving circuit includes: a plurality of switching transistors, a driving transistor T3, a first capacitor C1, and a second capacitor C2. The plurality of switching transistors includes: a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Specifically, the gate of the driving transistor T3 is connected to a first node N1, its first electrode is connected to a second node N2, and its second electrode is connected to a third node N3; the first electrode of the first capacitor C1 is connected to a fourth node N4, and its second electrode is connected to the first node N1; the first electrode of the second capacitor C2 is connected to the fourth node N4, and its second electrode is connected to the third node N3; the first electrode of the first transistor T1 is connected to a first initial signal terminal Vinit1, its second electrode is connected to the fourth node N4, and its gate is connected to a third reset signal terminal Re3; the first electrode of the second transistor T2 is connected to the first initial signal terminal Vinit1, its second electrode is connected to the first node N1, and its gate is connected to a second reset signal terminal Re2; the fourth transistor T3... The first electrode of transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first node N1, and the gate is connected to the gate drive signal terminal Gate; the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the second node N2, and the gate is connected to the first enable signal terminal EM1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first electrode of the light-emitting unit L, and the gate is connected to the second enable signal terminal EM2; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the first reset signal terminal Re1; the second electrode of the light-emitting unit L is connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be an anode, and the second electrode can be a cathode.

[0132] like Figure 7 As shown, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be N-type transistors.

[0133] like Figure 8 As shown, Figure 7 The diagram shows the timing of each node in a driving method of the pixel driving circuit. The driving method of this pixel driving circuit includes: a reset phase t1, a threshold compensation phase t2, a data writing phase t3, and a light emission phase t4.

[0134] During the reset phase t1: the first reset signal terminal Re1, the second reset signal terminal Re2, the third reset signal terminal Re3, and the second enable signal terminal EM2 output high-level signals. The first transistor T1, the second transistor T2, the sixth transistor T6, and the seventh transistor T7 are turned on. The first initial signal terminal Vinit1 outputs the first initial signal to the first node N1 and the fourth node N4. The second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L and the third node N3.

[0135] During the threshold compensation stage t2: the second reset signal terminal Re2, the third reset signal terminal Re3, and the first enable signal terminal EM1 output high-level signals, the first transistor T1, the second transistor T2, and the fifth transistor T5 are turned on, and the first power supply terminal VDD inputs the compensation voltage V1-Vth to the third node N3, where V1 is the voltage of the first initial signal and Vth is the threshold voltage of the driving transistor.

[0136] During the data writing phase t3: the third reset signal terminal Re3 and the gate drive signal terminal Gate output high-level signals, the first transistor T1 and the fourth transistor T4 are turned on, and the data signal terminal Da inputs a data signal to the first node N1. The voltage of the first node N1 is Vdata, and Vdata is the voltage of the data signal.

[0137] During the light-emitting stage t4: the first enable signal terminal EM1 and the second enable signal terminal EM2 output high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the driving transistor T3 increases the driving current to the light-emitting unit L. The output current of the driving transistor T3 is I = (μWCox / 2L)(Vgs-Vth). 2 =(μWCox / 2L)(Vdata-(V1-Vth)-Vth) 2 =(μWCox / 2L)(Vdata-V1) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current, where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor.

[0138] This exemplary embodiment also provides a display panel, which may include a first gate layer, a second gate layer, an active layer, a third gate layer, a first source / drain layer, a second source / drain layer, and an electrode layer stacked sequentially. An insulating layer is disposed between the aforementioned layers. Figures 9-21 As shown, Figure 9 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 10 for Figure 9The diagram shows the structural layout of the first gate layer in the display panel. Figure 11 for Figure 9 The diagram shows the structural layout of the second gate layer in the display panel. Figure 12 for Figure 9 The display panel shown contains the structure layout of the source layer. Figure 13 for Figure 9 The diagram shows the structural layout of the third gate layer in the display panel. Figure 14 for Figure 9 The diagram shown is a structural layout of the first source / drain layer in the display panel. Figure 15 for Figure 9 The diagram shows the structural layout of the second source / drain layer in the display panel. Figure 16 for Figure 9 The diagram shows the structural layout of the electrode layer in the display panel. Figure 17 for Figure 9 The diagram shows the stacked structure of the first gate layer and the second gate layer in the display panel. Figure 18 for Figure 9 The diagram shows the stacked structure of the first gate layer, the second gate layer, and the active layer in the display panel. Figure 19 for Figure 9 The diagram shows the stacked structure of the first gate layer, second gate layer, active layer, and third gate layer in the display panel. Figure 20 for Figure 9 The diagram shows the stacked structure layout of the first gate layer, second gate layer, active layer, third gate layer, and first source / drain layer in the display panel. Figure 21 for Figure 9 The diagram shows the stacked structure of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel.

[0139] like Figure 21 As shown, the display panel may include multiple pixel units, which can be arrayed along a first direction X and a second direction Y. The pixel driving circuit group includes three adjacent pixel driving circuits in the first direction X: a first pixel driving circuit PR, a second pixel driving circuit PG, and a third pixel driving circuit PB. The structure of the pixel driving circuit can be as follows: Figure 7 As shown.

[0140] like Figure 21 As shown, in the same pixel unit, the first pixel driving circuit PR and the second pixel driving circuit PG are at least partially mirror-symmetrically arranged on the substrate, and the second pixel driving circuit PG and the third pixel driving circuit PB are at least partially mirror-symmetrically arranged on the substrate.

[0141] like Figure 9 , 10As shown in Figure 17, the first gate layer may include a first conductive portion 11, a third conductive portion 13, and a first via connection portion 12 connected in the same layer. The first conductive portion 11 is used to form the first electrode of the first capacitor C1, and the third conductive portion 13 is used to form the first electrode of the second capacitor C2.

[0142] like Figure 9 , 11 As shown in Figure 17, the second gate layer includes: a second conductive portion 22, a fourth conductive portion 24, and a repair line RP. The orthographic projection of the second conductive portion 22 on the substrate overlaps with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 is used to form the second electrode of the first capacitor C1. The orthographic projection of the fourth conductive portion 24 on the substrate overlaps with the orthographic projection of the third conductive portion 13 on the substrate, and the fourth conductive portion 24 is used to form the second electrode of the second capacitor C2. The orthographic projection of the repair line RP on the substrate extends along the first direction X.

[0143] like Figure 9 , 12As shown in Figure 18, the active layer may include: a first main active unit 701, a second main active unit 702, a seventh active unit 77, a fourteenth active unit 714, and a fifteenth active unit 715. The first main active unit 701 includes: a first active unit 71, a second active unit 72, a fourth active unit 74, an eighth active unit 78, a tenth active unit 710, and an eleventh active unit 711. The second main active unit 702 includes: a third active unit 73, a fifth active unit 75, a sixth active unit 76, a twelfth active unit 712, and a thirteenth active unit 713. The first active portion 71 is used to form the channel region of the first transistor T1; the second active portion 72 is used to form the channel region of the second transistor T2; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to the end of the first active portion 71 away from the second active portion 72; and the ninth active portion... Section 79 is connected between the first active section 71 and the second active section 72; the tenth active section 710 is connected between the second active section 72 and the fourth active section 74; the eleventh active section 711 is connected to the end of the fourth active section 74 away from the second active section 72; the twelfth active section 712 is connected to the end of the fifth active section 75 away from the third active section 73; the thirteenth active section 713 is connected between the third active section 73 and the sixth active section 76; the fourteenth active section 714 is connected between the sixth active section 76 and the seventh active section 77; and the fifteenth active section 715 is connected to the end of the seventh active section 77 away from the sixth active section 76. The active layer can be formed of indium gallium zinc oxide (IGaZN), and correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-type metal-oxide transistors.

[0144] like Figure 9 , 12 As shown in Figure 18, the orthogonal projection of the fourth conductive part 24 on the substrate covers the orthogonal projection of the third active part 73 on the substrate. The fourth conductive part 24 can shield the third active part 73 from light to reduce the influence of light on the characteristics of the driving transistor T3.

[0145] like Figure 9 , 13As shown in Figure 19, the third gate layer may include: a first enable signal line EM1, a second enable signal line EM2, a fifth conductive portion 35, a sixth conductive portion 36, a seventh conductive portion 37, an eighth conductive portion 38, a ninth conductive portion 39, and a second via connection portion 310. The first enable signal line EM1 and the second enable signal line EM2 extend along the first direction X on the substrate. The first enable signal line EM1 is used to provide... Figure 7 The first enable signal terminal and the second enable signal line EM2 are used to provide... Figure 7 The second enable signal terminal is shown in the diagram. The orthogonal projection of the first enable signal line EM1 onto the substrate covers the orthogonal projection of the fifth active portion 75 onto the substrate. A portion of the structure of the first enable signal line EM1 can be used to form the top gate of the fifth transistor T5. The orthogonal projection of the second enable signal line EM2 onto the substrate covers the orthogonal projection of the sixth active portion 76 onto the substrate. A portion of the structure of the second enable signal line EM2 can be used to form the top gate of the sixth transistor T6. The orthogonal projection of the fifth conductive portion 35 onto the substrate covers the orthogonal projection of the third active portion 73 onto the substrate. The fifth conductive portion 35 is used to form the top gate of the driving transistor T3. The orthogonal projection of the sixth conductive portion 36 onto the substrate covers the orthogonal projection of the fourth active portion 74 onto the substrate. The sixth conductive portion 36 is used to form the top gate of the fourth transistor T4. The orthogonal projection of the seventh conductive portion 37 onto the substrate covers the orthogonal projection of the second active portion 72 onto the substrate. The seventh conductive portion 37 is used to form the top gate of the second transistor. The orthographic projection of the eighth conductive portion 38 onto the substrate covers the orthographic projection of the first active portion 71 onto the substrate. The eighth conductive portion 38 is used to form the top gate of the first transistor T1. The orthographic projection of the ninth conductive portion 39 onto the substrate covers the orthographic projection of the seventh active portion 77 onto the substrate. The ninth conductive portion 39 is used to form the top gate of the driving transistor T3. The second via connection portion 310 and the fifth conductive portion 35 are connected in the same layer. In the same pixel unit, the same type of switching transistor in the second pixel driving circuit and the third pixel driving circuit can share the same conductive portion as its gate. For example, the fourth transistor in the second pixel driving circuit and the third pixel driving circuit can share the sixth conductive portion 36 as its top gate, the second transistor in the second pixel driving circuit and the third pixel driving circuit can share the seventh conductive portion 47 as its top gate, and the first transistor in the second pixel driving circuit and the third pixel driving circuit can share the eighth conductive portion 48 as its top gate. The display panel can use the third gate layer as a mask to conduct the active layer, that is, the area of ​​the active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the active layer not covered by the third gate layer forms a conductor structure.

[0146] like Figure 9 , 14As shown in Figure 20, the first source / drain layer may include: a first power line VDD, a second power line VSS, a gate line Gate, a first reset signal line Re1, a second reset signal line Re2, a third reset signal line Re3, a first initial signal line Vinit1, a second initial signal line Vinit2, a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, and a sixth bridging portion 46. The first power line VDD, the second power line VSS, the gate line Gate, the first reset signal line Re1, the second reset signal line Re2, the third reset signal line Re3, the first initial signal line Vinit1, and the second initial signal line Vinit2 have their orthogonal projections on the substrate extending along a first direction X. The first power line VDD is used to provide... Figure 7 The first power supply terminal; the gate line is used to provide... Figure 7 The gate drive signal terminal; the first reset signal line Re1 is used to provide Figure 7 The first reset signal terminal; the second reset signal line Re2 is used to provide Figure 7 The second reset signal terminal; the third reset signal line Re3 is used to provide Figure 7 The third reset signal terminal; the first initial signal line Vinit1 is used to provide Figure 7 The first initial signal terminal; the second initial signal line Vinit2 is used to provide Figure 7 The second initial signal terminal, the second power line VSS, is used to provide... Figure 7The second power supply terminal is connected to the twelfth active part 712 via a via, connecting to the first terminal of the fifth transistor T5. The gate line Gate is connected to the sixth conductive part 36 via a via, connecting to the gate drive signal terminal and the top gate of the fourth transistor T4. The second reset signal line Re2 is connected to the seventh conductive part 37 via a via, connecting to the second reset signal terminal and the top gate of the second transistor T2. The first initial signal line Vinit1 is connected to the ninth active part 79 via a via, connecting to the first initial signal terminal and the first terminal of the second transistor T2 and the first terminal of the first transistor T1. The third reset signal line Re3 is connected to the eighth conductive part 38 via a via, connecting to the third reset signal terminal and the top gate of the first transistor T1. The second initial signal line Vinit2 is connected to the fifteenth active part 715 via a via, connecting to the second initial signal terminal and the first terminal of the seventh transistor T7. The first reset signal line Re1 is connected to the ninth conductive part 39 via a via, connecting to the first reset signal terminal and the gate of the seventh transistor. The first bridging portion 41 can be connected to the eleventh active portion 711 via a via, thereby connecting the first electrode of the fourth transistor T4. The second bridging portion 42 can be connected to the fifth conductive portion 35 and the tenth active portion 710 via vias respectively. The fourth bridging portion 44 can be connected to the second via connection portion 310 and the second conductive portion 22 via vias respectively, thereby connecting the second electrode of the first capacitor C1 and the second electrode of the fourth transistor T4 and the second electrode of the second transistor T2. The third bridging portion 43 can be connected to the thirteenth active portion 713 and the fourth conductive portion 24 via vias respectively, thereby connecting the second electrode of the driving transistor T3 and the second electrode of the second capacitor C2. The fifth bridging portion 45 can be connected to the first via connection portion 12 and the eighth active portion 78 via vias respectively, thereby connecting the second electrode of the first transistor T1 and the first electrode of the second capacitor C2 and the first electrode of the first capacitor C1. The sixth bridging portion 46 can be connected to the fourteenth active portion 714 via a via, thereby connecting the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0147] like Figure 9 , 15 As shown in Figure 21, the second source / drain layer includes: a data line Da, a first power connection line 5VDD, a second power connection line 5VSS, a first initial connection line 5Vinit1, a second initial connection line 5Vinit2, and a seventh bridge portion 57. The orthographic projections of the data line Da, the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 onto the substrate extend along the second direction Y. The data line Da is used to provide... Figure 7In the display panel, the data signal terminal, data line Da, is connected to the first bridge portion 41 via a via to connect the data signal terminal and the first terminal of the fourth transistor. The first power connection line 5VDD is connected to at least a portion of the first power line VDD intersecting with it via a via. The first power connection line 5VDD and the first power line VDD can form a grid structure to reduce the voltage difference at different locations of the first power terminal on the display panel, thereby improving the uniformity of the display panel. The first initial connection line 5Vinit1 is connected to at least a portion of the first initial signal line Vinit1 intersecting with it via a via. The first initial connection line 5Vinit1 and the first initial signal line Vinit1 can form a grid structure to reduce the voltage difference at different locations of the first initial signal terminal on the display panel, thereby improving the uniformity of the display panel. The second initial connection line 5Vinit2 is connected to at least a portion of the second initial signal line Vinit2 intersecting with it via a via. The second initial connection line 5Vinit2 and the second initial signal line Vinit2 can form a grid structure to reduce the voltage difference at different locations of the second initial signal terminal on the display panel, thereby improving the uniformity of the display panel. The second power connection line 5VSS is connected via a via to a second power line VSS intersecting its orthographic projection on the substrate. The second power connection line 5VSS and the second power line VSS form a mesh structure at least in the display area. This mesh structure can be connected to a common cathode in the display panel to reduce the voltage difference between the second power terminals at different locations on the display panel. The common cathode in the display panel is used to form the cathode of the light-emitting unit, and the common cathode can be located on the side of the light-emitting unit L facing away from the substrate. The seventh bridging portion 57 can be connected to the sixth bridging portion 46 via a via.

[0148] like Figure 9 , 16 As shown, the electrode layer includes multiple electrode sections, including a first electrode section R, a second electrode section G, and a third electrode section B. The first electrode section R forms the first electrode of the red light-emitting unit, the second electrode section G forms the first electrode of the green light-emitting unit, and the third electrode section B forms the first electrode of the blue light-emitting unit. Each electrode section is connected to its corresponding seventh bridge section 57 via vias to connect the second electrode of the sixth transistor T6 and the first electrode of the light-emitting unit. Specifically, the first pixel driving circuit PR drives the red light-emitting unit, the second pixel driving circuit PG drives the green light-emitting unit, and the third pixel driving circuit PB drives the blue light-emitting unit.

[0149] In this exemplary embodiment, as Figures 9-21As shown, the orthographic projections of the plurality of sixth bridging portions 46 distributed in the first direction onto the substrate and the orthographic projections of the repair line RP onto the substrate at least partially overlap. When a bright or dark spot defect occurs in the display panel, the sixth bridging portion 46 in the defective pixel driving circuit and the repair line RP can be connected by a laser, and the sixth bridging portion 46 in the normal pixel driving circuit and the repair line RP can be connected simultaneously. This allows the light-emitting unit in the defective pixel to be driven by the normal pixel driving circuit. The normal pixel driving circuit can be a virtual pixel driving circuit located on the periphery of the display area or other pixel driving circuits located within the display area.

[0150] like Figure 22 As shown, Figure 9 The diagram shows a partial cross-sectional view of the display panel taken along the dashed line AA. The display panel may further include a first insulating layer 101, a buffer layer 102, a second insulating layer 103, a dielectric layer 104, a passivation layer 105, a first planarization layer 106, and a second planarization layer 107. The substrate 100, first gate layer, first insulating layer 101, second gate layer, buffer layer 102, active layer, second insulating layer 103, third gate layer, dielectric layer 104, first source / drain layer, passivation layer 105, first planarization layer 106, second source / drain layer, second planarization layer 107, and electrode layer are sequentially stacked. The buffer layer 102, the first insulating layer 101, the second insulating layer 103, and the passivation layer 105 can be single-layer or multi-layer structures, and the materials of the buffer layer 102, the first insulating layer 101, and the second insulating layer 103 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the dielectric layer 104 can be a silicon nitride layer; the materials of the first planarization layer 106 and the second planarization layer 107 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The substrate 100 can include a substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0151] This exemplary embodiment also provides another display panel, in Figure 9 Based on the display panel shown, a third source / drain layer is added between the second source / drain layer and the electrode layer. For example... Figures 23-26 As shown, Figure 23This is a structural layout diagram of another exemplary embodiment of the display panel of this disclosure. Figure 24 for Figure 23 The diagram shows the structural layout of the second source / drain layer in the display panel. Figure 25 for Figure 23 The diagram shown is a structural layout of the third source / drain layer in the display panel. Figure 26 for Figure 23 The diagram shows the stacked structure layout of the first gate layer, second gate layer, active layer, third gate layer, first source / drain layer, and second source / drain layer in the display panel. Compared to... Figure 9 The display panel shown is shown. Figure 23 The display panel shown sets the data line Da to the third source / drain layer.

[0152] It should be understood that, in other exemplary embodiments, the display panel of the three-layer source-drain layer architecture may also have the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, the second initial connection line 5Vinit2, and the data line Da all located in the third source-drain layer.

[0153] like Figures 23-26 As shown, the third source / drain layer also includes an eighth bridging section 68, which can be connected between the seventh bridging section 57 and the light-emitting unit.

[0154] Figures 3-6 The fan-out configuration shown can be applied to... Figure 9 The dual-layer source-drain architecture shown can also be applied to Figure 23 The three-layer source / drain architecture is shown.

[0155] like Figures 27-29 As shown, Figure 27 This is a layout diagram of the stacked structure of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 28 This is a layout diagram of the stacked structure of the first source / drain layer and the second source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 29 This is a structural layout of the third source / drain layer in an exemplary embodiment of the display panel disclosed herein. The display panel will... Figure 3 The fan-out configuration shown is applied to a three-layer source-drain architecture.

[0156] like Figures 27-29As shown, the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 are disposed on the third source / drain layer. The first fan-out line FIPH is located on the second source / drain layer, and the second fan-out line FIPV is located on the third source / drain layer. The orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate lie between the orthographic projections of two adjacent rows of pixel units in different groups on the substrate. Similarly, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate lie between the orthographic projections of two adjacent columns of pixel units in different groups on the substrate.

[0157] like Figures 27-29 As shown, in the same pixel driving circuit, the orthographic projection of the second conductive part 22 on the substrate is located between the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. The orthographic projection of the first fan-out line FIPH on the substrate is located between the orthographic projection of the first power line VDD on the substrate in the current row pixel driving circuit and the orthographic projection of the first reset signal line Re1 on the substrate in the adjacent previous row pixel driving circuit. The first power line VDD and the first reset signal line Re1 can shield the signal interference of the first fan-out line FIPH to the second conductive part 22, that is, shield the signal interference of the first fan-out line FIPH to the gate of the driving transistor. Each pixel unit Pz is provided with a corresponding second initial connection line 5Vinit2. The orthographic projection of the second conductive part 22 of the third pixel driving circuit in this pixel unit onto the substrate is at least partially located between the orthographic projection of the second initial connection line 5Vinit2 corresponding to this pixel unit onto the substrate and the orthographic projection of the data line Da connected to the third pixel driving circuit in this pixel unit onto the substrate. The orthographic projection of the second fan-out line FIPV onto the substrate is located between the orthographic projection of the second initial connection line 5Vinit2 corresponding to this pixel unit onto the substrate and the orthographic projection of the data line connected to the first pixel driving circuit in the adjacent pixel unit onto the substrate. The second initial connection line 5Vinit2 and the data line Da can shield the second fan-out line FIPV from interference to the second conductive part.

[0158] like Figure 30 The diagram shown is a structural layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure. Figure 27 The difference is that the display panel shown is that... Figure 30The display panel shown has the first fan-out line FIPH disposed on the first source / drain layer, and the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 disposed on the second source / drain layer. Since the data line Da is located on a different conductive layer from the first power connection line 5VDD and the second initial connection line 5Vinit2, the data line Da can have a smaller distance from them. This arrangement saves space in the display panel in the first direction. It should be understood that in other exemplary embodiments, Figure 30 One or more of the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 in the display panel shown can also be set in the third source / drain layer.

[0159] like Figures 31-33 As shown, Figure 31 This is a layout diagram of the stacked structure of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 32 This is a layout diagram of the stacked structure of the first source / drain layer and the second source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 33 This is a structural layout of the third source / drain layer in an exemplary embodiment of the display panel disclosed herein. The display panel will... Figure 4 The fan-out configuration shown is applied to a three-layer source-drain architecture.

[0160] like Figures 31-33 As shown, the orthographic projection of the first fan-out line FIPH on the substrate is located between the orthographic projections of adjacent row pixel units on the substrate; the orthographic projection of the second fan-out line FIPV on the substrate is located between the orthographic projections of the second pixel driving circuit PG and the third pixel driving circuit PB on the substrate. The first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, the second initial connection line 5Vinit2, and the data line Da are disposed in the third source-drain layer, the first fan-out line FIPH is located in the second source-drain layer, and the second fan-out line FIPV is located in the third source-drain layer.

[0161] like Figures 31-33As shown, the orthographic projection of the first fan-out line FIPH on the substrate lies between the orthographic projection of the first power line VDD in the current row of pixel driving circuits on the substrate and the orthographic projection of the first reset signal line Re1 in the adjacent previous row of pixel driving circuits on the substrate. Within the same pixel unit, the orthographic projections of the data line Da connected to the second pixel driving circuit PG and the data line Da connected to the third pixel driving circuit PB on the substrate lie between the orthographic projections of the second conductive part 22 in the second pixel driving circuit and the second conductive part 22 in the third pixel driving circuit on the substrate; the orthographic projection of the second fan-out line FIPV on the substrate lies between the orthographic projections of the data line Da connected to the second pixel driving circuit and the data line Da connected to the third pixel driving circuit in the same column of pixel units. The data line Da can shield the second fan-out line FIPV from interference to the gate of the driving transistor.

[0162] like Figures 31-33 As shown, the display panel may be provided with a second virtual fan-out line FIPVd. The orthographic projection of the second virtual fan-out line FIPVd on the substrate is located between the orthographic projection of the data line Da connected to the second pixel driving circuit and the orthographic projection of the data line Da connected to the third pixel driving circuit on the substrate. The data line Da connected to the second pixel driving circuit can be connected to the nearest second virtual fan-out line FIPVd on the same layer. The first fan-out line FIPH can be connected to the second virtual fan-out line FIPVd through a via, so that the data line Da is connected to the first fan-out line FIPH through the second virtual fan-out line FIPVd. The data line Da connected to the first pixel driving circuit can be directly connected to the first fan-out line FIPH through a via, or it can be connected to the first fan-out line FIPH through the second virtual fan-out line connected on the same layer. Similarly, the data line Da connected to the third pixel driving circuit can be directly connected to the first fan-out line FIPH through a via, or it can be connected to the first fan-out line FIPH through the second virtual fan-out line connected on the same layer. Furthermore, in other exemplary embodiments, the data line Da connected to the second pixel driving circuit can also be directly connected to the first fan-out line FIPH through a via.

[0163] like Figure 34 The diagram shown is a structural layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel of this disclosure. Figure 31 The difference is that the display panel shown is that... Figure 34The display panel shown has the first fan-out line FIPH located on the first source / drain layer, and the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 located on the second source / drain layer. This arrangement also saves space in the display panel in the first direction. It should be understood that in other exemplary embodiments, Figure 34 One or more of the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 in the display panel shown can also be set in the third source / drain layer.

[0164] like Figures 35-39 As shown, Figure 35 This is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 36 This is a partial stack-up layout of the first source / drain layer and the second source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 37 This is a partial structural layout of the first source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 38 This is a partial structural layout of the second source / drain layer in an exemplary embodiment of the display panel disclosed herein. Figure 39 This is a partial structural layout of the third source / drain layer in an exemplary embodiment of the display panel disclosed herein. The display panel will... Figure 5 The fan-out configuration shown is applied to a three-layer source-drain architecture.

[0165] like Figures 35-39 As shown, in the same pixel driving circuit, the orthographic projection of the second conductive part 22 on the substrate is located between the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. The orthographic projection of the three first fan-out lines FIPH connected to the same pixel unit on the substrate is located between the orthographic projection of the first power line VDD connected to the pixel driving circuit of this row on the substrate and the orthographic projection of the first reset signal line Re1 connected to the pixel driving circuit of the adjacent previous row on the substrate. Each column of pixel units Pz is provided with a corresponding second initial connection line 5Vinit2. The orthographic projection of the second conductive part 22 of the third pixel driving circuit in this pixel unit on the substrate is at least partially located between the orthographic projection of the second initial connection line 5Vinit2 corresponding to this pixel unit on the substrate and the orthographic projection of the data line Da connected to the third pixel driving circuit in this pixel unit on the substrate. The orthographic projection of the three second fan-out lines FIPV connected to the same pixel unit on the substrate is located between the orthographic projection of the second initial connection line 5Vinit2 on the substrate and the orthographic projection of the data line Da on the substrate.

[0166] like Figures 35-39 As shown, the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 are located in the second source / drain layer, and the data line Da is located in the third source / drain layer. The first fan-out line FIPH can be located in the first source / drain layer, and the orthographic projections of multiple second fan-out lines FIPV connected to the same pixel unit on the substrate can be distributed at intervals along the first direction. Adjacent second fan-out lines FIPV can be located in different conductive layers. For example, among the three second fan-out lines FIPV connected to the same pixel unit, some second fan-out lines FIPV are located in the second source / drain layer, and some second fan-out lines FIPV are located in the third source / drain layer. This arrangement can reduce the distance between adjacent second fan-out lines FIPV, thereby saving space in the display panel in the first direction X. In this exemplary embodiment, the second fan-out lines FIPV connected to the first pixel driving circuit and the third pixel driving circuit can be located in the second source / drain layer, and the second fan-out lines FIPV connected to the second pixel driving circuit can be located in the third source / drain layer. Furthermore, in other exemplary embodiments, the second fan-out line FIPV connected to the first pixel driving circuit and the third pixel driving circuit may be located in the third source-drain layer, and the second fan-out line FIPV connected to the second pixel driving circuit may be located in the second source-drain layer.

[0167] It should be understood that, in other exemplary embodiments, the second outgoing FIPV may also be located in the second source-drain layer or in the third source-drain layer.

[0168] like Figure 40 The diagram shown is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in another exemplary embodiment of the display panel of this disclosure. Figure 35 The difference is that the display panel shown is that... Figure 40 The display panel shown has the first power connection line 5VDD, the second power connection line 5VSS, the first initial connection line 5Vinit1, and the second initial connection line 5Vinit2 set on the third source / drain layer.

[0169] like Figure 40 As shown, the orthographic projections of multiple first fan-out lines (FIPHs) connected to the same pixel unit on the substrate can be distributed at intervals along the second direction, and adjacent first fan-out lines (FIPHs) can be located in different conductive layers. This arrangement can save space in the display panel in the second direction. Among the three first fan-out lines (FIPHs) connected to the same pixel unit, some first fan-out lines (FIPHs) are located in the first source / drain layer, and some first fan-out lines (FIPHs) are located in the second source / drain layer. For example, the first fan-out lines (FIPHs) connected to the first pixel driving circuit and the third pixel driving circuit are located in the second source / drain layer, and the first fan-out lines (FIPHs) connected to the second pixel driving circuit are located in the first source / drain layer. The second fan-out line (FIPV) is located in the third source / drain layer.

[0170] It should be understood that, in other exemplary embodiments, the first outgoing FIPHs may all be located in the first source-drain layer or all be located in the second source-drain layer.

[0171] like Figure 41 The diagram shown is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in another exemplary embodiment of the display panel of this disclosure. Figure 35 Compared to the display panel shown, the orthographic projection of the three second fan-out lines FIPV connected to the same pixel unit on the substrate is located between the orthographic projection of the second pixel driving circuit PG on the substrate and the orthographic projection of the third pixel driving circuit PB on the substrate.

[0172] like Figure 42 The diagram shown is a partial stack-up layout of the first source / drain layer, the second source / drain layer, and the third source / drain layer in another exemplary embodiment of the display panel of this disclosure. Figure 40 Compared to the display panel shown, the orthographic projection of the three second fan-out lines FIPV connected to the same pixel unit on the substrate is located between the orthographic projection of the second pixel driving circuit PG on the substrate and the orthographic projection of the third pixel driving circuit PB on the substrate.

[0173] like Figure 41 , Figure 42 As shown, in the same pixel driving circuit, the orthographic projection of the second conductive part 22 on the substrate is located between the orthographic projection of the first power line VDD on the substrate and the orthographic projection of the first reset signal line Re1 on the substrate. The orthographic projection of the three first fan-out lines FIPH connected to the same pixel unit on the substrate is located between the orthographic projection of the first power line VDD connected to the current pixel driving circuit and the orthographic projection of the first reset signal line Re1 connected to the adjacent previous pixel driving circuit. In the same pixel unit, the orthographic projections of the data line Da connected to the second pixel driving circuit PG and the data line Da connected to the third pixel driving circuit PB on the substrate are located between the orthographic projections of the second conductive part 22 in the second pixel driving circuit and the second conductive part 22 in the third pixel driving circuit on the substrate. The orthographic projections of the three second fan-out lines FIPV connected to the same pixel unit on the substrate are located between the orthographic projections of the data line Da connected to the second pixel driving circuit and the data line Da connected to the third pixel driving circuit on the substrate.

[0174] like Figure 43 The diagram shown is a partial stack-up layout of the first source / drain layer and the second source / drain layer in another exemplary embodiment of the display panel of this disclosure. This display panel will... Figure 5 The fan-out configuration shown is applied to a two-layer source-drain layer architecture. (And...) Figure 35 Compared to the display panel shown, Figure 43 The display panel shown does not have a third source / drain layer; correspondingly, the data line Da and the second fan-out line FIPV are both located on the second source / drain layer. Figure 43 The other structures of the display panel shown can be related to Figure 35 The display panel shown is the same.

[0175] like Figure 44 The diagram shown is a partial stack-up layout of the first source / drain layer and the second source / drain layer in another exemplary embodiment of the display panel of this disclosure. Figure 41 Compared to the display panel shown, Figure 44 The display panel shown does not have a third source / drain layer; correspondingly, the data line Da and the second fan-out line FIPV are both located on the second source / drain layer. Figure 44 The other structures of the display panel shown can be related to Figure 41 The display panel shown is the same.

[0176] like Figures 9-44 As shown, the orthographic projection of the first fan-out line PIFH on the substrate is located on the side where the orthographic projection of the first conductive part 11 on the substrate is in the second direction Y; the orthographic projection of the second fan-out line FIPV on the substrate is located on the side where the orthographic projection of the first conductive part 11 on the substrate is in the first direction X.

[0177] It should be noted that, as Figures 9-44 As shown, the chamfered black squares drawn on the side of the first source / drain layer facing away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the chamfered black rectangles drawn on the side of the second source / drain layer facing away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate; and the chamfered black rectangles drawn on the side of the third source / drain layer facing away from the substrate represent vias connecting the third source / drain layer to other layers facing the substrate. Vias at different locations can penetrate different insulating layers.

[0178] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0179] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0180] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0181] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a pixel driving circuit located in the display area. The pixel driving circuit includes a driving transistor and a first capacitor. The first terminal of the driving transistor is connected to a first power line, and the first capacitor is connected between the second terminal of the driving transistor and the gate of the driving transistor. The display panel also includes: Substrate; A first gate layer is located on one side of the substrate, and the first gate layer includes a first conductive portion, at least a portion of which is used to form a first electrode of the first capacitor. The second gate layer is located on the side of the first gate layer away from the substrate. The second gate layer includes a second conductive portion. The orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The second conductive portion is used to form the second electrode of the first capacitor and is connected to the gate of the driving transistor. The display panel also includes: A data line, at least partially located in the display area, the data line extending along a second direction by its orthogonal projection on the substrate, the data line being used to provide data signals to the pixel driving circuit; The first fan-out line is at least partially located in the display area. The orthographic projection of the first fan-out line on the substrate extends along a first direction, which intersects with the second direction. The first fan-out line connects to the data line. The orthographic projection of the first fan-out line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is in the second direction. The second fan-out line is at least partially located in the display area. The orthographic projection of the second fan-out line on the substrate extends along the second direction. The second fan-out line is connected to the data line through the first fan-out line. The orthographic projection of the second fan-out line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is in the first direction.

2. The display panel according to claim 1, wherein, The display panel includes a plurality of pixel units, the orthographic projections of the plurality of pixel units on the substrate are distributed in an array along the first direction and the second direction, the pixel unit includes a plurality of pixel driving circuits distributed along the first direction, and the orthographic projections of the plurality of pixel driving circuits in the display panel on the substrate are distributed in an array along the first direction and the second direction. Wherein, the first direction is the row direction, the second direction is the column direction, and the orthographic projection of the first fan-out line on the substrate is located between the orthographic projections of two adjacent rows of pixel units on the substrate.

3. The display panel according to claim 2, wherein, The orthographic projection of multiple first fan-out lines connected to the same column of pixel units on the substrate is located between the orthographic projections of two adjacent rows of pixel units on the substrate. Alternatively, the orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate are respectively located between the orthographic projections of two adjacent rows of pixel units in different groups on the substrate.

4. The display panel according to any one of claims 2-3, wherein, The pixel driving circuit includes a driving transistor, a fifth transistor, and a seventh transistor. The first terminal of the fifth transistor is connected to a first power supply line, and the second terminal is connected to the first terminal of the driving transistor. The first terminal of the seventh transistor is connected to a second initial signal line, the second terminal is connected to a light-emitting unit, and the gate is connected to a first reset signal line. Wherein, the orthographic projections of the first power line and the first reset signal line on the substrate extend along the first direction. In the same pixel driving circuit, the orthographic projection of the second conductive part on the substrate is located between the orthographic projections of the first power line and the first reset signal line on the substrate, and the orthographic projection of the first fan-out line on the substrate is located between the orthographic projection of the first power line on the substrate in the current row pixel driving circuit and the orthographic projection of the first reset signal line on the substrate in the adjacent previous row pixel driving circuit.

5. The display panel according to claim 1, wherein, The display panel includes a plurality of pixel units, the orthographic projections of the plurality of pixel units on the substrate are distributed in an array along the first direction and the second direction, the pixel unit includes a plurality of pixel driving circuits distributed along the first direction, and the orthographic projections of the plurality of pixel driving circuits in the display panel on the substrate are distributed in an array along the first direction and the second direction. Wherein, the first direction is the row direction, the second direction is the column direction, and the orthographic projection of the second fan-out line on the substrate is located between the orthographic projections of two adjacent column pixel units on the substrate.

6. The display panel according to claim 5, wherein, The orthographic projection of multiple second fan-out lines connected to the same column of pixel units on the substrate is located between the orthographic projections of two adjacent columns of pixel units on the substrate. Alternatively, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are respectively located between the orthographic projections of two adjacent columns of pixel units in different groups on the substrate.

7. The display panel according to claim 6, wherein, The pixel driving circuit includes a seventh transistor, the first terminal of which is connected to a second initial signal line and the second terminal of which is connected to a light-emitting unit. Each column of pixel units is provided with a second initial connection line. The orthographic projection of the second initial signal line on the substrate extends along the first direction. The orthographic projection of the second initial connection line on the substrate extends along the second direction. The second initial connection line and at least a portion of the second initial signal line intersecting with it are connected by vias. The pixel unit includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are sequentially distributed along the first direction. The first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are used to drive light-emitting units of different colors. The orthographic projection of the second conductive part of the third pixel driving circuit in this pixel unit on the substrate is at least partially located between the orthographic projection of the second initial connection line corresponding to this pixel unit on the substrate and the orthographic projection of the data line connected to the third pixel driving circuit in this pixel unit on the substrate. The orthographic projection of the second fan-out line on the substrate is located between the orthographic projection of the second initial connection line corresponding to this pixel unit on the substrate and the orthographic projection of the data line connected to the first pixel driving circuit in the adjacent pixel unit on the substrate.

8. The display panel according to claim 1, wherein, The display panel includes a plurality of pixel units, the orthographic projections of the plurality of pixel units on the substrate are distributed in an array along the first direction and the second direction, the pixel unit includes a plurality of pixel driving circuits distributed along the first direction, and the orthographic projections of the plurality of pixel driving circuits in the display panel on the substrate are distributed in an array along the first direction and the second direction. Wherein, the first direction is the row direction, the second direction is the column direction, and the orthographic projection of the second fan-out line on the substrate is located between the orthographic projections of two adjacent column pixel driving circuits in the same column pixel unit on the substrate.

9. The display panel according to claim 8, wherein, The orthographic projection of multiple second fan-out lines connected to the same column of pixel units on the substrate is located between the orthographic projections of two adjacent columns of pixel driving circuits in the same column of pixel units on the substrate. Alternatively, the orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are respectively located between the orthographic projections of two adjacent pixel driving circuits in different columns of pixel units on the substrate.

10. The display panel according to any one of claims 8-9, wherein, The pixel unit includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are sequentially distributed along the first direction. In the same pixel unit, the orthographic projection of the data line connected to the second pixel driving circuit on the substrate and the orthographic projection of the data line connected to the third pixel driving circuit on the substrate are located between the orthographic projection of the second conductive part in the second pixel driving circuit on the substrate and the orthographic projection of the second conductive part in the third pixel driving circuit on the substrate. The orthographic projection of the second fan-out line on the substrate is located between the orthographic projections of the second pixel driving circuit and the third pixel driving circuit on the substrate in the same column of pixel units; The orthographic projection of the second fan-out line on the substrate is located between the orthographic projection of the data line connected to the second pixel driving circuit in the same column of pixel units on the substrate and the orthographic projection of the data line connected to the third pixel driving circuit on the substrate.

11. The display panel according to claim 3, wherein, The orthographic projections of multiple first fan-out lines connected to the same column of pixel units on the substrate are distributed at intervals in the second direction, and among the multiple first fan-out lines connected to the same column of pixel units, two adjacent first fan-out lines in the second direction are located in different conductive layers.

12. The display panel according to claim 6 or 9, wherein, The orthographic projections of multiple second fan-out lines connected to the same column of pixel units on the substrate are distributed at intervals in the first direction, and among the multiple second fan-out lines connected to the same column of pixel units, adjacent second fan-out lines in the first direction are located in different conductive layers.

13. The display panel according to claim 1, wherein, The pixel driving circuit includes multiple transistors, and the display panel further includes: The first source / drain layer is located on the side of the second gate layer away from the substrate, and a portion of the structure in the first source / drain layer bridges different transistors. The second source / drain layer is located on the side of the first source / drain layer that is away from the substrate. The first fan-out line is located in the first source-drain layer, and the second fan-out line and data line are located in the second source-drain layer.

14. The display panel according to claim 1, wherein, The pixel driving circuit includes multiple transistors, and the display panel further includes: The first source / drain layer is located on the side of the second gate layer away from the substrate, and a portion of the structure in the first source / drain layer bridges different transistors. The second source / drain layer is located on the side of the first source / drain layer that is away from the substrate. The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the data line is located in the third source / drain layer; Wherein, at least a portion of the first fan-out lines are located in the first source / drain layer and / or at least a portion of the first fan-out lines are located in the second source / drain layer.

15. The display panel according to claim 1, wherein, The pixel driving circuit includes multiple transistors, and the display panel further includes: The first source / drain layer is located on the side of the second gate layer away from the substrate, and a portion of the structure in the first source / drain layer bridges different transistors. The second source / drain layer is located on the side of the first source / drain layer that is away from the substrate. The third source / drain layer is located on the side of the second source / drain layer away from the substrate, and the data line is located in the third source / drain layer; Wherein, at least a portion of the second fan-out lines are located in the second source / drain layer and / or at least a portion of the second fan-out lines are located in the third source / drain layer.

16. The display panel according to claim 1, wherein, The display panel includes a plurality of pixel units, and the orthographic projections of the plurality of pixel units on the substrate are distributed in an array along the first direction and the second direction. The pixel unit includes a plurality of pixel driving circuits distributed along the first direction. The pixel unit includes a first pixel driving circuit, a second pixel driving circuit, and a third pixel driving circuit that are sequentially distributed in the first direction. The first pixel driving circuit and the second pixel driving circuit are arranged at least partially mirror-symmetrically in their orthogonal projections on the substrate, and the second pixel driving circuit and the third pixel driving circuit are arranged at least partially mirror-symmetrically in their orthogonal projections on the substrate.

17. The display panel according to claim 16, wherein, The pixel driving circuit includes one or more switching transistors. In the same pixel unit, the same type of switching transistors in the second pixel driving circuit and the third pixel driving circuit share the same conductive portion as the gate.

18. The display panel according to claim 1, wherein, The pixel driving circuit also includes a second capacitor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; The first electrode of the second capacitor is connected to the first electrode of the first capacitor, and the second electrode of the second capacitor is connected to the second electrode of the driving transistor; The first terminal of the first transistor is connected to the first initial signal line, the second terminal is connected to the first electrode of the first capacitor, and the gate is connected to the third reset signal line. The first terminal of the second transistor is connected to the first initial signal line, the second terminal is connected to the gate of the driving transistor, and the gate is connected to the second reset signal line; The first terminal of the fourth transistor is connected to the data line, the second terminal is connected to the gate of the driving transistor, and the gate is connected to the gate line. The first terminal of the fifth transistor is connected to the first power supply line, the second terminal is connected to the first terminal of the driving transistor, and the gate is connected to the first enable signal line. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the second enable signal line. The first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light-emitting unit, and the gate is connected to the first reset signal line. The first gate layer further includes a third conductive portion, which is connected to the first conductive portion in the same layer. At least a portion of the third conductive portion is used to form a first electrode of the second capacitor. The second gate layer further includes a fourth conductive portion, the orthographic projection of the fourth conductive portion on the substrate and the orthographic projection of the third conductive portion on the substrate overlap at least partially. The fourth conductive portion is used to form a second electrode of the second capacitor. The orthographic projections of the second conductive portion on the substrate and the orthographic projections of the fourth conductive portion on the substrate are distributed along the column direction. The display panel also includes: An active layer is located on the side of the second gate layer away from the substrate. The active layer includes a first main active portion and a second main active portion. The orthographic projection of the first main active portion on the substrate and the orthographic projection of the second main active portion on the substrate extend along a second direction and are spaced apart in a first direction. The first main active portion includes a first active portion, a second active portion, and a fourth active portion that are sequentially spaced apart along a second direction. The first active portion is used to form the channel region of the first transistor, the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor. The second main active portion includes a sixth active portion, a third active portion, and a fifth active portion that are sequentially spaced along a second direction. The sixth active portion is used to form the channel region of a sixth transistor, the third active portion is used to form the channel region of a driving transistor, and the fifth active portion is used to form the channel region of a fifth transistor. The orthographic projection of the fourth conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate.

19. The display panel according to claim 1, wherein, The display panel also includes: The repair line extends along the first direction when its orthogonal projection is on the substrate. The sixth bridging portion connects to the light-emitting unit, and the orthographic projections of the plurality of sixth bridging portions distributed in the first direction on the substrate overlap with the orthographic projections of the repair line on the substrate.

20. A display device, wherein, The display device includes the display panel as described in any one of claims 1-19.

Images