Display device

Abstract

The utility model relates to a display device. A display device of the present disclosure includes: a first pixel including a first light emitting area; a second pixel including a second light emitting region spaced apart from the first light emitting region in the second direction; and a bank defining a non-emission area between the first emission area and the second emission area, in which each of the first pixel and the second pixel includes: at least one dummy electrode spaced apart in a first direction intersecting a second direction and extending in the second direction; a light emitting element disposed between the at least one dummy electrode within the light emitting region; a first pixel electrode electrically connected to the first driving power supply and a first end of the light emitting element; and a second pixel electrode electrically connected to the second driving power supply and the second end of the light emitting element.

Description

Technical Field

[0001] This disclosure relates to display devices. Background Technology

[0002] In recent years, with the increasing interest in information display, research and development of display devices has been ongoing. Utility Model Content

[0003] Technical issues

[0004] The purpose of this disclosure is to provide a display device capable of improving luminous efficiency by repairing luminous defects in the light-emitting element (or pixel) caused by defects in the pixel circuit connected to the light-emitting element, and a method for manufacturing the display device.

[0005] The purpose of this disclosure is not limited to the above-described purposes, and other technical purposes not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Technical solution

[0007] A display device according to embodiments of the present disclosure may include: a first pixel including a first emitting region; a second pixel including a second emitting region spaced apart from the first emitting region in a second direction; and a dam defining a non-emitting region between the first emitting region and the second emitting region. Each of the first pixel and the second pixel may include: at least one dummy electrode spaced apart from each other in a first direction intersecting the second direction and extending in the second direction; a light-emitting element disposed in the emitting region between the at least one dummy electrode; a first pixel electrode electrically connected to a first driving power supply and a first end of the light-emitting element; and a second pixel electrode electrically connected to a second driving power supply and a second end of the light-emitting element. The first pixel electrode of the first pixel may extend from the first emitting region to the non-emitting region, and the first pixel electrode of the first pixel may be electrically connected to one of the at least one dummy electrode of the first pixel. The first pixel electrode of the second pixel may be electrically connected to the first driving power supply, and the first pixel electrode of the second pixel may be electrically connected to the dummy electrode.

[0008] According to the implementation method, the first pixel electrode of the first pixel can be electrically connected to the first driving power supply through the first pixel electrode of the second pixel and the dummy electrode.

[0009] According to an embodiment, at least one dummy electrode of the second pixel may be spaced apart from at least one dummy electrode of the first pixel in a second direction in a non-emission region, and at least one dummy electrode of the second pixel may not be electrically connected to at least one dummy electrode of the first pixel.

[0010] According to the implementation, the first pixel electrode of the second pixel can extend from the second emitting region to the non-emitting region, and the first pixel electrode of the second pixel can be electrically connected to the dummy electrode through the second contact hole.

[0011] According to an embodiment, at least one dummy electrode of the first pixel may further include: a first dummy electrode that overlaps with a first pixel electrode of the first pixel in a planar view; and a third dummy electrode that is spaced apart from the first dummy electrode in a first direction and overlaps with a second pixel electrode of the first pixel in a planar view.

[0012] According to the implementation method, the dummy electrode can be disposed between the first dummy electrode and the third dummy electrode in a plan view.

[0013] According to the implementation method, the dummy electrode can be further apart from the first dummy electrode in a plan view than the third dummy electrode.

[0014] According to an embodiment, the first pixel electrode of the first pixel may include: a first partial electrode that overlaps with a first dummy electrode in a planar view; and a second partial electrode that protrudes from the first partial electrode in a first direction and overlaps with at least a portion of the dummy electrode in a planar view. The second partial electrode may be electrically connected to the dummy electrode through a first contact hole.

[0015] According to an embodiment, the display device may further include an isolation electrode, spaced apart from a first pixel electrode of the first pixel in a second direction in a non-emitting region. The isolation electrode may be electrically connected to the first dummy electrode via a third contact hole.

[0016] A display device according to embodiments of the present disclosure may include: a first pixel including a first emitting region; a second pixel including a second emitting region spaced apart from the first emitting region in a second direction; and a dam defining a non-emitting region between the first emitting region and the second emitting region. Each of the first pixel and the second pixel may include: at least one dummy electrode spaced apart from each other in a first direction intersecting the second direction and extending in the second direction; a light-emitting element disposed in the emitting region between the at least one dummy electrode; a first pixel electrode electrically connected to a first driving power supply and a first end of the light-emitting element; and a second pixel electrode electrically connected to a second driving power supply and a second end of the light-emitting element. The first pixel electrode of the first pixel may extend from the first emitting region to the non-emitting region, and the first pixel electrode of the first pixel may be electrically connected to one of the at least one dummy electrode of the second pixel. The first pixel electrode of the second pixel may be electrically connected to the first driving power supply, and the first pixel electrode of the second pixel may be electrically connected to that one dummy electrode.

[0017] According to an embodiment, at least one dummy electrode of the second pixel may be spaced apart from at least one dummy electrode of the first pixel in a second direction in a non-emission region, and at least one dummy electrode of the second pixel may not be electrically connected to at least one dummy electrode of the first pixel.

[0018] According to an embodiment, at least one dummy electrode of the second pixel may include a first dummy electrode, a second dummy electrode, a third dummy electrode and a fourth dummy electrode arranged sequentially in a first direction, and the dummy electrode may be the first dummy electrode.

[0019] According to an embodiment, at least one dummy electrode of the first pixel may include a first dummy electrode, a second dummy electrode, a third dummy electrode and a fourth dummy electrode arranged sequentially in a first direction, and the display device may further include an isolation electrode that overlaps with the first dummy electrode in a non-emission region in a plan view and is at least partially surrounded by the first pixel electrode of the first pixel.

[0020] According to an embodiment, the first pixel electrode of the first pixel may include: a first portion that overlaps with a first dummy electrode in a planar view; and a curved portion that extends from the first portion and overlaps with at least a portion of the dummy electrode in a planar view.

[0021] According to an embodiment, the curved portion may include: a second portion electrode that protrudes from the first portion in a second direction and overlaps with a second dummy electrode in a plan view; and a third portion electrode that overlaps with at least a portion of the dummy electrode in a plan view, the dummy electrode being one of at least one dummy electrodes of the second pixel.

[0022] According to the implementation method, the third electrode can be electrically connected to the dummy electrode through the first contact hole.

[0023] A method for manufacturing a display device according to embodiments of the present disclosure may include: forming a pixel circuit layer on a substrate; forming first alignment electrodes to fourth alignment electrodes spaced apart from each other in a first direction on the pixel circuit layer; forming a first emission region defining a first pixel, a second emission region of a second pixel spaced apart from the first emission region in a second direction intersecting the first direction, and a non-emission region between the first emission region and the second emission region on the first alignment electrodes to the fourth alignment electrodes; providing a light-emitting element to each of the first emission region and the second emission region; providing a first pixel electrode electrically connected to one end of the light-emitting element and a second pixel electrode electrically connected to the other end of the light-emitting element; and removing the first alignment electrode from the second alignment layer. A portion of each of the first to fourth alignment electrodes in the non-emission region is electrically separated into at least one dummy electrode overlapping the first emission region in a planar view and at least one dummy electrode overlapping the second emission region in a planar view; a first pixel and a second pixel are inspected for defects using a mother substrate inspection device; based on the inspection results, if the first pixel is in a defective state, the electrical connection between the first pixel electrode and the pixel circuit layer of the first pixel is separated; the first pixel electrode disposed in the non-emission region and one of the at least one dummy electrodes of the first pixel are electrically connected; and the one dummy electrode is electrically connected to the first pixel electrode of the second pixel.

[0024] According to an implementation, when separating the electrical connection between the first pixel electrode of the first pixel and the pixel circuit layer, the first pixel electrode can be separated into an isolation electrode electrically connected to the pixel circuit layer and a portion of the electrode spaced apart from the isolation electrode and extending from the first emission region to the non-emission region by radiating a laser to the first pixel electrode in the non-emission region to remove a portion of the first pixel electrode of the first pixel.

[0025] According to the embodiment, a portion of the protruding part of a partial electrode in a first direction is electrically connected to the dummy electrode through a first contact hole, and a portion of the first pixel electrode of the second pixel extending from the second emission region to the non-emission region is electrically connected to the dummy electrode through a second contact hole.

[0026] According to an embodiment, setting the first pixel electrode of the first pixel and the first pixel electrode of the second pixel includes: forming a portion of the partial electrode and a portion of the first pixel electrode of the second pixel by using at least one of conductive ink and chemical vapor deposition (CVD).

[0027] Beneficial effects

[0028] According to the implementation, a portion of the protruding part of a partial electrode in a first direction can be electrically connected to the dummy electrode through a first contact hole, and a portion of the first pixel electrode of the second pixel extending from the second emission region to the non-emission region can be electrically connected to the dummy electrode through a second contact hole.

[0029] According to an embodiment, setting the first pixel electrode of the first pixel and the first pixel electrode of the second pixel may include forming a portion of the partial electrode and a portion of the first pixel electrode of the second pixel by using at least one of conductive ink and chemical vapor deposition (CVD).

[0030] The effects of the embodiments are not limited to the above description, and various additional effects are included in the specification. Attached Figure Description

[0031] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0032] Figure 1 This is a schematic perspective view showing a light-emitting element according to an embodiment of the present disclosure.

[0033] Figure 2 It is shown Figure 1 A schematic cross-sectional view of an example of a light-emitting element.

[0034] Figure 3 This is a schematic plan view illustrating a display device according to an embodiment of the present disclosure.

[0035] Figure 4 This shows the situation where the pixel is in its normal state, including... Figure 3 A schematic diagram of the equivalent circuit of an example pixel in a display device.

[0036] Figure 5a It is shown schematically. Figure 4 A planar diagram of example pixels.

[0037] Figure 5b and Figure 5c It is shown schematically. Figure 4 Other examples of pixel planar diagrams.

[0038] Figure 6a It is schematically shown along Figure 5a An example sectional view of the section cut by line A-A'.

[0039] Figure 6b It is schematically shown along Figure 5aA cross-sectional view of an example section taken by line B-B'.

[0040] Figure 6c It is shown that it includes Figure 3 A cross-sectional view of the first to third pixels in a display device.

[0041] Figure 7a This illustrates the situation where a pixel is in a defective state, including... Figure 3 A schematic diagram of the equivalent circuit of an example pixel in a display device.

[0042] Figure 7b and Figure 7c This is shown for explanation Figure 7a A schematic diagram of the equivalent circuit of an example pixel in a defective state repair method.

[0043] Figure 8 and Figure 9 This is shown for explanation Figure 7a A schematic plan view of an example pixel in a defective state, illustrating a method for repairing pixels.

[0044] Figure 10 It is schematically shown along Figure 8 A cross-sectional view of an example section taken by line I-I'.

[0045] Figure 11a and Figure 11b It is schematically shown along Figure 9 A cross-sectional view of an example section taken by line II-II'.

[0046] Figure 12 and Figure 13 This is shown for explanation Figure 7a A schematic plan view of other examples of pixel repair methods in defective states. Detailed Implementation

[0047] Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements, and repeated descriptions of the same elements are omitted.

[0048] Figure 1 This is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 A schematic cross-sectional view of an example of a light-emitting element.

[0049] refer to Figure 1 and Figure 2The light-emitting element (LD) may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed or interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element (LD) may be implemented as a light-emitting stack (or stack pattern) in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are stacked sequentially on top of each other.

[0050] In an embodiment, the light-emitting element (LD) can be configured to extend in one direction. When the direction of extension of the LD is referred to as the longitudinal direction, the LD may include a first end EP1 and a second end EP2 in the longitudinal direction. One of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the first end EP1 of the LD. The other of the first semiconductor layer 11 and the second semiconductor layer 13 may be located at the second end EP2 of the LD.

[0051] In implementation methods, the light-emitting element (LD) can be configured in various shapes. For example, such as... Figure 1 As shown, the light-emitting element (LD) can have a rod-like shape, bar-like shape, or column-like shape that is long in the longitudinal direction (or has an aspect ratio greater than about 1). As another example, the light-emitting element (LD) can have a rod-like shape, bar-like shape, or column-like shape that is short in the longitudinal direction (or has an aspect ratio less than about 1). As yet another example, the light-emitting element (LD) can have a rod-like shape, bar-like shape, or column-like shape with an aspect ratio of about 1.

[0052] As an example, a light-emitting element LD may include a light-emitting diode (LED) configured to be ultra-small in size to have a diameter D and / or length L in the nanometer (or nanometer) or micrometer (or micrometer) range.

[0053] In embodiments where the light-emitting element (LD) is long in the longitudinal direction (e.g., having an aspect ratio greater than about 1), the diameter D of the LD can be from about 0.5 μm to about 6 μm, and the length L of the LD can be from about 1 μm to about 10 μm. However, the diameter D and length L of the LD are not limited thereto. The dimensions of the LD can be varied to meet the requirements (or design conditions) of the lighting device or self-emissive display device to which the LD is applied.

[0054] In an embodiment, the first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. In the longitudinal direction of the light-emitting element LD, the first semiconductor layer 11 may include an upper surface that contacts the active layer 12 and a lower surface exposed to the outside. The lower surface of the first semiconductor layer 11 may be one end (or the lower end) of the light-emitting element LD.

[0055] In an embodiment, the active layer 12 may be disposed on the first semiconductor layer 11 and may be formed as a single quantum well structure or a multiple quantum well structure. As an example, when the active layer 12 is formed as a multiple quantum well structure, the active layer 12 may have a structure in which a barrier layer, a strain enhancement layer, and a well layer are periodically and repeatedly stacked as a part. Since the strain enhancement layer has a smaller lattice constant than the barrier layer, the strain applied to the well layer, for example, compressive strain, can be further enhanced. However, the structure of the active layer 12 is not limited to the embodiments described above.

[0056] In one embodiment, the active layer 12 can emit light with a wavelength of about 400 nm to about 900 nm, and a dual heterostructure can be used. The active layer 12 may include a first surface that contacts the first semiconductor layer 11 and a second surface that contacts the second semiconductor layer 13.

[0057] In this implementation, the color (or emitted color) of the light-emitting element LD can be determined based on the wavelength of the light emitted from the active layer 12. The color of the light-emitting element LD can determine the color of the corresponding pixel. For example, the light-emitting element LD can emit red, green, or blue light.

[0058] In this embodiment, when an electric field of voltage (e.g., a predetermined or optional voltage) or higher is applied to the end of the light-emitting element LD, the light-emitting element LD can emit light while electron-hole pairs recombine in the active layer 12. By controlling the light emission of the light-emitting element LD using this principle, the light-emitting element LD can be used as a light source (or light source) for various light-emitting devices, including pixels, in a display device.

[0059] In an implementation, the second semiconductor layer 13 may be disposed on the second surface of the active layer 12, and may include a semiconductor layer of a different type than the first semiconductor layer 11. As an example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0060] In one embodiment, in the longitudinal direction of the light-emitting element LD, the second semiconductor layer 13 may include a lower surface that contacts the second surface of the active layer 12 and an upper surface exposed to the outside. The upper surface of the second semiconductor layer 13 may be the other end (or the upper end) of the light-emitting element LD.

[0061] In this embodiment, the first semiconductor layer 11 and the second semiconductor layer 13 may have different thicknesses in the longitudinal direction of the light-emitting element LD. As an example, the first semiconductor layer 11 may have a relatively larger thickness in the longitudinal direction of the light-emitting element LD than the second semiconductor layer 13. Therefore, the active layer 12 of the light-emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11.

[0062] Figure 1 and Figure 2 An embodiment in which each of the first semiconductor layer 11 and the second semiconductor layer 13 is configured as a single layer is shown, but the present disclosure is not limited thereto. In the example, depending on the material of the active layer 12, each of the first semiconductor layer 11 and the second semiconductor layer 13 may further include one or more layers, such as a cladding layer and / or a tensile strain barrier reduction (TSBR) layer. The TSBR layer may be a strain relief layer disposed between semiconductor layers with different lattice structures and acting as a buffer to reduce lattice constant differences. The TSBR layer may consist of a p-type semiconductor layer such as p-GaInP, p-AlInP, p-AlGaInP, etc., but the present disclosure is not limited thereto.

[0063] In one embodiment, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 described above, the light-emitting element LD may further include a contact electrode (hereinafter referred to as the "first contact electrode") disposed on the second semiconductor layer 13. According to another embodiment, it may further include another contact electrode (hereinafter referred to as the "second contact electrode") disposed on an end of the first semiconductor layer 11.

[0064] In some embodiments, each of the first and second contact electrodes may be an ohmic contact electrode, but this disclosure is not limited thereto. According to some embodiments, the first and second contact electrodes may be Schottky contact electrodes. The first and second contact electrodes may comprise conductive materials.

[0065] In an embodiment, the light-emitting element LD may further include an insulating film 14 (or an insulating thin film). However, according to an embodiment, the insulating film 14 may be omitted or may be configured to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0066] In this embodiment, the insulating film 14 can prevent electrical short circuits that may occur when the active layer 12 comes into contact with conductive materials other than the first semiconductor layer 11 and the second semiconductor layer 13. The insulating film 14 can minimize surface defects of the light-emitting element LD, thereby improving the lifetime and luminous efficiency of the light-emitting element LD. Whether or not the insulating film 14 is provided is not limited, as long as it can prevent short circuits between the active layer 12 and external conductive materials.

[0067] In one embodiment, the insulating film 14 may surround at least a portion of the outer peripheral surface of the light-emitting stack including the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0068] In the above embodiments, the form in which the insulating film 14 completely surrounds the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 has been described, but this disclosure is limited thereto.

[0069] In some embodiments, the insulating film 14 may comprise a transparent insulating material. For example, the insulating film 14 may comprise a material selected from silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum oxide (AlO) x Titanium oxide (TiO) x ), hafnium oxide (HfO) x ), Strontium titanium oxide (SrTiO) x ), cobalt oxide (Co) x O y ), magnesium oxide (MgO), zinc oxide (ZnO) x ), Ruthenium oxide (RuO) x Nickel oxide (NiO) and tungsten oxide (WO) x ), tantalum oxide (TaO) x ), gadolinium oxide (GdO) x Zirconium oxide (ZrO) x Gallium oxide (GaO) x ), Vanadium oxide (V x O y ZnO:Al, ZnO:B, In x O y H, niobium oxide (Nb) x O y ), magnesium fluoride (MgF) x ), aluminum fluoride (AlF) x ), aluminum cone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlN) x It is at least one insulating material from the group consisting of gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), and vanadium nitride (VN). However, this disclosure is not limited thereto, and various materials with insulating properties can be used as the material of the insulating film 14.

[0070] In an embodiment, the insulating film 14 may be configured as a single layer or as a multilayer comprising at least two layers.

[0071] The aforementioned light-emitting elements (LDs) can be used as light sources (or light sources) in various display devices. LDs can be manufactured using surface treatment processes. For example, when a light-emitting element (LD) is mixed with a liquid solution (or solvent) and provided to each pixel area (e.g., the emitting area of ​​each pixel or the emitting area of ​​each sub-pixel), each of the LDs can be surface-treated so that the LDs can be uniformly distributed without unevenly agglomerating in the solution.

[0072] Light-emitting components (or light-emitting devices) including the aforementioned light-emitting elements (LDs) can be used in various types of electronic devices (including display devices) that require a light source. For example, when the light-emitting element (LD) is disposed in the pixel area of ​​each pixel on a display panel, the LD can serve as a light source for each pixel. However, the application of LDs is not limited to the examples described above. For instance, LDs can also be used in other types of electronic devices that require a light source (such as lighting devices).

[0073] However, this is merely an example, and the light-emitting element (LD) applied to a display device according to embodiments of this disclosure is not limited thereto. For example, the light-emitting element (LD) may be a flip-chip micro-light-emitting diode or an organic light-emitting element including an organic light-emitting layer.

[0074] Figure 3 This is a schematic plan view of a display device according to an embodiment of the present disclosure.

[0075] refer to Figure 1 , Figure 2 and Figure 3 The display device DD may include pixels PXL1, PXL2, PXL3, and PXL4 disposed on a substrate SUB and each including at least one light-emitting element LD. Pixels PXL1, PXL2, PXL3, and PXL4 may include light-emitting elements (e.g., Figure 1 The light-emitting element (LD) of the display device (DD) may also include a driver and wiring portions electrically connected to the driver.

[0076] The substrate SUB may include the display area DA and the non-display area NDA.

[0077] The display area DA can be the area where an image is displayed, and pixels PXL1, PXL2, PXL3, and PXL4 may or may not emit light. The non-display area NDA can be a portion of the area where drivers for driving pixels PXL1, PXL2, PXL3, and PXL4 are configured, as well as a portion of the wiring portion for electrically connecting pixels PXL1, PXL2, PXL3, and PXL4 to the drivers.

[0078] The non-display area NDA can be located near the display area DA. The non-display area NDA can be located on at least one side of the display area DA. For example, the non-display area NDA can surround the periphery (or edge) of the display area DA.

[0079] The wiring section may include signal lines. These signal lines may be electrically connected to pixels PXL1, PXL2, PXL3, and PXL4 to provide signals. The signal lines may include fan-out lines electrically connected to scan lines, data lines, transmit control lines, etc.

[0080] In an implementation, pixels PXL1, PXL2, PXL3, and PXL4 may include a first pixel PXL1, a second pixel PXL2, a third pixel PXL3, and a fourth pixel PXL4. In an example, the first pixel PXL1 to the third pixel PXL3 may be pixels that emit light of the same color. For example, the first pixel PXL1 to the third pixel PXL3 may be one of a red pixel, a green pixel, and a blue pixel. In an example, the fourth pixel PXL4 may emit light of a different color than the first pixel PXL1. For example, if the first pixel PXL1 is a red pixel emitting red light, the fourth pixel PXL4 may be a green pixel emitting green light or a blue pixel emitting blue light. However, this disclosure is not limited to this, and the fourth pixel PXL4 and the first pixel PXL1 may emit light of the same color.

[0081] In this embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 can be arranged sequentially on the second direction DR2. The fourth pixel PXL4 can be configured to be spaced apart from the first pixel PXL1 on the first direction DR1.

[0082] The light-emitting element (LD) can have a size as small as nanometers (or nanometers) or micrometers (or micrometers), and can be electrically connected in parallel with other light-emitting elements (LDs) arranged adjacent to it, but this disclosure is not limited thereto. The light-emitting elements (LDs) can constitute (or form) a light source for each of pixels PXL1, PXL2, PXL3, and PXL4.

[0083] Figure 4 This shows the situation where the pixel is in its normal state, including... Figure 3 A schematic diagram of the equivalent circuit of an example pixel in a display device.

[0084] Figure 4 The pixel PXL shown can be Figure 3 Any one of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0085] refer to Figure 1 , Figure 2 , Figure 3 and Figure 4 The pixel PXL may include the pixel circuitry PXC and the transmitter unit EMU.

[0086] The pixel PXL may include a pixel circuit PXC that controls the drive current based on a data signal and an emitting part EMU that emits light with a brightness corresponding to the drive current.

[0087] The transmitting section EMU can be electrically connected to the first driving power supply VDD and the second driving power supply VSS through the corresponding pixel circuit PXC, and can be turned on.

[0088] The state in which the transmitting EMU is electrically connected to the first driving power supply VDD and the second driving power supply VSS through the corresponding pixel circuit PXC and is conducting can be referred to as the state of pixel PXL in normal condition. The state in which the transmitting EMU is not conducting due to a defect in the corresponding pixel circuit PXC and is not electrically connected to the first driving power supply VDD can be referred to as the state of pixel PXL in defective condition.

[0089] In one embodiment, the emitting section EMU may include light-emitting elements (LDs) connected in parallel between a first power line PL1 and a second power line PL2. The first power line PL1 may be electrically connected to a first driving power supply VDD, and the voltage of the first driving power supply VDD may be applied to the first power line PL1. The second power line PL2 may be electrically connected to a second driving power supply VSS, and the voltage of the second driving power supply VSS may be applied to the second power line PL2. For example, the emitting section EMU may include light-emitting elements (LDs) connected in parallel with each other in the same direction between a first pixel electrode ELT1 and a fifth pixel electrode ELT5.

[0090] The first driving power supply VDD and the second driving power supply VSS can have different potentials. As an example, the first driving power supply VDD can be set to a high potential power supply, and the second driving power supply VSS can be set to a low potential power supply. During the emission cycle of pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS can be set to be higher than or equal to the threshold voltage of the light-emitting element LD.

[0091] The first pixel electrode ELT1 can be electrically connected to the first driving power supply VDD via the pixel circuit PXC and the first power line PL1, and the fifth pixel electrode ELT5 can be electrically connected to the second driving power supply VSS via the second power line PL2. In this embodiment, the first pixel electrode ELT1 can be the anode, and the fifth pixel electrode ELT5 can be the cathode.

[0092] In the following text, when one or more of the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the fourth light-emitting element LD4 are mentioned arbitrarily or when two or more types of light-emitting elements are mentioned in full, they will be referred to as "light-emitting element LD" or "multiple light-emitting elements LD".

[0093] In an embodiment, each of the light-emitting elements (LDs) may include a first terminal electrically connected to a first driving power supply VDD via a first pixel electrode ELT1 and a second terminal electrically connected to a second driving power supply VSS via a fifth pixel electrode ELT5.

[0094] As described above, each of the light-emitting elements LDs that are electrically connected in parallel in the same direction (e.g., the forward direction) between the first pixel electrode ELT1 and the fifth pixel electrode ELT5, which are supplied with different power supply voltages, can constitute an effective light source.

[0095] In this implementation, the light-emitting elements (LDs) of the transmitting section EMU can emit light with a brightness corresponding to the drive current provided by the corresponding pixel circuit (PXC). For example, during each frame period, the pixel circuit (PXC) can provide the transmitting section EMU with a drive current corresponding to the grayscale value of the corresponding frame data. The drive current provided to the transmitting section EMU can be shunted and flow to each of the light-emitting elements (LDs). Therefore, when each light-emitting element (LD) emits light with a brightness corresponding to the current flowing through it, the transmitting section EMU can emit light with a brightness corresponding to the drive current.

[0096] In the above embodiments, it has been described that the ends of the light-emitting elements LD are electrically connected in the same direction between the first driving power supply VDD and the second driving power supply VSS, but this disclosure is not limited thereto. According to the embodiments, in addition to the light-emitting elements LD constituting an effective light source, the emitting part EMU may also include at least one ineffective light source, such as a reverse light-emitting element LDr.

[0097] The reverse light-emitting element LDr can be electrically connected in parallel with the light-emitting element LD constituting the effective light source between the first pixel electrode ELT1 and the fifth pixel electrode ELT5, but it can also be electrically connected between the first pixel electrode ELT1 and the fifth pixel electrode ELT5 in the opposite direction to the light-emitting element LD. Even when a driving voltage (e.g., a predetermined or optional driving voltage) is applied between the first pixel electrode ELT1 and the fifth pixel electrode ELT5, the reverse light-emitting element LDr can remain in an inactive state. Therefore, current can substantially not flow through the reverse light-emitting element LDr.

[0098] The pixel circuit PXC can be electrically connected to the scan line Si and the data line Dj. The pixel circuit PXC can also be electrically connected to the control line CLI and the sensing line SENj. As an example, if pixel PXL is located in the i-th row and j-th column of the display area DA, the pixel circuit PXC of pixel PXL can be electrically connected to the i-th scan line Si, the j-th data line Dj, the i-th control line CLI, and the j-th sensing line SENj.

[0099] In an implementation, the pixel circuit PXC may include a first transistor T1 to a third transistor T3 and a storage capacitor Cst.

[0100] The first transistor T1 can be a drive transistor for controlling the drive current applied to the transmitting section EMU, and can be electrically connected between the first drive power supply VDD and the transmitting section EMU. The first terminal of the first transistor T1 can be electrically connected to the first drive power supply VDD via the first power line PL1, the second terminal of the first transistor T1 can be electrically connected to the second node N2, and the gate electrode of the first transistor T1 can be electrically connected to the first node N1. The first transistor T1 can control the amount of drive current applied from the first drive power supply VDD to the transmitting section EMU through the second node N2 based on the voltage applied to the first node N1. The first terminal of the first transistor T1 can be the drain electrode, and the second terminal of the first transistor T1 can be the source electrode, but this disclosure is not limited thereto. According to an embodiment, the first terminal can be the source electrode, and the second terminal can be the drain electrode.

[0101] The second transistor T2 can be a switching transistor that selects (or activates) pixel PXL in response to a scan signal, and can be electrically connected between data line Dj and the first node N1. The first terminal of the second transistor T2 can be electrically connected to data line Dj, the second terminal of the second transistor T2 can be electrically connected to the first node N1, and the gate electrode of the second transistor T2 can be electrically connected to scan line Si. If the first terminal is a drain electrode, the second terminal can be a source electrode, but this disclosure is not limited thereto.

[0102] When a scan signal with a gate on-state voltage (e.g., a high-level voltage) is provided from the scan line Si, the second transistor T2 can be turned on to electrically connect the data line Dj and the first node N1. The first node N1 can be the point where the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are electrically connected to each other, and the second transistor T2 can transmit the data signal to the gate electrode of the first transistor T1.

[0103] In the implementation, the second terminal of the third transistor T3 can be electrically connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be electrically connected to the sensing line SENj, and the gate electrode of the third transistor T3 can be electrically connected to the control line CLI.

[0104] In this implementation, the first terminal of the third transistor T3 can be electrically connected to an initialization power supply. The third transistor T3 can be an initialization transistor capable of initializing the second node N2, and can be turned on when a sensing control signal is provided from the control line CLI to transmit the voltage of the initialization power supply applied to the sensing line SENj to the second node N2. Therefore, the second storage electrode UE of the storage capacitor Cst, which is electrically connected to the second node N2, can be initialized.

[0105] In another embodiment, the third transistor T3 can obtain a sensing signal through the sensing line SENj by electrically connecting the first transistor T1 to the sensing line SENj, and can use the sensing signal to detect characteristics of pixel PXL, including the threshold voltage of the first transistor T1. Information about the characteristics of pixel PXL can be used to transform image data so that characteristic deviations between pixels PXL can be compensated.

[0106] In this embodiment, the first storage electrode LE of the storage capacitor Cst may be electrically connected to the first node N1, and the second storage electrode UE of the storage capacitor Cst may be electrically connected to the second node N2. The storage capacitor Cst may be charged with a data voltage corresponding to the data signal provided to the first node N1 during a frame period. The storage capacitor Cst may store a voltage corresponding to the difference between the voltage of the gate electrode of the first transistor T1 and the voltage of the second node N2.

[0107] In an implementation, the emitting section EMU can be configured to include at least one series stage, wherein the at least one series stage includes light-emitting elements (LDs) electrically connected in parallel with each other. In an example, the emitting section EMU can have a hybrid series or parallel structure. For example, the emitting section EMU can have a 4-series-stage structure including four series stages. However, this disclosure is not limited thereto, and the emitting section EMU can have a 2-series-stage structure including two series stages or a 6-series-stage structure including six series stages.

[0108] In an implementation, each series stage may include a pair of electrodes (e.g., two electrodes) and at least one light-emitting element (LD) electrically connected between the pair of electrodes in the forward direction. The number of LDs constituting each series stage is not particularly limited. As an example, the number of LDs constituting each series stage may be the same or different, and the number of LDs is not particularly limited.

[0109] In an implementation, the transmitting section EMU may include a first cascade stage, a second cascade stage, a third cascade stage, and a fourth cascade stage.

[0110] In an embodiment, the first cascade stage may include a first pixel electrode ELT1, a second pixel electrode ELT2, and at least one first light-emitting element LD1 electrically connected between the first pixel electrode ELT1 and the second pixel electrode ELT2. Each first light-emitting element LD1 may be electrically connected between the first pixel electrode ELT1 and the second pixel electrode ELT2 in the forward direction. For example, a first terminal EP1 of the first light-emitting element LD1 may be electrically connected to the first pixel electrode ELT1, and a second terminal EP2 of the first light-emitting element LD1 may be electrically connected to the second pixel electrode ELT2.

[0111] In an embodiment, the second cascade stage may include a second pixel electrode ELT2, a third pixel electrode ELT3, and at least one second light-emitting element LD2 electrically connected between the second pixel electrode ELT2 and the third pixel electrode ELT3. Each second light-emitting element LD2 may be electrically connected between the second pixel electrode ELT2 and the third pixel electrode ELT3 in the forward direction. For example, the first end EP1 of the second light-emitting element LD2 may be electrically connected to the second pixel electrode ELT2, and the second end EP2 of the second light-emitting element LD2 may be electrically connected to the third pixel electrode ELT3.

[0112] In an embodiment, the third cascade stage may include a third pixel electrode ELT3, a fourth pixel electrode ELT4, and at least one third light-emitting element LD3 electrically connected between the third pixel electrode ELT3 and the fourth pixel electrode ELT4. Each third light-emitting element LD3 may be electrically connected between the third pixel electrode ELT3 and the fourth pixel electrode ELT4 in the forward direction. For example, the first terminal EP1 of the third light-emitting element LD3 may be electrically connected to the third pixel electrode ELT3, and the second terminal EP2 of the third light-emitting element LD3 may be electrically connected to the fourth pixel electrode ELT4.

[0113] In an embodiment, the fourth cascade stage may include a fourth pixel electrode ELT4, a fifth pixel electrode ELT5, and at least one fourth light-emitting element LD4 electrically connected between the fourth pixel electrode ELT4 and the fifth pixel electrode ELT5. Each fourth light-emitting element LD4 may be electrically connected between the fourth pixel electrode ELT4 and the fifth pixel electrode ELT5 in the forward direction. For example, a first terminal EP1 of the fourth light-emitting element LD4 may be electrically connected to the fourth pixel electrode ELT4, and a second terminal EP2 of the fourth light-emitting element LD4 may be electrically connected to the fifth pixel electrode ELT5.

[0114] In an implementation, the first pixel electrode ELT1 of the first cascade stage can be the anode electrode of each pixel PXL, and the fifth pixel electrode ELT5 of the fourth cascade stage can be the cathode electrode of each pixel PXL.

[0115] In this implementation, the remaining electrodes of the transmitting portion EMU (e.g., the second pixel electrode ELT2, the third pixel electrode ELT3, and the fourth pixel electrode ELT4) can constitute intermediate electrodes. For example, the second pixel electrode ELT2 can constitute the first intermediate electrode IET1, the third pixel electrode ELT3 can constitute the second intermediate electrode IET2, and the fourth pixel electrode ELT4 can constitute the third intermediate electrode IET3.

[0116] In an embodiment, at least one of the first to fourth series stages may include a reverse light-emitting element LDr electrically connected between two electrodes in the opposite direction to the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the fourth light-emitting element LD4.

[0117] In this implementation, the first pixel electrode ELT1 can be electrically connected to the pixel circuit PXC via the second node N2. The fifth pixel electrode ELT5 can be electrically connected to the second power line PL2 via the third node N3. In this example, the second node N2 can be the first point where the pixel circuit PXC and the transmitting section EMU are electrically connected to each other, and the third node N3 can be the second point where the second power line PL2 and the transmitting section EMU are electrically connected to each other.

[0118] In this embodiment, the first transistor T1, the second transistor T2, and the third transistor T3 can be oxide semiconductor transistors. The first transistor T1, the second transistor T2, and the third transistor T3 can each include an oxide semiconductor layer as an active layer (semiconductor layer or channel layer). For example, the first transistor T1, the second transistor T2, and the third transistor T3 can be n-type oxide semiconductor transistors. However, this disclosure is not limited thereto. For example, the first transistor T1, the second transistor T2, and the third transistor T3 can be implemented as p-type semiconductor transistors.

[0119] Oxide-semiconductor (OSB) transistors can be manufactured using low-temperature processes and can exhibit lower charge mobility than polycrystalline silicon (PCS) transistors. For example, OSB transistors possess excellent cutoff current characteristics. Therefore, when the first transistor T1, the second transistor T2, and the third transistor T3 are composed of OSB transistors, leakage current through these transistors can be minimized by using low-frequency and variable-frequency driving. This can improve display quality.

[0120] Figure 5a It is shown schematically. Figure 4 A planar diagram of example pixels.

[0121] Figure 5a This is a schematic plan view showing the first pixel PXL1, which is included as a pixel in the display device DD. For ease of description, Figures 5a to 5c A portion of the first pixel PXL1 and its adjacent second pixel PXL2 is shown. Figures 5a to 5c The diagram shows that each pixel PXL includes, for example... Figure 4 The embodiment shown depicts a light-emitting element LD arranged in four cascade stages, but the number of cascade stages for each pixel PXL can vary depending on the embodiment.

[0122] refer to Figure 3 , Figure 4 and Figure 5a The display device DD may include a BNK, first alignment electrodes ALE1 to fourth alignment electrodes ALE4, light-emitting elements LD1 to LD4, and pixel electrodes ELT1 to ELT5 to configure pixels PXL1 and PXL2.

[0123] In this implementation, the first pixel PXL1 and the second pixel PXL2 may have the same or similar structures. Since the second pixel PXL2 may be substantially similar to the first pixel PXL1, the first pixel PXL1 will be described.

[0124] In an implementation, the dam BNK can divide a first pixel PXL1 and a second pixel PXL2. Pixel PXL can include an emitting region and a non-emitting region NEA. The first pixel PXL1 can include a first emitting region EMA1, and the second pixel PXL2 can include a second emitting region EMA2. The non-emitting region NEA can be formed between the first emitting region EMA1 and the second emitting region EMA2. In an example, the first emitting region EMA1 and the second emitting region EMA2 can correspond to an opening defined by the dam BNK. The non-emitting region NEA can correspond to an opening region OPA formed in the dam BNK. The dam BNK can surround the emitting regions EMA1 and EMA2. In an example, the opening region OPA can be a region different from the opening corresponding to the first emitting region EMA1 and the second emitting region EMA2.

[0125] In an embodiment, the first alignment electrodes ALE1 to the fourth alignment electrodes ALE4 may be arranged sequentially, spaced apart from each other in a first direction DR1, and may extend in a second direction DR2. The first alignment electrodes ALE1 to the fourth alignment electrodes ALE4 may be electrodes for aligning light-emitting elements LD disposed in the first pixel PXL1 and the second pixel PXL2. The light-emitting element LD may move (or rotate) according to an electric field force (e.g., dielectric electrophoresis (DEP) force) and be aligned (or disposed) on the alignment electrodes. In the process of manufacturing pixel PXL, the first pixel PXL1 and the second pixel PXL2 may share the first alignment electrodes ALE1 to the fourth alignment electrodes ALE4.

[0126] In an embodiment, during the process of aligning the light-emitting element LD (hereinafter referred to as the alignment process), the first alignment electrode ALE1 to the fourth alignment electrode ALE4 may be supplied with (or provided with) a first alignment signal or a second alignment signal, respectively.

[0127] In implementations, the first alignment signal and the second alignment signal may have different waveforms, potentials, and / or phases. The first alignment signal may be a ground signal, and the second alignment signal may be an AC signal. However, this disclosure is not limited to the above examples. For example, the first alignment signal may be an AC signal, and the second alignment signal may be a ground signal.

[0128] In this implementation, different alignment signals can be applied to adjacent alignment electrodes. In the example, if a first alignment signal can be applied to a first alignment electrode ALE1, a second alignment signal can be applied to a second alignment electrode ALE2. If a first alignment signal is applied to a second alignment electrode ALE2, a second alignment signal can be applied to a first alignment electrode ALE1. If a first alignment signal is applied to a third alignment electrode ALE3, a second alignment signal can be applied to a fourth alignment electrode ALE4.

[0129] In an embodiment, an electric field can be formed between the first alignment electrode ALE1 and the second alignment electrode ALE2 (or on the first alignment electrode ALE1 and the second alignment electrode ALE2), and the first light-emitting element LD1 and the second light-emitting element LD2 can be aligned based on the electric field on the first alignment electrode ALE1 and the second alignment electrode ALE2.

[0130] In an embodiment, an electric field can be formed between (or on) the third alignment electrode ALE3 and the fourth alignment electrode ALE4, and the third light-emitting element LD3 and the fourth light-emitting element LD4 can be aligned on the third alignment electrode ALE3 and the fourth alignment electrode ALE4 based on the electric field.

[0131] In an implementation, the first light-emitting element LD1 can be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. In an example, the first light-emitting element LD1 can be aligned in a region (e.g., the lower region) of the first alignment electrode ALE1 and the second alignment electrode ALE2, the first end EP1 of the first light-emitting element LD1 can be electrically connected to the first pixel electrode ELT1, and the second end EP2 of the first light-emitting element LD1 can be electrically connected to the second pixel electrode ELT2.

[0132] In one implementation, the second light-emitting element LD2 can be aligned between the first alignment electrode ALE1 and the second alignment electrode ALE2. In another example, the second light-emitting element LD2 can be aligned in another region (e.g., the upper region) of the first alignment electrode ALE1 and the second alignment electrode ALE2, the first end EP1 of the second light-emitting element LD2 can be electrically connected to the second pixel electrode ELT2, and the second end EP2 of the second light-emitting element LD2 can be electrically connected to the third pixel electrode ELT3.

[0133] In one implementation, the third light-emitting element LD3 can be aligned between the third alignment electrode ALE3 and the fourth alignment electrode ALE4, and is electrically connected between the third pixel electrode ELT3 and the fourth pixel electrode ELT4. In another example, the third light-emitting element LD3 can be aligned in another region (e.g., the upper region) of the third alignment electrode ALE3 and the fourth alignment electrode ALE4, the first end EP1 of the third light-emitting element LD3 can be electrically connected to the third pixel electrode ELT3, and the second end EP2 of the third light-emitting element LD3 can be electrically connected to the fourth pixel electrode ELT4.

[0134] In one embodiment, the fourth light-emitting element LD4 can be aligned between the third alignment electrode ALE3 and the fourth alignment electrode ALE4, and is electrically connected between the fourth pixel electrode ELT4 and the fifth pixel electrode ELT5. In an example, the fourth light-emitting element LD4 can be aligned in a region (e.g., the lower region) of the third alignment electrode ALE3 and the fourth alignment electrode ALE4, the first end EP1 of the fourth light-emitting element LD4 can be electrically connected to the fourth pixel electrode ELT4, and the second end EP2 of the fourth light-emitting element LD4 can be electrically connected to the fifth pixel electrode ELT5.

[0135] In this embodiment, the first light-emitting element LD1 may be located in the lower left region of the first emission region EMA1, and the second light-emitting element LD2 may be located in the upper left region of the first emission region EMA1. The third light-emitting element LD3 may be located in the upper right region of the first emission region EMA1, and the fourth light-emitting element LD4 may be located in the lower right region of the first emission region EMA1. However, the arrangement and / or connection structure of the light-emitting elements LD can be adjusted according to the emission portion (e.g., Figure 4 The structure of the transmitter section (EMU) and / or the number of cascade stages vary.

[0136] In this embodiment, some of the first alignment electrodes ALE1 to the fourth alignment electrodes ALE4 can be electrically connected to some of the pixel electrodes ELT1 to ELT5 through contact holes. For example, the first alignment electrode ALE1 can be electrically connected to the first pixel electrode ELT1 through a first contact hole CH1 located in the non-emitting region NEA, and the third alignment electrode ALE3 can be electrically connected to the fifth pixel electrode ELT5 through a second contact hole CH2 located in the non-emitting region NEA.

[0137] In an embodiment, after the light-emitting elements LD1, LD2, LD3 and LD4 are provided and aligned in the first emission region EMA1 and the second emission region EMA2, at least one of the first alignment electrodes ALE1 to the fourth alignment electrodes ALE4 can be separated from the alignment electrodes ALE1 to ALE4 disposed in the second pixel PXL2 adjacent to the first pixel PXL1.

[0138] The first dummy electrode ALE1a disposed in the first pixel PXL1 and the first dummy electrode ALE1b disposed in the second pixel PXL2 can be integrally connected (or integral with each other) to form the first alignment electrode ALE1. The first dummy electrode ALE1a can be electrically connected to the pixel circuitry (e.g., through a contact hole) Figure 4 The pixel circuit (PXC) and / or the first power line PL1. A first alignment signal (or a second alignment signal) can be provided to the first alignment electrode ALE1 through the pixel circuit PXC or the first power line PL1. After the alignment of the light-emitting element LD is completed, the first alignment electrode ALE1 can be separated into the first dummy electrode ALE1a of the first pixel PXL1 and the first dummy electrode ALE1b of the second pixel PXL2 by removing the first alignment electrode ALE1 from the first floating region FLA1 located around the first dummy electrode ALE1a.

[0139] In this embodiment, the second dummy electrode ALE2a disposed in the first pixel PXL1 and the second dummy electrode ALE2b disposed in the second pixel PXL2 can be integrally connected (or integral with each other) to form the second alignment electrode ALE2. A second alignment signal (or a first alignment signal) can be provided to the second dummy electrode ALE2a through a contact hole (not shown). After the alignment of the light-emitting element LD is completed, the second alignment electrode ALE2 can be separated into the second dummy electrode ALE2a of the first pixel PXL1 and the second dummy electrode ALE2b of the second pixel PXL2 by removing the second alignment electrode ALE2a from the second floating region FLA2 located around the second dummy electrode ALE2a in the non-emitting region NEA. The electrical connection between the second dummy electrode ALE2a of the first pixel PXL1 and the second dummy electrode ALE2b of the second pixel PXL2 can be disconnected.

[0140] In this embodiment, the third dummy electrode ALE3a disposed in the first pixel PXL1 and the third dummy electrode ALE3b disposed in the second pixel PXL2 can be integrally connected (or integral with each other) to form the third alignment electrode ALE3. The third dummy electrode ALE3a can be electrically connected to the pixel circuit PXC and / or the second power line PL2 through a contact hole. The second alignment signal (or the first alignment signal) can be provided to the third dummy electrode ALE3a through the pixel circuit PXC and / or the second power line PL2. After the alignment of the light-emitting element LD is completed, the third alignment electrode ALE3 can be separated into the third dummy electrode ALE3a of the first pixel PXL1 and the third dummy electrode ALE3b of the second pixel PXL2 by removing the third alignment electrode ALE3 from the third floating region FLA3 located around the third dummy electrode ALE3a.

[0141] In this embodiment, the fourth dummy electrode ALE4a disposed in the first pixel PXL1 and the fourth dummy electrode ALE4b disposed in the second pixel PXL2 can be integrally connected (or integrally formed with each other) to form the fourth alignment electrode ALE4. A second alignment signal (or a first alignment signal) can be provided to the fourth dummy electrode ALE4a through a contact hole (not shown). After the alignment of the light-emitting element LD is completed, the fourth alignment electrode ALE4 can be separated into the fourth dummy electrode ALE4a of the first pixel PXL1 and the fourth dummy electrode ALE4b of the second pixel PXL2 by removing the fourth alignment electrode ALE4a from the fourth floating region FLA4 located around the fourth dummy electrode ALE4a in the non-emitting region NEA. The electrical connection between the fourth dummy electrode ALE4a of the first pixel PXL1 and the fourth dummy electrode ALE4b of the second pixel PXL2 can be disconnected.

[0142] In an implementation, by separating each of the first alignment electrodes ALE1 to the fourth alignment electrodes ALE4, the first alignment electrodes ALE1 to the fourth alignment electrodes ALE4 can be separated into first dummy electrodes ALE1a to fourth dummy electrodes ALE4a that overlap with the first emission region EMA1 of the first pixel PXL1 in a view or direction (e.g., in a plan view) and first dummy electrodes ALE1b to fourth dummy electrodes ALE4b that overlap with the second emission region EMA2 of the second pixel PXL2.

[0143] In this embodiment, dummy electrodes ALE1a to ALE4a of the first pixel PXL1 may be disposed at least in the first emission region EMA1. The dummy electrodes ALE1a to ALE4a may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The dummy electrodes ALE1a to ALE4a may extend from the first emission region EMA1 to the non-emission region NEA. For example, the dummy electrodes ALE1a to ALE4a may extend from the first emission region EMA1 to the opening region OPA. The first dummy electrode ALE1a, the second dummy electrode ALE2a, the third dummy electrode ALE3a, and the fourth dummy electrode ALE4a may extend in the second direction DR2 and may be arranged sequentially in the first direction DR1, spaced apart from each other.

[0144] In one implementation, the electrical connection between the first dummy electrode ALE1b and the first power line PL1 can be disconnected by removing a portion of the contact hole of the first alignment electrode ALE1 located in the non-emission region NEA. Similarly, the electrical connection between the third dummy electrode ALE3b and the second power line PL2 can be disconnected by removing a portion of the contact hole of the third alignment electrode ALE3 located in the non-emission region NEA.

[0145] In an implementation, the opening region OPA can refer to a region that includes the interval region between the dummy electrodes ALE1a to ALE4a and the dummy electrodes ALE1b to ALE4b respectively included in the first pixel PXL1 and the second pixel PXL2.

[0146] In this embodiment, the dummy electrodes ALE1a to ALE4a of the first pixel PXL1 and the dummy electrodes ALE1b to ALE4b of the second pixel PXL2 can be configured as rods with a constant width in the emission regions EMA1 and EMA2, but this disclosure is not limited thereto. The dummy electrodes ALE1a to ALE4a of the first pixel PXL1 and the dummy electrodes ALE1b to ALE4b of the second pixel PXL2 can have a rod shape with a constant width or a shape with a curved portion in the non-emission region NEA, but the shape and / or size of the dummy electrodes ALE1a to ALE4a of the first pixel PXL1 and the dummy electrodes ALE1b to ALE4b of the second pixel PXL2 in the remaining areas other than the emission regions EMA1 and EMA2 are not particularly limited and can be varied in various ways.

[0147] In an embodiment, the first pixel electrode ELT1 to the fifth pixel electrode ELT5 may be disposed in each of the emission regions EMA1 and EMA2, and may be configured to overlap with one or more dummy electrodes ALE1a to ALE4a and ALE1b to ALE4b and / or light-emitting elements LD1 to LD4. For example, each of the pixel electrodes ELT1 to ELT5 may be formed on the dummy electrodes ALE1a to ALE4a and ALE1b to ALE4b and / or light-emitting elements LD1 to LD4 to overlap with the dummy electrodes ALE1a to ALE4a and ALE1b to ALE4b and / or light-emitting elements LD1 to LD4, and may be electrically connected to the light-emitting elements LD.

[0148] In an embodiment, the first pixel electrode ELT1 may be disposed in a region (e.g., the lower region) of the first dummy electrode ALE1a and the first terminal EP1 of the first light-emitting element LD1, and may be electrically connected to the first terminal EP1 of the first light-emitting element LD1.

[0149] In an embodiment, the second pixel electrode ELT2 can be disposed in one region (e.g., the lower region) of the second dummy electrode ALE2a and on the second end EP2 of the first light-emitting element LD1, and can be electrically connected to the second end EP2 of the first light-emitting element LD1. The second pixel electrode ELT2 can also be disposed in another region (e.g., the upper region) of the first dummy electrode ALE1a and on the first end EP1 of the second light-emitting element LD2, and can be electrically connected to the first end EP1 of the second light-emitting element LD2. For example, the second pixel electrode ELT2 can be electrically connected to the second end EP2 of the first light-emitting element LD1 and the first end EP1 of the second light-emitting element LD2 in the first emission region EMA1. For this purpose, the second pixel electrode ELT2 can have a curved shape. For example, the second pixel electrode ELT2 can have a structure that is bent or curved at the boundary between the region where at least one first light-emitting element LD1 is disposed and the region where at least one second light-emitting element LD2 is disposed.

[0150] In an embodiment, the third pixel electrode ELT3 can be disposed in another region (e.g., the upper region) of the second dummy electrode ALE2a and on the second end EP2 of the second light-emitting element LD2, and can be electrically connected to the second end EP2 of the second light-emitting element LD2. The third pixel electrode ELT3 can also be disposed in another region (e.g., the upper region) of the fourth dummy electrode ALE4a and on the first end EP1 of the third light-emitting element LD3, and can be electrically connected to the first end EP1 of the third light-emitting element LD3. For example, the third pixel electrode ELT3 can be electrically connected to the second end EP2 of the second light-emitting element LD2 and the first end EP1 of the third light-emitting element LD3 in the first emission region EMA1. For this purpose, the third pixel electrode ELT3 can have a curved shape. For example, the third pixel electrode ELT3 can have a structure that is bent or curved at the boundary between the region where at least one second light-emitting element LD2 is disposed and the region where at least one third light-emitting element LD3 is disposed.

[0151] In one embodiment, the fourth pixel electrode ELT4 can be disposed in another region (e.g., the upper region) of the third dummy electrode ALE3a and on the second end EP2 of the third light-emitting element LD3, and can be electrically connected to the second end EP2 of the third light-emitting element LD3. The fourth pixel electrode ELT4 can also be disposed in a region (e.g., the lower region) of the fourth dummy electrode ALE4a and on the first end EP1 of the fourth light-emitting element LD4, and can be electrically connected to the first end EP1 of the fourth light-emitting element LD4. For example, the fourth pixel electrode ELT4 can be electrically connected to the second end EP2 of the third light-emitting element LD3 and the first end EP1 of the fourth light-emitting element LD4 in the first emission region EMA1. For this purpose, the fourth pixel electrode ELT4 can have a curved shape. For example, the fourth pixel electrode ELT4 can have a structure that is bent or curved at the boundary between the region where at least one third light-emitting element LD3 is disposed and the region where at least one fourth light-emitting element LD4 is disposed.

[0152] In an implementation, the fifth pixel electrode ELT5 can be disposed in a region (e.g., the lower region) of the third dummy electrode ALE3a and on the second end EP2 of the fourth light-emitting element LD4, and can be electrically connected to the second end EP2 of the fourth light-emitting element LD4.

[0153] In the same manner as described above, the first light-emitting elements LD1 to the fourth light-emitting element LD4 aligned between the dummy electrodes ALE1a to ALE4a can be electrically connected in a desired manner using pixel electrodes ELT1 to ELT5. For example, the first light-emitting element LD1, the second light-emitting element LD2, the third light-emitting element LD3, and the fourth light-emitting element LD4 can be electrically connected in series sequentially using pixel electrodes ELT1 to ELT5.

[0154] Figure 5b and Figure 5c It is shown schematically. Figure 4 Other examples of pixel planar diagrams.

[0155] refer to Figure 5a and Figure 5b At least the first pixel electrode ELT1' of the first pixel PXL1 can be connected with Figure 5a The first pixel electrode ELT1 shown is different. The same reference numerals are used for the same or corresponding components, and repeated descriptions will be omitted.

[0156] Figure 5a The first pixel electrode ELT1 and the fifth pixel electrode ELT5 can extend from the first emitting region EMA1 to the non-emitting region NEA, and can be configured as a bar shape with a constant width.

[0157] Figure 5bThe first pixel electrode ELT1' may include a bar shape with a constant width and a shape protruding in one direction with a curved portion. The bar-shaped portion of the first pixel electrode ELT1' may extend from the first emitting region EMA1 to the non-emitting region NEA. The curved portion of the first pixel electrode ELT1' may be disposed in the non-emitting region NEA.

[0158] The embodiment illustrates a case where a portion of the first pixel electrode ELT1' having a curved portion is electrically connected to a portion of the first pixel electrode ELT1' having a rod-shaped portion and protrudes in a first direction DR1, but the present disclosure is not limited thereto. The portion of the first pixel electrode ELT1' having a curved portion may protrude in a direction opposite to the first direction DR1 relative to the rod-shaped portion of the first pixel electrode ELT1'.

[0159] In an implementation, the first pixel electrode ELT1' can extend from the first emitting region EMA1 to the non-emitting region NEA, and can include a first part, a second part, and a third part. The first part is disposed on the first dummy electrode ALE1a and connected to (or extended to) the first contact hole CH1. The second part extends or protrudes from the first part in the first direction DR1 to be disposed on the second dummy electrode ALE2b. The third part extends from the second part and is disposed on the first dummy electrode ALE1b of the second pixel PXL2.

[0160] In an implementation, the second portion of the first pixel electrode ELT1' may overlap with a region of the second dummy electrode ALE2a of the first pixel PXL1 and a region of the second dummy electrode ALE2b of the second pixel PXL2. In an example, the first contact hole CH1 formed in the first portion of the first pixel electrode ELT1' may be surrounded by the second portion and the third portion of the first pixel electrode ELT1'.

[0161] In one implementation, the second pixel PXL2 may include the first pixel electrode ELT1. In another example, the second pixel PXL2 may include the first pixel electrode ELT1'.

[0162] refer to Figure 5a and Figure 5c At least the first pixel electrode ELT1” of the first pixel PXL1 and the second pixel electrode ELT2” of the second pixel PXL2 can be connected with Figure 5a The ones shown are different. Therefore, the same reference numerals are used for the same or corresponding components, and repeated descriptions will be omitted.

[0163] The first pixel PXL1 may include a first pixel electrode ELT1, and the second pixel PXL2 may include a second pixel electrode ELT2.

[0164] The first pixel electrode ELT1” of the first pixel PXL1 may include a first portion of a rod shape with a constant width and a second portion having a protrusion extending from the rod shape in one direction. The first portion of the rod shape of the first pixel electrode ELT1” may extend from the first emitting region EMA1 to the non-emitting region NEA. The second portion of the first pixel electrode ELT1” with the protrusion may be disposed in the non-emitting region NEA.

[0165] In an implementation, the first pixel electrode ELT1” can extend from the first emitting region EMA1 to the non-emitting region NEA, and may include a first portion disposed on the first dummy electrode ALE1a and including the first contact hole CH1, and a second portion extending from the first portion and overlapping at least one region of the second dummy electrode ALE2a of the first pixel PXL1.

[0166] In an embodiment, the second pixel electrode ELT2” of the second pixel PXL2 may include a rod shape with a constant width and a protrusion extending from the rod shape in one direction. The rod-shaped portion of the second pixel electrode ELT2” may extend from the second emission region EMA2 to the non-emission region NEA (or the non-emission region NEA between the first emission region EMA1 and the second emission region EMA2). The portion of the second pixel electrode ELT2” with the protrusion may be disposed in the non-emission region NEA.

[0167] In an implementation, the second pixel electrode ELT2” can extend from the second emitting region EMA2 to the non-emitting region NEA, and can include a first portion disposed on the first dummy electrode ALE1b and a second portion extending from the first portion and overlapping at least one region of the second dummy electrode ALE2a of the first pixel PXL1.

[0168] In an embodiment, the first pixel electrode ELT1” of the first pixel PXL1 can be configured to be spaced apart from the second portion of the second pixel electrode ELT2” of the second pixel PXL2 in the second direction DR2. The second portion of the first pixel electrode ELT1” of the first pixel PXL1 and the second portion of the second pixel electrode ELT2” of the second pixel PXL2 can overlap with the second dummy electrode ALE2a of the first pixel PXL1.

[0169] Figures 5a to 5c The planar view of pixel PXL shown can illustrate pixel PXL in its normal state, but this disclosure is not limited thereto. For example, Figures 5a to 5cThe pixel PXL shown can be the pixel PXL in the defective state (reference). Figure 7a Pixels PXL before the repair process was performed.

[0170] In the event that the light-emitting state of the light-emitting element LD of the first pixel PXL1 is defective due to a defect in the pixel circuit PXC of the first pixel PXL1 during the manufacturing process of the first pixel PXL1, Figure 5b The first pixel electrode ELT1' and Figure 5c Each of the first pixel electrodes ELT1' can be a pixel electrode provided for convenience during the repair process of the first pixel PXL1 in a defective state. In the example, the third part of the first pixel electrode ELT1' can be... Figure 9 The third part of ELT1'c) and the second part of the first pixel electrode ELT1" (e.g., Figure 12 The second part, ELT1”b), performs the repair process.

[0171] Figure 6a It is schematically shown along Figure 5a An example sectional view of the section cut by line A-A'. Figure 6b It is schematically shown along Figure 5a A cross-sectional view of an example section taken by line B-B'.

[0172] The following text will focus on the first light-emitting element LD1 reference. Figure 6a and Figure 6b Describe the cross-sectional structure of the first pixel PXL1 in detail. Figure 6a and Figure 6b The first transistor T1 is shown as a component of the pixel circuit (e.g., Figure 4 Examples of various circuit elements in a pixel circuit (PXC). Unless otherwise specified, first transistor T1 through third transistor T3 will be collectively referred to as "transistor T". The structure and / or location of each layer of transistor T is not limited to... Figure 6a The embodiments shown are different from those described above and can be modified in various ways.

[0173] refer to Figure 5a , Figure 6a and Figure 6b The circuit element layer of the first pixel PXL1 may include circuit elements and various wirings electrically connected to the circuit elements. The circuit elements include transistors T disposed on the base layer BSL. Dummy electrodes ALE1a to ALE4a, light-emitting elements LD1 to LD4, and pixel electrodes ELT1 to ELT5 constituting the emitting portion EMU may be disposed on the circuit elements. A light-emitting element layer may be disposed on the circuit element layer. The light-emitting element layer may include light-emitting elements LD.

[0174] In embodiments, the base layer (BSL) can constitute a basic component and can be a rigid substrate or film, or a flexible substrate or film. As an example, the base layer (BSL) can be a rigid substrate made of glass or tempered glass, a flexible substrate (or film) made of plastic or metal, or at least one insulating layer. The material and / or physical properties of the base layer (BSL) are not particularly limited. In embodiments, the base layer (BSL) can be substantially transparent. The expression "substantially transparent" can mean that light can be transmitted at a transmittance (e.g., a predetermined or optional transmittance) or higher. In another embodiment, the base layer (BSL) can be translucent or opaque. According to embodiments, the base layer (BSL) may include a reflective material.

[0175] In this implementation, a buffer layer BFL can be disposed on the base layer BSL. The buffer layer BFL prevents impurities from diffusing into the circuit elements. The buffer layer BFL can consist of a single layer, but it can also consist of multiple layers, including at least two layers. When the buffer layer BFL is formed as a multilayer, each layer can be formed of the same material or different materials.

[0176] The buffer layer BFL can be an inorganic insulating layer comprising inorganic materials. In an example, the buffer layer BFL may comprise silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and such as aluminum oxide (AlO) x At least one of the metal oxides of ). The buffer layer BFL can be a single layer, but it can also be a multilayer comprising at least two layers.

[0177] A semiconductor pattern SCP can be disposed on a buffer layer BFL. The semiconductor pattern SCP may include a first region contacting a first transistor electrode TE1, a second region contacting a second transistor electrode TE2, and a channel region located between the first and second regions. According to an embodiment, one of the first and second regions may be a source region, and the other may be a drain region. In an embodiment, the first transistor electrode TE1 may be electrically connected to a first power conductive layer PL1a.

[0178] In this embodiment, the semiconductor pattern SCP can be formed from polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The channel region of the semiconductor pattern SCP can be an undoped semiconductor pattern, and can be an intrinsic semiconductor. The first and second regions of the semiconductor pattern SCP can be doped semiconductors.

[0179] refer to Figure 6a and Figure 6bThe gate insulating layer GI can be disposed on the buffer layer BFL and the semiconductor pattern SCP. As an example, the gate insulating layer GI can be disposed between the semiconductor pattern SCP and the gate electrode GE. The gate insulating layer GI can be disposed between the buffer layer BFL and the second power supply conductive layer PL2a. The gate insulating layer GI can consist of a single layer or multiple layers and can include various types of inorganic materials, such as silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x ).

[0180] The gate electrode GE and the second power conductive layer PL2a of transistor T can be disposed on the gate insulating layer GI. The gate electrode GE and the second power conductive layer PL2a can be disposed on the same layer. For example, the gate electrode GE and the second power conductive layer PL2a can be formed simultaneously in the same process, but this disclosure is not limited thereto. The gate electrode GE can be disposed on the gate insulating layer GI to overlap with the semiconductor pattern SCP on a third-direction DR3. The second power conductive layer PL2a can constitute a reference. Figure 4 The second power supply line PL2, etc., as described.

[0181] Each of the gate electrode GE and the second power conductive layer PL2a can be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn), or their oxides or alloys. For example, each of the gate electrode GE and the second power conductive layer PL2a can be formed as multiple layers in which titanium (Ti), copper (Cu), and / or indium tin oxide (ITO) are stacked sequentially or repeatedly.

[0182] The interlayer insulating layer (ILD) can be disposed on the gate electrode GE and the second power supply conductive layer PL2a. As an example, the ILD can be disposed between the gate electrode GE and the first transistor electrode TE1 and the second transistor electrode TE2. The ILD and the gate insulating layer GI can comprise the same material, or the ILD can comprise one or more materials selected from those constituting the gate insulating layer GI.

[0183] refer to Figure 6aThe first transistor electrode TE1 and the second transistor electrode TE2 can be configured to overlap the semiconductor pattern SCP on a third-direction DR3. The first transistor electrode TE1 and the second transistor electrode TE2 can be electrically connected to the semiconductor pattern SCP. For example, the first transistor electrode TE1 can be electrically connected to a first region of the semiconductor pattern SCP through a contact hole passing through the interlayer insulating layer (ILD). The second transistor electrode TE2 can be electrically connected to a second region of the semiconductor pattern SCP through a contact hole passing through the ILD. The second transistor electrode TE2 can be electrically connected to the conductive layer BML that receives the first drive power supply VDD. According to an embodiment, one of the first transistor electrode TE1 and the second transistor electrode TE2 can be a source electrode, and the other can be a drain electrode.

[0184] In an embodiment, the first transistor electrode TE1 and the second transistor electrode TE2 (and the first power conductive layer PL1a) can be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), indium (In), tin (Sn) or their oxides or alloys.

[0185] A passivation layer PSV can be disposed on the first transistor electrode TE1, the second transistor electrode TE2, and the second power supply conductive layer PL2a. The passivation layer PSV can consist of a single layer or multiple layers, and can include components such as silicon oxide (SiO2). x Inorganic materials.

[0186] In this implementation, the via layer VIA can be disposed on the passivation layer PSV. The via layer VIA can be made of organic materials to reduce the step difference. For example, the via layer VIA can include various types of inorganic materials.

[0187] In one embodiment, the dam pattern INP can be disposed on the through-hole layer VIA. According to another embodiment, the dam pattern INP can have various shapes. In one embodiment, the dam pattern INP can have a shape that protrudes in a third direction DR3 on the base layer BSL. The dam pattern INP can be formed with an inclined surface that is tilted relative to the base layer BSL at an angle (e.g., a predetermined or optional angle). However, this disclosure is not limited thereto, and the dam pattern INP can have curved or stepped sidewalls. As an example, the dam pattern INP can have a semi-circular or semi-elliptical cross-section.

[0188] Dummy electrodes ALE1a to ALE4a can be disposed on the via layer VIA and the embankment pattern INP. Dummy electrodes ALE1a to ALE4a can be spaced apart from each other in the first pixel PXL1. Dummy electrodes ALE1a to ALE4a can be disposed on the same layer. For example, dummy electrodes ALE1a to ALE4a can be formed simultaneously in the same process, but this disclosure is not limited thereto.

[0189] In an implementation, the dummy electrodes ALE1a to ALE4a disposed on the embankment pattern INP can have a cross-sectional shape corresponding to the cross-sectional shape of the embankment pattern INP. As an example, the dummy electrodes ALE1a to ALE4a disposed on the embankment pattern INP may include a sloping or curved surface having a shape corresponding to the shape of the embankment pattern INP. Therefore, the embankment pattern INP, together with the dummy electrodes ALE1a to ALE4a disposed thereon, can serve as a reflective member that improves the light output efficiency of the display device by guiding light emitted from the light-emitting element LD in the positive direction of the first pixel PXL1 (e.g., in the third direction DR3).

[0190] The dummy electrodes ALE1a to ALE4a can receive alignment signals during the alignment of the light-emitting element LD. Therefore, an electric field can be formed between the dummy electrodes ALE1a to ALE4a, so that the light-emitting element LD disposed in the first pixel PXL1 can be aligned between the dummy electrodes ALE1a to ALE4a.

[0191] The dummy electrodes ALE1a to ALE4a may comprise at least one conductive material. As an example, the dummy electrodes ALE may comprise various metallic materials, such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and copper (Cu). Since the dummy electrodes ALE1a to ALE4a may correspond to reflective electrodes, they may comprise metals (or metallic materials) with a specific reflectivity. The dummy electrodes ALE1a to ALE4a may comprise at least one of metals and alloys comprising metals. The dummy electrodes ALE1a to ALE4a may comprise at least one conductive material selected from conductive oxides and conductive polymers. The conductive oxide may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc tin oxide (ZTO), or gallium tin oxide (GTO). The conductive polymer may be, for example, poly(3,4-ethylenedioxythiophene) (PEDOT), but this disclosure is not limited thereto. At least one conductive material may be a material used to protect the metal.

[0192] In this embodiment, the first dummy electrode ALE1a can be electrically connected to the first transistor electrode TE1 of the transistor T through a contact hole passing through the via layer VIA and the passivation layer PSV. The third dummy electrode ALE3a can be electrically connected to the second power conductive layer PL2a through a contact hole passing through the via layer VIA, the passivation layer PSV, and the interlayer insulating layer ILD.

[0193] The first insulating layer INS1 can be disposed on the dummy electrodes ALE1a to ALE4a. The first insulating layer INS1 can consist of a single layer or multiple layers, and can include various types of inorganic materials.

[0194] A dam BNK can be disposed on the first insulating layer INS1. In the step of providing the light-emitting element LD to the first pixel PXL1, the dam BNK can be a dam structure that separates the emission area to which the light-emitting element LD will be provided. The desired type and / or amount of light-emitting element ink can be provided to the emission area separated by the dam BNK.

[0195] According to an embodiment, the dam BNK may include at least one light-blocking material and / or a reflective material. Therefore, light leakage between adjacent pixels PXL can be prevented. For example, the dam BNK may include at least one black matrix material and / or a color filter material. As an example, the dam BNK may be formed with a black opaque pattern capable of blocking light transmission. In an embodiment, a reflective film or the like may be formed on the surface (e.g., sidewalls) of the dam BNK to increase the light efficiency of each pixel PXL.

[0196] The light-emitting element (LD) can be disposed on the first insulating layer INS1. The LD can be disposed on the first insulating layer INS1 between the first dummy electrode ALE1a and the second dummy electrode ALE2a, and between the third dummy electrode ALE3a and the fourth dummy electrode ALE4a. The LD can be fabricated to be dispersed in a light-emitting element ink and can be provided to each pixel PXL by inkjet printing or the like. For example, the LD can be provided to each pixel PXL by dispersing it in a volatile solvent.

[0197] A second insulating layer INS2 can be disposed on the light-emitting element LD. For example, the second insulating layer INS2 can be partially disposed on the light-emitting element LD, and the first end EP1 and the second end EP2 of the light-emitting element LD can be exposed. When the second insulating layer INS2 is formed on the light-emitting element LD after alignment, it can prevent the light-emitting element LD from separating from the alignment position.

[0198] The third insulating layer INS3 may be disposed on at least a portion of the first insulating layer INS1 and on the embankment BNK.

[0199] Pixel electrodes (e.g., pixel electrodes ELT1, ELT2, ELT4, and ELT5) can be formed on the first end EP1 and the second end EP2 of the light-emitting element LD, which are exposed by the second insulating layer INS2 and the third insulating layer INS3. In an embodiment, the first pixel electrode ELT1 can be electrically connected to the first dummy electrode ALE1a through the first contact hole CH1, and the fifth pixel electrode ELT5 can be electrically connected to the third dummy electrode ALE3a through the second contact hole CH2. Since the first dummy electrode ALE1a can be electrically connected to the first power conductive layer PL1a, the first pixel electrode ELT1 can be electrically connected to the first power conductive layer PL1a through the first dummy electrode ALE1a. Since the third dummy electrode ALE3a can be electrically connected to the second power conductive layer PL2a, the fifth pixel electrode ELT5 can be electrically connected to the second power conductive layer PL2a through the second contact hole CH2.

[0200] In one embodiment, the first pixel electrode ELT1 can be directly disposed on the first end EP1 of the first light-emitting element LD1 and can contact the first end EP1 of the first light-emitting element LD1. The second pixel electrode ELT2 can be directly disposed on the second end EP2 of the first light-emitting element LD1 and can contact the second end EP2 of the first light-emitting element LD1. In another embodiment, the fourth pixel electrode ELT4 can be directly disposed on the first end EP1 of the fourth light-emitting element LD4 and can contact the first end EP1 of the fourth light-emitting element LD4. The fifth pixel electrode ELT5 can be directly disposed on the second end EP2 of the fourth light-emitting element LD4 and can contact the second end EP2 of the fourth light-emitting element LD4.

[0201] With the fourth insulating layer INS4 disposed between pixel electrodes ELT1, ELT2, ELT4, and ELT5, the pixel electrodes ELT1, ELT2, ELT4, and ELT5 can be stably separated from each other through the fourth insulating layer INS4. For example, the first pixel electrode ELT1 and the second pixel electrode ELT2 can be disposed on different layers with the fourth insulating layer INS4 interposed between them. Therefore, electrical stability between the first terminal EP1 and the second terminal EP2 of the light-emitting element LD can be ensured.

[0202] In an implementation, the fourth insulating layer INS4 may be configured to cover at least some areas of the first pixel electrode ELT1, the fourth pixel electrode ELT4, the second insulating layer INS2, and the third insulating layer INS3.

[0203] The third insulating layer INS3 and the fourth insulating layer INS4 can be composed of a single layer or multiple layers, and can include various types of inorganic materials.

[0204] Figure 6c It is shown that it includes Figure 3 A schematic cross-sectional view of the first to third pixels in a display device.

[0205] Figure 6c The setting is shown Figure 3 The pixel PXL has a light-emitting element layer LEL with a barrier wall WL, a color conversion layer CCL, an optical layer OPL, and a color filter layer CFL.

[0206] refer to Figure 6c The barrier wall WL can be disposed on the light-emitting element layer LEL of the first pixel PXL1 to the third pixel PXL3. As an example, the barrier wall WL can be disposed between the first pixel PXL1 and the third pixel PXL3 or at the boundary between the first pixel PXL1 and the third pixel PXL3, and can include openings that overlap with the first pixel PXL1 to the third pixel PXL3 respectively. The openings of the barrier wall WL can provide space for the color conversion layer CCL to be disposed therein.

[0207] The barrier wall WL may comprise organic materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, or benzocyclobutene (BCB). However, this disclosure is not limited thereto, and the barrier wall WL may comprise various types of inorganic materials, such as silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x ).

[0208] According to an embodiment, the barrier wall WL may include at least one light-blocking material and / or a reflective material. Therefore, light leakage between adjacent pixels PXL can be prevented. For example, the barrier wall WL may include at least one black matrix material and / or a color filter material. As an example, the barrier wall WL may be formed into a black opaque pattern capable of blocking light transmission. In an embodiment, a reflective film (not shown) or the like may be formed on the surface (e.g., sidewall) of the barrier wall WL to increase the light efficiency of each pixel PXL.

[0209] The color conversion layer CCL can be disposed on the light-emitting element layer LEL, which includes the light-emitting element LD, in the opening of the barrier wall WL. The color conversion layer CCL may include a first color conversion layer CCL1 disposed in the first pixel PXL1, a second color conversion layer CCL2 disposed in the second pixel PXL2, and a scattering layer LSL disposed in the third pixel PXL3.

[0210] In one embodiment, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements (LDs) that emit light of the same color. For example, the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 may include light-emitting elements (LDs) that emit light of a third color (or blue). By distributing color conversion layers (CCLs) including color conversion particles onto the light-emitting elements (LDs) of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3, respectively, a full-color image can be displayed.

[0211] The first color conversion layer CCL1 may include first color conversion particles that convert light of a third color emitted from the light-emitting element LD into light of a first color. For example, the first color conversion layer CCL1 may include first quantum dots QD1 dispersed in a matrix material such as a base resin.

[0212] In one embodiment, when the light-emitting element LD is a blue light-emitting element that emits blue light and the first pixel PXL1 is a red pixel, the first color conversion layer CCL1 may include a first quantum dot QD1 that converts blue light emitted from the blue light-emitting element into red light. The first quantum dot QD1 may absorb blue light and emit red light by shifting the wavelength according to the energy conversion. When the first pixel PXL1 is a pixel of a different color, the first color conversion layer CCL1 may include a first quantum dot QD1 corresponding to the color of the first pixel PXL1.

[0213] The second color conversion layer CCL2 may include second color conversion particles that convert light of a third color emitted from the light-emitting element LD into light of a second color. For example, the second color conversion layer CCL2 may include second quantum dots QD2 dispersed in a matrix material such as a base resin.

[0214] In one embodiment, when the light-emitting element LD is a blue light-emitting element that emits blue light and the second pixel PXL2 is a green pixel, the second color conversion layer CCL2 may include a second quantum dot QD2 that converts the blue light emitted by the blue light-emitting element into green light. The second quantum dot QD2 may absorb blue light and emit green light by shifting the wavelength according to the energy conversion. When the second pixel PXL2 is a pixel of a different color, the second color conversion layer CCL2 may include a second quantum dot QD2 corresponding to the color of the second pixel PXL2.

[0215] In this implementation, when blue light with a relatively short wavelength in the visible light region is incident on the first quantum dot QD1 and the second quantum dot QD2, the absorption coefficients of the first quantum dot QD1 and the second quantum dot QD2 can be increased. Therefore, the efficiency of the light ultimately emitted from the first pixel PXL1 and the second pixel PXL2 can be improved, and excellent color reproduction can be ensured. The emitting portions (EMUs) of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3 are configured using light-emitting elements (LDs) of the same color (e.g., blue light-emitting elements). Figure 4 (or light-emitting element layer (LEL)) can improve the manufacturing efficiency of display devices.

[0216] The scattering layer LSL can be configured to effectively utilize light of a third color (or blue) emitted from the light-emitting element LD. As an example, in the case where the light-emitting element LD is a blue light-emitting element that emits blue light and the third pixel PXL3 is a blue pixel, the scattering layer LSL can include at least one type of scatterer SCT to effectively utilize the light emitted from the light-emitting element LD.

[0217] For example, the scattering layer LSL may include a scatterer SCT dispersed in a matrix material such as a base resin. As an example, the scattering layer LSL may include a scatterer SCT such as silicon dioxide, but the material constituting the scatterer SCT is not limited to this. The scatterer SCT is not only disposed in the third pixel PXL3, but may also be selectively included in the first color conversion layer CCL1 or the second color conversion layer CCL2. According to embodiments, the scattering layer LSL made of a transparent polymer can be provided by omitting the scatterer SCT.

[0218] The first capping layer CPL1 can be disposed on the color conversion layer CCL. The first capping layer CPL1 can be disposed covering the first pixel PXL1 to the third pixel PXL3. The first capping layer CPL1 can cover the color conversion layer CCL. The first capping layer CPL1 can prevent impurities such as moisture or air from seeping in from the outside to damage or contaminate the color conversion layer CCL.

[0219] The first capping layer CPL1 can be an inorganic layer and may include silicon nitride (SiN). x ), aluminum nitride (AlN) x Titanium nitride (TiN) x ), silicon dioxide (SiO) x ), aluminum oxide (AlO) x Titanium oxide (TiO) x ), silicon dioxide (SiO) x C y ), silicon oxynitride (SiO) x N y )wait.

[0220] An optical layer OPL can be disposed on the first capping layer CPL1. The optical layer OPL can be used to improve light extraction efficiency by recycling light provided from the color conversion layer CCL through total internal reflection. For this purpose, the optical layer OPL can have a relatively low refractive index compared to the color conversion layer CCL. For example, the refractive index of the color conversion layer CCL can be from about 1.6 to about 2.0, and the refractive index of the optical layer OPL can be from about 1.1 to about 1.3.

[0221] The second capping layer CPL2 can be disposed on the optical layer OPL. The second capping layer CPL2 can be disposed across the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The second capping layer CPL2 can cover the optical layer OPL. The second capping layer CPL2 can prevent impurities such as moisture or air from damaging or contaminating the optical layer OPL by infiltration from the outside.

[0222] The second capping layer CPL2 can be an inorganic layer and may include silicon nitride (SiN). x ), aluminum nitride (AlN) x Titanium nitride (TiN) x ), silicon dioxide (SiO) x ), aluminum oxide (AlO) x Titanium oxide (TiO) x ), silicon dioxide (SiO) x C y ), silicon oxynitride (SiO) x N y )wait.

[0223] The planarization layer PLL can be set on the second capping layer CPL2. The planarization layer PLL can be set to extend across the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0224] The planarization layer PLL may include organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyester resin, polyphenylene sulfide resin, benzocyclobutene (BCB), etc. However, this disclosure is not limited thereto, and the planarization layer PLL may include various types of inorganic materials, such as silicon dioxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x ).

[0225] A color filter layer (CFL) can be placed on a planarization layer (PLL). The CFL can include color filters CF1, CF2, and CF3 corresponding to the color of each pixel PXL. A full-color image can be displayed by arranging color filters CF1, CF2, and CF3 corresponding to the colors of each of the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3.

[0226] The color filter layer CFL may include a first color filter CF1 disposed in a first pixel PXL1 to selectively transmit light emitted from the first pixel PXL1, a second color filter CF2 disposed in a second pixel PXL2 to selectively transmit light emitted from the second pixel PXL2, and a third color filter CF3 disposed in a third pixel PXL3 to selectively transmit light emitted from the third pixel PXL3.

[0227] In embodiments, the first color filter CF1, the second color filter CF2, and the third color filter CF3 may be a red color filter, a green color filter, and a blue color filter, respectively, but this disclosure is not limited thereto. In the following, if any of the first color filter CF1, the second color filter CF2, and the third color filter CF3 is mentioned arbitrarily, or if two or more types of color filters are mentioned inclusively, they will be referred to as "color filter CF" or "multiple color filters CF".

[0228] The first color filter CF1 may overlap with the light-emitting element layer LEL (or light-emitting element LD) and the first color conversion layer CCL1 of the first pixel PXL1 on the third-direction DR3. The first color filter CF1 may include a color filter material that selectively transmits light of a first color (or red). For example, if the first pixel PXL1 is a red pixel, the first color filter CF1 may include a red color filter material.

[0229] The second color filter CF2 may overlap the light-emitting element layer LEL (or light-emitting element LD) and the second color conversion layer CCL2 of the second pixel PXL2 on the third-direction DR3. The second color filter CF2 may include a color filter material that selectively transmits light of a second color (or green). For example, if the second pixel PXL2 is a green pixel, the second color filter CF2 may include a green color filter material.

[0230] The third color filter CF3 may overlap with the light-emitting element layer LEL (or light-emitting element LD) and the scattering layer LSL of the third pixel PXL3 on the third-direction DR3. The third color filter CF3 may include a color filter material that selectively transmits light of a third color (or blue). For example, if the third pixel PXL3 is a blue pixel, the third color filter CF3 may include a blue color filter material.

[0231] According to an embodiment, the light-blocking layer BM can be further disposed between the first color filter CF1, the second color filter CF2, and the third color filter CF3. Therefore, with the light-blocking layer BM formed between the first color filter CF1, the second color filter CF2, and the third color filter CF3, color mixing defects can be prevented from being visually identified from the front or side of the display device. The material of the light-blocking layer BM is not particularly limited and can be composed of various light-blocking materials. As an example, the light-blocking layer BM can be implemented by stacking the first color filter CF1, the second color filter CF2, and the third color filter CF3 on top of each other.

[0232] The outer coating OC can be applied to the color filter layer CFL. The outer coating OC can be applied across the first pixel PXL1, the second pixel PXL2, and the third pixel PXL3. The outer coating OC can cover the lower component, including the color filter layer CFL. The outer coating OC prevents moisture or air from penetrating the lower component. The outer coating OC protects the lower component from foreign matter such as dust.

[0233] The outer coating OC may include organic materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, polyester resins, polyphenylene sulfide resins, benzocyclobutene (BCB), etc. However, this disclosure is not limited thereto, and the outer coating OC may include various types of inorganic materials, such as silicon dioxide (SiO₂). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ), aluminum nitride (AlN) x ), aluminum oxide (AlO) x Zirconium oxide (ZrO) x ), hafnium oxide (HfO) x ) or titanium dioxide (TiO) x ).

[0234] Figure 7a This illustrates the situation where a pixel is in a defective state, including... Figure 3 A schematic diagram of the equivalent circuit of an example pixel in a display device.

[0235] Figure 7a The diagram schematically illustrates the state of the first pixel PXL1 in a defective condition. For example, Figure 7a The transmitting section EMU is shown due to Figure 4 The pixel PXL shown is in a state where it is unable to be electrically connected to the pixel circuit PXC via the second node N2 due to a defect in the pixel circuit PXC. When pixel PXL is in a defective state, the light-emitting element LD included in the corresponding pixel PXL may fail to emit light.

[0236] In this implementation, an inspection to determine whether the pixel PXL is defective can be performed during the manufacturing process of the pixel PXL. For example, during the setting of the alignment electrode (e.g., Figure 8 Alignment electrodes ALE1 to ALE4), and towards the emission region (e.g., Figure 8 After providing a light-emitting element LD in a first emission region EMA1 and a second emission region EMA2, aligning the light-emitting element LD by an electric field formed by alignment electrodes ALE1 to ALE4, and setting pixel electrodes ELT1 to ELT5 on the light-emitting element LD, an inspection to determine whether the pixel PXL is defective can be performed by a mother substrate inspection. The mother substrate inspection equipment can be an equipment capable of determining whether the pixel circuit PXC of the mother panel is defective. In the example, the inspection to determine whether the pixel PXL is defective can be performed after setting the pixel electrodes ELT1 to ELT5 on the light-emitting element LD and removing at least a portion of at least one of the alignment electrodes ALE1 to ALE4 (e.g., a separation process). In this disclosure, the inspection to determine whether the pixel PXL is emitting light (or conducting) normally will be referred to as an illumination inspection.

[0237] In an implementation, during the inspection to determine whether pixel PXL is defective, if the first pixel PXL1 is in a defective state and the second pixel PXL2 adjacent to the first pixel PXL1 is in a normal state, a repair process for the first pixel PXL1 can be performed.

[0238] In the following text, reference will be made to Figures 7b to 13 This describes a method for repairing pixels in a defective state.

[0239] Figure 7b and Figure 7c This is shown for explanation Figure 7a A schematic diagram of the equivalent circuit of an example pixel in a defective state repair method.

[0240] refer to Figure 7b and Figure 7c In the case where the first pixel PXL1 is in a defective state and the second pixel PXL2 (or the second pixel PXL2 adjacent to the first pixel PXL1) is in a normal state, the repair method may include disconnecting the connection between the emission portion EMU and the pixel circuit PXC in the first pixel PXL1 and using a dummy electrode (e.g., Figure 8 One of the first dummy electrodes ALE1a to the fourth dummy electrodes ALE4a and the first dummy electrodes ALE1b to the fourth dummy electrodes ALE4b (e.g., Figure 5aThe first dummy electrode ALE1a to the fourth dummy electrode ALE4a and the first dummy electrode ALE1b to the fourth dummy electrode ALE4b electrically connect the anode electrodes of the first pixel PXL1 and the second pixel PXL2 to each other.

[0241] refer to Figure 7b By using dummy electrodes ALE1a to ALE4a and ALE1b to ALE4b, which are partially removed and in a floating state after receiving the first alignment signal QVDD, the anode electrode of the second pixel PXL2 can be electrically connected to the anode electrode of the first pixel PXL1.

[0242] refer to Figure 7c By using dummy electrodes ALE1a to ALE4a and ALE1b to ALE4b, which are partially removed and in a floating state after receiving the second alignment signal QVSS, the anode electrode of the second pixel PXL2 can be electrically connected to the anode electrode of the first pixel PXL1.

[0243] Figure 8 and Figure 9 This is shown for explanation Figure 7a A schematic plan view of an example pixel in a defective state, illustrating a method for repairing pixels.

[0244] refer to Figure 7a , Figure 8 and Figure 9 When the first pixel PXL1 is in a defective state and the second pixel PXL2 adjacent to the first pixel PXL1 is in a normal state, a repair process for the first pixel PXL1 can be performed in the opening region OPA, which is the non-emitting region NEA. The repair process for the first pixel PXL1 may include cutting a portion of the first pixel electrode ELT1 of the first pixel PXL1 to disconnect the connection between the first pixel electrode ELT1 and the pixel circuit PXC, and electrically connecting the first pixel electrode ELT1 of the first pixel PXL1 to the anode electrode of the second pixel PXL2 adjacent to the first pixel PXL1.

[0245] refer to Figure 8 The process of disconnecting the connection between the first pixel electrode ELT1 of the first pixel PXL1 and the pixel circuit PXC can be performed in the non-emitting region NEA.

[0246] In one implementation, a portion of the first pixel electrode ELT1 of the first pixel PXL1 can be removed from the non-emitting region NEA. In an example, the first pixel electrode ELT1 can be removed by irradiating or emitting a laser into the cutting region LCA located in the region adjacent to the first contact hole CH1.

[0247] In one embodiment, the first pixel electrode ELT1 can be separated into a first partial electrode ELT1a and an isolation electrode ILT by removing the cutting region LCA of the first pixel electrode ELT1. The isolation electrode ILT can be configured to be spaced apart from the first partial electrode ELT1a in the second direction DR2, and can be not electrically connected to the first partial electrode ELT1a.

[0248] In an implementation, the isolation electrode ILT may include a first contact hole CH1. In an example, the isolation electrode ILT can be electrically connected to a first dummy electrode ALE1a through the first contact hole CH1. The first dummy electrode ALE1a can contact a pixel circuit layer disposed below the first dummy electrode ALE1a (e.g., Figure 10 The pixel circuit PXC in the pixel circuit layer (PCL).

[0249] In this embodiment, the first partial electrode ELT1a may contact the first end EP1 of the first light-emitting element LD1 in the first emitting region EMA1. At least a portion of the first partial electrode ELT1a may extend from the first emitting region EMA1 to the non-emitting region NEA. The first partial electrode ELT1a may be in a floating state because it is not electrically connected to the isolation electrode ILT.

[0250] Figure 9 The process is shown to electrically connect the first partial electrodes ELT1a and ELT1'a to the second pixel electrode ELT2 of the second pixel PXL2, which is adjacent to the first pixel PXL1, after performing the process of disconnecting the first pixel electrodes ELT1 and ELT1' of the first pixel PXL1 from the pixel circuit PXC.

[0251] refer to Figure 9 The first partial electrode ELT1a can extend from the first emitting region EMA1 to the non-emitting region NEA, and can be integrated with the second partial electrode ELT1b and the third partial electrode ELT1c. The third partial electrode ELT1c can have a shape having a curved portion that overlaps with the first dummy electrode ALE1b of the second pixel PXL2. The second partial electrode ELT1b can be an electrode that electrically connects the first partial electrode ELT1a and the third partial electrode ELT1c. For example, the second partial electrode ELT1b can be formed to bypass the isolation electrode ILT. In the example, the second partial electrode ELT1b can protrude from the first partial electrode ELT1a in the first direction DR1 and overlap with the second dummy electrode ALE2a. However, this disclosure is not limited to this, and the second partial electrode ELT1b can protrude in a direction opposite to the first direction DR1.

[0252] In an implementation, in the first pixel electrode (e.g., Figure 5aAfter the first pixel electrode (ELT1) is separated into a first partial electrode (ELT1a) and an isolation electrode (ILT), the second partial electrode (ELT1b) and the third partial electrode (ELT1c) can be integrated with the first partial electrode (ELT1a). For example, a process for forming the second partial electrode (ELT1b) and the third partial electrode (ELT1c) can be performed such that the first partial electrode (ELT1a) is electrically connected to the second partial electrode (ELT1b) and the third partial electrode (ELT1c).

[0253] In an embodiment, the second partial electrode ELT1b and the third partial electrode ELT1c can be repair electrodes formed to electrically connect the first partial electrode ELT1a to the second pixel electrode ELT2 of the second pixel PXL2. The second partial electrode ELT1b and the third partial electrode ELT1c can be formed using at least one of conductive ink and chemical vapor deposition (CVD) methods.

[0254] In another example, the second partial electrode ELT1'b and the third partial electrode ELT1'c can be components of the first pixel electrode (e.g., Figure 5b The first pixel electrode (ELT1') is an electrode. In the example, during the process of setting the pixel electrode in the manufacturing process of the display device, the first pixel electrode (ELT1') may be configured to overlap with the first dummy electrode (ALE1a) and the first light-emitting element (LD1) in the first emission region (EMA1), and may be configured to overlap with the first dummy electrode (ALE1a), the second dummy electrode (ALE2a), and the first dummy electrode (ALE1b) in the non-emission region (NEA).

[0255] In this embodiment, when the first pixel electrode ELT1' of the first pixel PXL1 is formed during the manufacturing process of the display device, since the repair electrodes (e.g., the second partial electrode ELT1'b and the third partial electrode ELT1'c) are pre-formed before the repair process of the first pixel PXL1, the step of forming the repair electrodes can be omitted in the repair process of the first pixel PXL1. For example, after the first pixel electrode ELT1' is separated into the first partial electrode ELT1'a and the isolation electrode ILT, a process of forming a contact hole in the region of the third partial electrode ELT1'c can be performed.

[0256] During the manufacturing process of a display device, by setting a first pixel electrode ELT1' for the repair process of pixels in a defective state, the efficiency of the repair process of defective pixels can be improved.

[0257] In this embodiment, the third partial electrodes ELT1c and ELT1'c can be electrically connected to the first dummy electrode ALE1b of the second pixel PXL2 through the third contact hole CH3. Therefore, the first partial electrode ELT1a of the first pixel PXL1 can be electrically connected to the second pixel electrode ELT2 of the second pixel PXL2.

[0258] In one embodiment, the second pixel electrode ELT2 of the second pixel PXL2 can be electrically connected to the first dummy electrode ALE1b of the second pixel PXL2 via a fourth contact hole CH4. Although the fourth contact hole CH4 is shown as being formed in the second emission region EMA2 of the second pixel PXL2, this disclosure is not limited thereto, and the fourth contact hole CH4 can be formed in the non-emission region NEA. When the fourth contact hole CH4 is formed in the non-emission region NEA, the second pixel electrode ELT2 of the second pixel PXL2 can extend from the second emission region EMA2 to the non-emission region NEA.

[0259] In the implementation, the third part electrodes ELT1c and ELT1'c can be electrically connected to the anode electrode of the second pixel PXL2 through the first dummy electrode ALE1b of the second pixel PXL2 and the second pixel electrode ELT2 of the second pixel PXL2.

[0260] In a first pixel PXL1 and a second pixel PXL2 that emit light of the same color, if the light-emitting element LD of the first pixel PXL1 fails to emit light due to a defect in the pixel circuit PXC, the first pixel PXL1 in its defective state can be repaired by electrically connecting the anode electrode of the second pixel PXL2, which is adjacent to the first pixel PXL1 and is in a normal state, to the first pixel PXL1. This repair process for defective pixels prevents a decrease in the luminous efficiency of the pixel PXL1 due to defects in the pixel circuit PXC.

[0261] Figure 10 It is schematically shown along Figure 8 A cross-sectional view of an example section taken by line I-I'.

[0262] refer to Figure 10 The first dummy electrode ALE1a of the embankment BNK and the first pixel PXL1 can be set on the pixel circuit layer PCL.

[0263] In an implementation, the pixel circuit layer (PCL) can refer to a pixel circuit that includes transistors and signal lines electrically connected to the transistors (e.g., ...). Figure 4 The pixel circuit (PXC) layer.

[0264] In one embodiment, the first dummy electrode ALE1b of the second pixel PXL2 can be disposed on the pixel circuit layer PCL to cover the dam BNK. A first insulating layer INS1 and a third insulating layer INS3 can be disposed on the first dummy electrode ALE1a of the first pixel PXL1 and the first dummy electrode ALE1b of the second pixel PXL2. The first dummy electrode ALE1b of the second pixel PXL2, as well as the first insulating layer INS1 and the third insulating layer INS3, can be configured to protrude on a third-direction DR3 according to the shape of the dam BNK.

[0265] In an implementation, the first alignment electrode can be removed in the first floating region FLA1 (e.g., Figure 8 The first alignment electrode ALE1) and at least a portion of the first insulating layer INS1 and the third insulating layer INS3. The first dummy electrode ALE1a of the first pixel PXL1 and the first dummy electrode ALE1b of the second pixel PXL2 may not be electrically connected to each other.

[0266] In an implementation, the first pixel electrode ELT1 of the first pixel PXL1 and the second pixel electrode ELT2 of the second pixel PXL2 can be disposed on the third insulating layer INS3.

[0267] In this implementation, in the non-emitting region NEA, at least one region of the first pixel electrode ELT1 of the first pixel PXL1 corresponding to the cutting region LCA and the region of the third insulating layer INS3 corresponding to the cutting region LCA can be removed. The first pixel electrode ELT1 of the first pixel PXL1 can be separated into a first partial electrode ELT1a and an isolation electrode ILT. The first partial electrode ELT1a can be in a floating state. The isolation electrode ILT can be electrically connected to the first dummy electrode ALE1a and the pixel circuit PXC of the first pixel PXL1 disposed in the pixel circuit layer PCL through the first contact hole CH1.

[0268] Figure 11a and Figure 11b It is schematically shown along Figure 9 A cross-sectional view of an example section taken by line II-II'.

[0269] refer to Figure 11a and Figure 11bThe first partial electrode ELT1a of the first pixel PXL1 can be electrically connected to the first dummy electrode ALE1b of the second pixel PXL2 through the third contact hole CH3 formed in the third partial electrode ELT1c. The second pixel electrode ELT2 of the second pixel PXL2 can be electrically connected to the first dummy electrode ALE1b of the second pixel PXL2 through the fourth contact hole CH4. For example, the first partial electrode ELT1a of the first pixel PXL1 can be electrically connected to the second pixel electrode ELT2 of the second pixel PXL2 through the third contact hole CH3.

[0270] refer to Figure 11a The second electrode ELT1b can be configured according to the shape of the second floating region FLA2. For example, the second electrode ELT1b can contact the second dummy electrode ALE2a of the first pixel PXL1 and the second dummy electrode ALE2b of the second pixel PXL2.

[0271] refer to Figure 11b An insulating material (not shown) may be filled in the second floating region FLA2. For example, the second partial electrode ELT1b may be disposed on the insulating material disposed in the second floating region FLA2.

[0272] Figure 12 and Figure 13 This is shown for explanation Figure 7a A schematic plan view of other examples of pixel repair methods in defective states.

[0273] refer to Figure 12 At least the first pixel electrode ELT1” of the first pixel PXL1, the second pixel electrode ELT2” of the second pixel PXL2, and the third contact hole CH3’ and the fourth contact hole CH4’ may differ from those shown in FIG11. Therefore, the same reference numerals are used for the same or corresponding components, and repeated descriptions will be omitted.

[0274] Figure 12 The process is shown to electrically connect the first partial electrode ELT1”a to the second pixel electrode ELT2 of the second pixel PXL2 adjacent to the first pixel PXL1 after performing the process of disconnecting the connection between the first pixel electrode ELT1 and ELT1” of the first pixel PXL1 and the pixel circuit PXC.

[0275] refer to Figure 12 The first pixel electrode (e.g., Figure 5a and Figure 5cThe first pixel electrodes ELT1 and ELT1”) may include a first partial electrode ELT1”a. The first partial electrode ELT1”a may extend from the first emitting region EMA1 to the non-emitting region NEA and is integral with an electrode having a protrusion that overlaps with the second dummy electrode ALE2a of the first pixel PXL1. In the example, the electrode with the protrusion may include a second partial electrode ELT1”b that protrudes from the first partial electrode ELT1”a in the first direction DR1 and overlaps with a region of the second dummy electrode ALE2a.

[0276] In an implementation, the first pixel electrode (e.g., Figure 5a The first pixel electrode (ELT1) can be separated into a first partial electrode (ELT1”a) and an isolation electrode (ILT). After the first pixel electrode (ELT1) is separated into the first partial electrode (ELT1”a) and the isolation electrode (ILT), the second partial electrode (ELT1”b) can be integrated with the first partial electrode (ELT1”a). For example, a process for forming the second partial electrode (ELT1”b) can be performed such that the first partial electrode (ELT1”a) is electrically connected to the second partial electrode (ELT1”b).

[0277] In an embodiment, the second partial electrode ELT1”b can be a repair electrode formed to electrically connect the first partial electrode ELT1”a to the second pixel electrode ELT2 of the second pixel PXL2. The second partial electrode ELT1”b can be formed using at least one of conductive ink and chemical vapor deposition (CVD) methods.

[0278] In another embodiment, the first pixel electrode (e.g., Figure 5c The first portion of the first pixel electrode ELT1” can be separated into a first part electrode ELT1”a and an isolation electrode ILT. In the example, the second part electrode ELT1”b can be an electrode constituting the first pixel electrode ELT1” and can correspond to the second portion of the first pixel electrode ELT1”. In the example, the first pixel electrode ELT1” can be set in the process of setting pixel electrodes during the manufacturing process of the display device. The first pixel electrode ELT1” can be set to overlap with the first dummy electrode ALE1a and the first light-emitting element LD1 in the first emission region EMA1, and can be set to overlap with at least one region of the first dummy electrode ALE1a and at least one region of the second dummy electrode ALE2a in the non-emission region NEA.

[0279] In this embodiment, when the first pixel electrode ELT1” of the first pixel PXL1 is formed during the manufacturing process of the display device, since the repair electrode (e.g., the second partial electrode ELT1”b) is pre-formed before the repair process of the first pixel PXL1, the step of forming the repair electrode can be omitted in the repair process of the first pixel PXL1. For example, after the first pixel electrode ELT1” is separated into the first partial electrode ELT1”a and the isolation electrode ILT, a process of forming a contact hole in the area of ​​the second partial electrode ELT1”b can be performed.

[0280] During the manufacturing process of a display device, by setting a first pixel electrode "ELT1" for the repair process of pixels in a defective state, the efficiency of the repair process of defective pixels can be improved.

[0281] In the implementation, the second pixel electrode of the second pixel PXL2 (e.g., Figure 5c The second pixel electrode ELT2”) may include a bar shape with a constant width and a shape protruding from the bar shape in one direction. In the example, the second pixel electrode ELT2” may include a third part electrode ELT2”a extending from the second emission region EMA2 to the non-emission region NEA and disposed on the first dummy electrode ALE1b, and a fourth part electrode ELT2”b extending from the third part electrode ELT2”a and overlapping at least a region of the second dummy electrode ALE2a of the first pixel PXL1.

[0282] In this embodiment, the second partial electrode ELT1”b and the fourth partial electrode ELT2”b can be configured to overlap with the second dummy electrode ALE2a. The second partial electrode ELT1”b can be configured to be spaced apart from the fourth partial electrode ELT2”b in the second direction DR2.

[0283] In the implementation, the second partial electrode ELT1”b can be electrically connected to the second dummy electrode ALE2a through the third contact hole CH3'.

[0284] In the implementation, the fourth part electrode ELT2”b can be electrically connected to the second dummy electrode ALE2a through the fourth contact hole CH4'.

[0285] In an implementation, the second part electrode ELT1”b can be electrically connected to the anode electrode of the second pixel PXL2 through the second dummy electrode ALE2a of the first pixel PXL1 and the second pixel electrode ELT2” of the second pixel PXL2.

[0286] refer to Figure 13 At least the first pixel electrode of the first pixel PXL1, the second pixel electrode of the second pixel PXL2, and the third contact hole CH3” and the fourth contact hole CH4” can be connected to Figure 12 The ones shown are different. Therefore, the same reference numerals are used for the same or corresponding components, and repeated descriptions will be omitted.

[0287] Figure 13 The process is shown to electrically connect the first partial electrode ELT1”'a to the second pixel electrode ELT2 of the second pixel PXL2 adjacent to the first pixel PXL1 after performing the process of disconnecting the connection between the first pixel electrode ELT1 of the first pixel PXL1 and the pixel circuit PXC.

[0288] refer to Figure 13 The first pixel electrode (e.g., Figure 5a The first pixel electrode (ELT1) may include a first partial electrode (ELT1”'a). The first partial electrode (ELT1”'a) may extend from the first emitting region (EMA1) to the non-emitting region (NEA) and is integral with an electrode having a protrusion overlapping with a second dummy electrode (ALE2a), a third dummy electrode (ALE3a), and a fourth dummy electrode (ALE4a) of the first pixel (PXL1). In an example, the electrode with the protrusion may include a second partial electrode (ELT1”'b) that protrudes from the first partial electrode (ELT1”'a) in the first direction (DR1) and overlaps with a region of the second dummy electrode (ALE2a), the third dummy electrode (ALE3a), and the fourth dummy electrode (ALE4a).

[0289] In an implementation, the first pixel electrode (e.g., Figure 5a The first pixel electrode ELT1 can be separated into a first partial electrode ELT1”'a and an isolation electrode ILT. After the first pixel electrode ELT1 is separated into the first partial electrode ELT1”'a and the isolation electrode ILT, the second partial electrode ELT1”'b can be integrated with the first partial electrode ELT1”'a. For example, a process for forming the second partial electrode ELT1”'b can be performed such that the first partial electrode ELT1”'a is electrically connected to the second partial electrode ELT1”'b.

[0290] In another example, during the process of setting pixel electrodes in the manufacturing process of the display device, a first pixel electrode including a first partial electrode ELT1”'a and a second partial electrode ELT1”'b can be set. The first pixel electrode including the first partial electrode ELT1”'a and the second partial electrode ELT1”'b can be set to overlap with the first dummy electrode ALE1a and the first light-emitting element LD1 in the first emission region EMA1, and can be set to overlap with at least one region of the first dummy electrode ALE1a, the second dummy electrode ALE2a, the third dummy electrode ALE3a and the fourth dummy electrode ALE4a in the non-emission region NEA.

[0291] In this embodiment, when a first pixel electrode including a first partial electrode ELT1”'a and a second partial electrode ELT1”'b is provided during the manufacturing process of the display device, since the repair electrode (e.g., the second partial electrode ELT1”'b) is pre-formed before the repair process of the first pixel PXL1, the step of forming the repair electrode can be omitted in the repair process of the first pixel PXL1. For example, after the first pixel electrode is separated into the first partial electrode ELT1”'a and the isolation electrode ILT, a process of forming a contact hole in the region of the second partial electrode ELT1”'b can be performed.

[0292] During the manufacturing process of a display device, by setting a first pixel electrode including a first partial electrode ELT1”'a and a second partial electrode ELT1”'b for the repair process of pixels in a defective state, the efficiency of the repair process of defective pixels can be improved.

[0293] In an implementation, the second pixel electrode of the second pixel PXL2 may include a first partial electrode ELT2”'a and a second partial electrode ELT2”'b. The first partial electrode ELT2”'a may extend from the second emitting region EMA2 to the non-emitting region NEA, and may be disposed on the first dummy electrode ALE1b. The second partial electrode ELT2”'b may extend from the first partial electrode ELT2”'a in the first direction DR1, and may overlap at least a region of the second dummy electrode ALE2a, the third dummy electrode ALE3a, and the fourth dummy electrode ALE4a of the first pixel PXL1.

[0294] In an embodiment, the second partial electrode ELT1”'b and the second partial electrode ELT2”'b may be configured to overlap at least a region of the second dummy electrode ALE2a, the third dummy electrode ALE3a, and the fourth dummy electrode ALE4a. The second partial electrode ELT2”'b may be configured to be spaced apart from the second partial electrode ELT2”'b in the second direction DR2.

[0295] In an embodiment, the second partial electrode ELT1”'b may include a third contact hole CH3”. The second partial electrode ELT1”'b can be electrically connected to the fourth dummy electrode ALE4a through the third contact hole CH3”.

[0296] In an embodiment, the second partial electrode ELT2”'b may include a fourth contact hole CH4”. The second partial electrode ELT2”'b may be electrically connected to the fourth dummy electrode ALE4a through the fourth contact hole CH4”.

[0297] In an implementation, the second partial electrode ELT1”'b can be electrically connected to the anode electrode of the second pixel PXL2 via the fourth dummy electrode ALE4a of the first pixel PXL1 and the second pixel electrode of the second pixel PXL2, which includes the first partial electrode ELT2”'a and the second partial electrode ELT2”'b. For pixels including pixel circuits in a defective state, the defective pixel can be repaired by using dummy electrodes to electrically connect the electrode of the defective pixel to the electrode of the adjacent pixel in a normal state. For example, by repairing the defective pixel, the light-emitting element of the pixel can be prevented from failing to emit light due to defects in the pixel circuit, thus preventing a reduction in the pixel's luminous efficiency.

[0298] By pre-arranging pixel electrodes for a repair process of pixels in a defective state during the manufacturing process of a display device, the efficiency of the repair process for defective pixels can be improved.

[0299] The above description is an example of the technical features of this disclosure, and those skilled in the art will be able to make various modifications and variations. Therefore, the embodiments of this disclosure described above can be implemented individually or in combination with each other.

[0300] Therefore, the embodiments disclosed herein are not intended to limit the technical spirit of this disclosure, but rather to describe it, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirit within the equivalent scope is included within the scope of this disclosure.

Claims

1. A display device, characterized in that, The display device includes: The first pixel includes the first emission region; The second pixel includes a second emission region spaced apart from the first emission region in a second direction; and A dike defines a non-launching area between the first launch area and the second launch area, wherein... Each of the first pixel and the second pixel includes: At least one dummy electrode is spaced apart from each other in a first direction intersecting the second direction and extends in the second direction; A light-emitting element is disposed in the emitting region between the at least one dummy electrode; A first pixel electrode is electrically connected to a first driving power supply and a first end of the light-emitting element; and The second pixel electrode is electrically connected to the second driving power supply and the second end of the light-emitting element. The first pixel electrode of the first pixel extends from the first emitting region to the non-emitting region. The first pixel electrode of the first pixel is electrically connected to one of the at least one dummy electrodes of the first pixel. The first pixel electrode of the second pixel is electrically connected to the first driving power supply, and The first pixel electrode of the second pixel is electrically connected to the dummy electrode.

2. The display device according to claim 1, characterized in that, The first pixel electrode of the first pixel is electrically connected to the first driving power supply through the first pixel electrode of the second pixel and the dummy electrode.

3. The display device according to claim 1, characterized in that, The at least one dummy electrode of the second pixel is spaced apart from the at least one dummy electrode of the first pixel in the non-emitting region in the second direction, and The at least one dummy electrode of the second pixel is not electrically connected to the at least one dummy electrode of the first pixel.

4. The display device according to claim 1, characterized in that, The first pixel electrode of the second pixel extends from the second emitting region to the non-emitting region, and The first pixel electrode of the second pixel is electrically connected to the dummy electrode through the second contact hole.

5. The display device according to claim 1, characterized in that, The at least one dummy electrode of the first pixel further includes: The first dummy electrode overlaps with the first pixel electrode of the first pixel in the planar view; and The third dummy electrode is spaced apart from the first dummy electrode in the first direction and overlaps with the second pixel electrode of the first pixel in the planar view.

6. The display device according to claim 5, characterized in that, The dummy electrode is positioned between the first dummy electrode and the third dummy electrode in the plan view.

7. The display device according to claim 5, characterized in that, The first dummy electrode is further away from the first dummy electrode in the plan view than the third dummy electrode.

8. The display device according to claim 5, characterized in that, The first pixel electrode of the first pixel includes: The first electrode portion overlaps with the first dummy electrode in the plan view; and The second electrode portion protrudes from the first electrode portion in the first direction and overlaps with at least a portion of the dummy electrode in a plan view, and The second part of the electrode is electrically connected to the dummy electrode through the first contact hole.

9. The display device according to claim 5, characterized in that, The display device further includes: An isolation electrode, spaced apart from the first pixel electrode of the first pixel in the second direction in the non-emitting region. The isolation electrode is electrically connected to the first dummy electrode through a third contact hole.

10. A display device, characterized in that, The display device includes: The first pixel includes the first emission region; The second pixel includes a second emission region spaced apart from the first emission region in a second direction; and A dike defines a non-launching area between the first launch area and the second launch area, wherein... Each of the first pixel and the second pixel includes: At least one dummy electrode is spaced apart from each other in a first direction intersecting the second direction and extends in the second direction; A light-emitting element is disposed in the emitting region between the at least one dummy electrode; A first pixel electrode is electrically connected to a first driving power supply and a first end of the light-emitting element; and The second pixel electrode is electrically connected to the second driving power supply and the second end of the light-emitting element. The first pixel electrode of the first pixel extends from the first emitting region to the non-emitting region. The first pixel electrode of the first pixel is electrically connected to one of the at least one dummy electrodes of the second pixel, and The first pixel electrode of the second pixel is electrically connected to the first driving power supply, and The first pixel electrode of the second pixel is electrically connected to the dummy electrode.

11. The display device according to claim 10, characterized in that, The at least one dummy electrode of the second pixel is spaced apart from the at least one dummy electrode of the first pixel in the non-emitting region in the second direction, and The at least one dummy electrode of the second pixel is not electrically connected to the at least one dummy electrode of the first pixel.

12. The display device according to claim 11, characterized in that, The at least one dummy electrode of the second pixel includes a first dummy electrode, a second dummy electrode, a third dummy electrode, and a fourth dummy electrode sequentially disposed in the first direction, and The dummy electrode is the first dummy electrode.

13. The display device according to claim 11, characterized in that, The at least one dummy electrode of the first pixel includes a first dummy electrode, a second dummy electrode, a third dummy electrode, and a fourth dummy electrode sequentially disposed in the first direction, and the display device further includes an isolation electrode that overlaps with the first dummy electrode in the non-emission region in the plan view and is at least partially surrounded by the first pixel electrode of the first pixel.

14. The display device according to claim 13, characterized in that, The first pixel electrode of the first pixel includes: The first part overlaps with the first dummy electrode in the plan view; and The curved portion extends from the first portion and overlaps with at least a portion of the dummy electrode in the plan view.

15. The display device according to claim 14, characterized in that, The curved portion includes: The second electrode portion protrudes from the first portion in the second direction and overlaps with the second dummy electrode in the plan view; and The third electrode overlaps at least a portion of the dummy electrode in the plan view, the dummy electrode being one of the at least one dummy electrodes of the second pixel.

16. The display device according to claim 15, characterized in that, The third electrode is electrically connected to the dummy electrode through the first contact hole.

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