RELU neuron chip circuit

Abstract

A RELU neuron chip circuit belongs to the field of chip circuits, and is characterized by comprising a vector summation circuit, a shift circuit, a subtraction circuit, a logic judgment circuit, an input port and an output port, the input ports comprise a data input port, a weight input port, a bias data input port and a data counting port; the output port comprises a data output port and a logic output port; by directly realizing the function of the neurons on the chip circuit, when a neural network system calls a certain neuron to carry out corresponding function calculation, data input and output can be directly carried out at the bottommost circuit level, so that a large amount of data cross-layer conversion time is saved. Only after the whole neural network completes one time of complete training or judgment operation, the operation result of the bottom layer circuit can be transmitted to the high layer from the bottom layer circuit in a cross-layer mode and displayed in a human eye recognizable mode. Therefore, the overall operation performance of the neural network system is improved.

Description

Technical Field

[0001] This utility model belongs to the field of chip circuits, and in particular relates to a RELU neuron chip circuit. Background Technology

[0002] In existing neural network implementations, the functions of neurons are implemented through software code. When implementing a specific neuron function in the entire system, the high-level programming language is translated by the program processing mechanism, then converted into a low-level language on the operating system platform, and then converted into machine language by the underlying translation mechanism. Finally, the machine language is run on the chip circuit to realize the neuron's operation function. After the neuron completes the corresponding calculation, the reverse process is followed, transforming the chip circuit's calculation result layer by layer upwards, ultimately into a high-level language result, which is fed back to the operating system and above, and then read by the neural network system to complete one calculation.

[0003] It is evident that with this operating mechanism, very little resource and time is spent on efficient computation during the realization of neuron functions. Instead, more computational resources and time are consumed in the process of data conversion from higher to lower levels and from lower to higher levels, resulting in extremely low operating efficiency of the entire neural network system. Summary of the Invention

[0004] The present invention aims to solve the above problems and provide a RELU neuron chip circuit that directly realizes neuron functions based on chip-level circuitry.

[0005] The RELU neuron chip circuit described in this utility model includes a vector summation circuit, a shift circuit, a subtraction circuit, a logic judgment circuit, an input port, and an output port;

[0006] The input ports include a data input port, a weight input port, a bias data input port, and a data counting port;

[0007] The output ports include data output ports and logic output ports;

[0008] The data input port, weight input port, and data counting port are all connected to the aforementioned vector summation circuit;

[0009] The vector summation circuit, shift circuit, and subtraction circuit are connected in sequence;

[0010] The aforementioned bias data input port is connected to the subtraction circuit;

[0011] The data output port is connected to the aforementioned subtraction circuit;

[0012] The logic judgment circuit is connected to the aforementioned subtraction circuit;

[0013] The logic output port is connected to the aforementioned logic judgment circuit.

[0014] The ReLU neuron chip circuit described in this invention, based on the internal circuitry at the circuit level—including vector summation circuits, shift circuits, subtraction circuits, logic judgment circuits, input ports, and output ports—directly performs neuron functional operations and data transmission between neurons, eliminating the need for high-performance CPUs and GPUs to support the neural network system. The high-level language system at the operating system level is only used for further processing of the raw data and results of the neural network system, significantly reducing data exchange between lower and higher layers and greatly minimizing the ineffective resource overhead of the entire system.

[0015] Furthermore, in the RELU neuron chip circuit of this invention, the vector summation circuit includes a vector product calculation circuit and an accumulator connected in sequence;

[0016] The aforementioned data input port and weight input port are both connected to the vector product calculation circuit;

[0017] The aforementioned data counting port is connected to the accumulator;

[0018] The accumulator is connected to the aforementioned shift circuit.

[0019] Furthermore, in the RELU neuron chip circuit of this invention, the data input port, weight input port, bias data input port, and data counting port all have a data bit width of 32 bits.

[0020] Furthermore, in the RELU neuron chip circuit of this invention, the data output port has a data bit width of 32 bits, and the logic output port has a data bit width of 1 bit.

[0021] Furthermore, in the RELU neuron chip circuit of this invention, the data input port uses a multi-beat sequential input method, which can significantly reduce the circuit area overhead and give the chip circuit of this invention good scalability.

[0022] The ReLU neuron chip circuit described in this invention implements the function of neurons directly on the chip circuit. This allows the neural network system to directly input and output data at the lowest circuit level when calling a specific neuron to perform a corresponding calculation, thereby saving a significant amount of time spent on data conversion across layers. Only after the entire neural network has completed a full training or judgment operation will the calculation result from the lower-level circuit be transmitted across layers to the higher levels and presented in a form that is recognizable to the human eye. This achieves the effect of improving the overall computational performance of the neural network system. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the RELU neuron chip circuit structure described in this utility model;

[0024] Figure 2 This is a schematic diagram of the vector summation circuit structure described in this utility model;

[0025] Figure 3 This is a schematic diagram of the RELU neuron chip circuit described in an embodiment of the present invention. Detailed Implementation

[0026] The RELU (Revised Linear Unit) neuron chip circuit of this utility model will be described in detail below with reference to the accompanying drawings and embodiments.

[0027] This embodiment discloses a RELU neuron chip circuit, such as Figure 1 As shown, the circuit includes a vector summation circuit, a shift circuit, a subtraction circuit, a logic judgment circuit, an input port, and an output port. The input port includes a data input port, a weight input port, a bias data input port, and a data counting port. The output port includes a data output port and a logic output port. The data input port, weight input port, and data counting port are all connected to the aforementioned vector summation circuit. The vector summation circuit, shift circuit, and subtraction circuit are connected sequentially. The aforementioned bias data input port is connected to the subtraction circuit. The data output port is connected to the aforementioned subtraction circuit. The logic judgment circuit is connected to the aforementioned subtraction circuit. The logic output port is connected to the aforementioned logic judgment circuit.

[0028] In the embodiments disclosed herein, such as Figure 2 As shown, the vector summation circuit includes a vector product calculation circuit and an accumulator connected in sequence; the aforementioned data input port and weight input port are both connected to the vector product calculation circuit; the aforementioned data counting port is connected to the accumulator; and the accumulator is connected to the aforementioned shift circuit.

[0029] In practical applications, the aforementioned shift circuit is constructed using a serial shift first-in-first-out (FIFO) circuit and a parallel-to-serial conversion circuit. The shift circuit receives input in parallel, writing a group of n data items at a time into the parallel-to-serial conversion circuit under clock cycle control. The parallel-to-serial conversion circuit is connected to the serial shift first-in-first-out circuit at the rear end. Under clock cycle control, one data item is fed into the serial shift first-in-first-out circuit each clock cycle. After n clock cycles, the n data items are fed into the FIFO circuit. At the output of the shift circuit, the n data items are output sequentially after n clock cycles.

[0030] The aforementioned subtraction circuit consists of a basic serial carry adder and a sign-magnitude complement converter circuit. Its operating principle is "minuend - subtrahend = minuend + the two's complement of the negative value of the subtrahend". One input of the serial carry adder serves as the input of the minuend, which is directly input into the adder. The subtrahend is input to the sign-magnitude complement converter circuit, which converts the subtrahend into its two's complement before sending the complement to the other end of the adder.

[0031] The aforementioned logic judgment circuit is a non-zero value judgment circuit, implemented by an n-bit high-fan-in OR gate.

[0032] In this embodiment of the disclosure, the input and output data bit width of the ReLU neuron chip circuit is defined as 32 bits. For example... Figure 3 As shown, each neuron has a data input port DATAIN and a corresponding weight input port WIN, with all ports having a data width of 32 bits. A 32-bit bias data input port and a data counter port indicating the number of input data points are also provided, both with a data width of 32 bits. The data output port is a 32-bit port, and there is also a 1-bit logic output port.

[0033] In practical applications, the input data can be any number of sets, and the number of data is input by the data counting port LNGTH. In this embodiment, the input clock signal clk controls the sequential input of data into the neurons for vector multiplication calculation.

[0034] In this embodiment of the disclosure, during data processing, the data vector input through the data input port and the weight input port is multiplied with the corresponding weight vector, and then summed with the data input through the data counting port. Then, the data is shifted 32 bits to the right through a shift circuit to restore the bit width of the data to 32 bits. Finally, the bias value input through the bias data input port BIAS is subtracted through a subtraction circuit to obtain the calculation result of the RELU neuron.

[0035] The calculation result is then output through the 32-bit data output port DATAOUT. At the same time, the logic judgment circuit judges whether the output data is greater than 0. If the output data is greater than 0, 1 will be output at the logic output port logiout, otherwise 0 will be output.

[0036] When the circuit encounters abnormal data or fails to converge, the external control circuit can pull down the reset signal rst_n to reset the entire circuit to its initial state.

[0037] The neuron chip circuit described in this embodiment has a 32-bit input and output data bit width. The multi-beat sequential input method for vector data significantly reduces circuit area overhead and provides good scalability. Through logic decision circuits and logic output ports, the neural network system composed of these neurons can not only perform regression functions but also clustering functions simultaneously.

[0038] The neuron chip circuit described in this embodiment can directly perform neuron function calculations and transmit data between neurons directly through the circuit interface based on the internal circuitry of the chip. It does not require a high-performance GPU to perform multi-dimensional array calculations, thereby avoiding the problem of having to use a high-computing GPU and effectively reducing the implementation and operating costs of the system.

Claims

1. A RELU neuron chip circuit, characterized by: It includes vector summation circuits, shift circuits, subtraction circuits, logic judgment circuits, input ports, and output ports; The input ports include a data input port, a weight input port, a bias data input port, and a data counting port; The output ports include data output ports and logic output ports; The data input port, weight input port, and data counting port are all connected to the aforementioned vector summation circuit; The vector summation circuit, shift circuit, and subtraction circuit are connected in sequence; The aforementioned bias data input port is connected to the subtraction circuit; The data output port is connected to the aforementioned subtraction circuit; The logic judgment circuit is connected to the aforementioned subtraction circuit; The logic output port is connected to the aforementioned logic judgment circuit.

2. The RELU neuron chip circuit according to claim 1, wherein: The vector summation circuit includes a vector product calculation circuit and an accumulator connected in sequence; The aforementioned data input port and weight input port are both connected to the vector product calculation circuit; The aforementioned data counting port is connected to the accumulator; The accumulator is connected to the aforementioned shift circuit.

3. The RELU neuron chip circuit according to claim 1 or 2, characterized in that: The data input port, weight input port, bias data input port, and data counting port all have a data bit width of 32 bits.

4. The RELU neuron chip circuit of claim 3, wherein: The data output port has a data width of 32 bits; the logic output port has a data width of 1 bit.

5. The RELU neuron chip circuit of claim 4, wherein: The data input port uses a multi-beat sequential input method.

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