Circuit for realizing line voltage protection

Abstract

The utility model relates to the technical field of protection circuits, in particular to a circuit for realizing line voltage protection. During normal power-on, the comparator CMP2 outputs a logic high level, the detection comparator CMP1 for detecting the line voltage is immediately started, when it is detected that the negative end voltage of the comparator CMP1 is lower than 1.25 V, the comparator CMP1 outputs the logic high level and controls the AND gate to output the logic high level, then the control unit works normally, and the power tube NPN1 is controlled to normally control energy exchange of the transformer T1; and in a normal power-on working period, if the line voltage suddenly rises and exceeds the VREF1, the comparator CMP1 outputs a logic low level, the AND gate is controlled to output the logic low level, the control unit outputs a high resistance state, the power tube NPN1 is not controlled, and the transmission energy of the transformer is zero, so that the line voltage protection is realized.

Description

Technical Field

[0001] This utility model relates to the field of protection circuit technology, specifically a circuit for implementing line voltage protection. Background Technology

[0002] The rapid development of smartphones has created a huge demand for compatible chargers. However, in the Indian market, the power grid is extremely poor and unstable, often exceeding 280V. Operating under such high line voltage conditions can easily damage chargers and create safety hazards. To address this issue of chip damage due to excessive line voltage in Indian exports, the following two solutions are currently available:

[0003] Firstly, by sampling the voltage of the secondary winding and calculating the line voltage of the primary winding based on the turns ratio of the secondary winding and the primary winding, the voltage of the secondary winding is sampled and then converted to the line voltage of the primary winding. The voltage of the secondary winding is sampled to the DEM pin of the ACDC control chip through the pull-up resistor connected to the secondary winding. The ACDC control chip detects the current flowing through the DEM pin when the switch is turned on. If the current exceeds the internal threshold current, it is determined to be line voltage protection. In this method, the resistor connected to the DEM pin will affect the size of the system line compensation, and the adjustment range is very narrow. Moreover, the primary winding conduction time is different under different output loads, which causes the line voltage detection to be inconsistent under no-load and full-load conditions, with a difference of 20V-30V. The error is large, and it often fails to provide overvoltage protection under no-load conditions.

[0004] Secondly, the line voltage is directly detected by voltage divider. After the line voltage overvoltage protection is detected, the GND of AC-CDC is disconnected from the rectified GND1, thus breaking the current loop. When the line voltage is normal, the GND of AC-CDC is connected to the rectified GND1 through the channel NMOS, and the current loop is normal. This method has the disadvantages of complex design and very high cost, resulting in extremely low cost-effectiveness. Utility Model Content

[0005] In view of this, the purpose of this utility model is to provide a circuit for line voltage protection, so as to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the technical solution adopted by this utility model is as follows:

[0007] A circuit for implementing line voltage protection includes a transformer T1, a control unit, a second capacitor C2, a power transistor NPN1, a comparator CMP1, a comparator CMP2, an AND gate AND1, and a switching transistor N2.

[0008] The transformer T1 is electrically connected to the collector of the power transistor NPN1, the base of the power transistor NPN1 is electrically connected to the control unit, the emitter of the power transistor NPN1 is electrically connected to the drain of the switching transistor N2, one end of the second capacitor C2, and the positive input of the comparator CMP2, respectively, the gate of the switching transistor N2 is electrically connected to the control unit, and the source of the switching transistor N2 and the other end of the second capacitor C2 are both grounded. The inverting input of the comparator CMP2 is externally connected to a reference voltage VREF1, and the output of the comparator CMP2 is electrically connected to the control unit and one input of the AND gate AND1, respectively. The inverting input of the comparator CMP1 is externally connected to a voltage VIN, the positive input of the comparator CMP1 is externally connected to a reference voltage VREF2, the output of the comparator CMP1 is electrically connected to the other input of the AND gate AND1, and the output of the AND gate AND1 is electrically connected to the control unit.

[0009] Preferably, it also includes a diode D2, the anode of which is electrically connected to the emitter of the power transistor NPN1 and the drain of the switching transistor N2, and the cathode of which is electrically connected to one end of the second capacitor C2 and the positive input terminal of the comparator CMP2.

[0010] Preferably, it further includes a voltage regulator unit VZ, the negative terminal of which is electrically connected to the base of the control unit and the power transistor NPN1, and the positive terminal of which is grounded.

[0011] Preferably, it also includes resistors R1 and R2; one end of resistor R1 is connected to an external voltage VIN, the other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of comparator CMP1, and the other end of resistor R2 is grounded.

[0012] Preferably, it also includes a third capacitor C3; one end of the third capacitor C3 is electrically connected to the other end of resistor R1, one end of resistor R2 and the inverting input terminal of comparator CMP1 respectively, and the other end of the third capacitor C3 is grounded.

[0013] Preferably, it also includes a starting resistor RS, a first capacitor C1, a diode D1, and a resistor R3; the transformer T1 includes a primary winding LP and a secondary winding LS;

[0014] One end of the primary winding LP is electrically connected to one end of the starting resistor RS and the line voltage VIN, and the other end of the primary winding LP is electrically connected to the collector of the power transistor NPN1; the other end of the starting resistor RS is electrically connected to the base of the power transistor NPN1.

[0015] One end of the secondary winding LS is electrically connected to the positive terminal of diode D1, and the negative terminal of diode D1 is electrically connected to one end of the first capacitor C1, one end of resistor R3 and the positive output terminal, respectively; the other end of the secondary winding LS is electrically connected to the other end of the first capacitor C1, the other end of resistor R3 and the negative output terminal, respectively.

[0016] The beneficial effects of this utility model are:

[0017] This utility model provides a circuit for line voltage protection, including a transformer T1, a control unit, a second capacitor C2, a power transistor NPN1, comparators CMP1 and CMP2, an AND gate AND1, and a switching transistor N2. Through their electrical connections, line voltage protection is achieved. Specifically, during normal power-on, comparator CMP2 outputs a logic high level. The control unit generates a reference voltage VREF2 (1.25V), the bias current required by comparator CMP1, and the reference voltage VREF1 (1.25V). Immediately, the line voltage detection comparator CMP1 is activated. When the voltage at the negative terminal of comparator CMP1 is detected to be lower than 1.25V, the comparator... CMP1 outputs a high logic level, and the control AND gate outputs a high logic level, thus enabling the control unit to operate normally and control the power transistor NPN1, thereby controlling the energy exchange of the transformer T1. Furthermore, during normal power-on operation, if the line voltage suddenly rises and exceeds VREF1, comparator CMP1 outputs a low logic level, the control AND gate outputs a low logic level, the control unit outputs a high impedance state, and the power transistor NPN1 is not controlled. The transformer transmits zero energy, thus achieving line voltage protection and shutting down all bias consumption of the control unit, retaining only the generation of reference voltages VREF2 and VREF1, and the bias current of comparators CMP1 and CMP2, consuming a current of 100μA. This technical solution avoids the problem of no-load overvoltage protection failure, and is simple in design and low in cost. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of a circuit for implementing line voltage protection according to this utility model;

[0019] Figure 2 This is the circuit schematic of the comparator CMP1 of this utility model. Detailed Implementation

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments:

[0021] like Figures 1 to 2 The present invention provides a circuit for implementing line voltage protection, including a transformer T1, a control unit, a second capacitor C2, a power transistor NPN1, a comparator CMP1, a comparator CMP2, an AND gate AND1, and a switching transistor N2.

[0022] The transformer T1 is electrically connected to the collector of the power transistor NPN1, the base of the power transistor NPN1 is electrically connected to the control unit, the emitter of the power transistor NPN1 is electrically connected to the drain of the switching transistor N2, one end of the second capacitor C2, and the positive input of the comparator CMP2, respectively, the gate of the switching transistor N2 is electrically connected to the control unit, and the source of the switching transistor N2 and the other end of the second capacitor C2 are both grounded. The inverting input of the comparator CMP2 is externally connected to a reference voltage VREF1, and the output of the comparator CMP2 is electrically connected to the control unit and one input of the AND gate AND1, respectively. The inverting input of the comparator CMP1 is externally connected to a voltage VIN, the positive input of the comparator CMP1 is externally connected to a reference voltage VREF2, the output of the comparator CMP1 is electrically connected to the other input of the AND gate AND1, and the output of the AND gate AND1 is electrically connected to the control unit.

[0023] The beneficial effects of this utility model are:

[0024] This utility model provides a circuit for line voltage protection, including a transformer T1, a control unit, a second capacitor C2, a power transistor NPN1, comparators CMP1 and CMP2, an AND gate AND1, and a switching transistor N2. Through their electrical connections, line voltage protection is achieved. Specifically, during normal power-on, comparator CMP2 outputs a logic high level. The control unit generates a reference voltage VREF2 (1.25V), the bias current required by comparator CMP1, and the reference voltage VREF1 (1.25V). Immediately, the line voltage detection comparator CMP1 is activated. When the voltage at the negative terminal of comparator CMP1 is detected to be lower than 1.25V, the comparator... CMP1 outputs a high logic level, and the control AND gate outputs a high logic level, thus enabling the control unit to operate normally and control the power transistor NPN1, thereby controlling the energy exchange of the transformer T1. Furthermore, during normal power-on operation, if the line voltage suddenly rises and exceeds VREF1, comparator CMP1 outputs a low logic level, the control AND gate outputs a low logic level, the control unit outputs a high impedance state, and the power transistor NPN1 is not controlled. The transformer transmits zero energy, thus achieving line voltage protection and shutting down all bias consumption of the control unit, retaining only the generation of reference voltages VREF2 and VREF1, and the bias current of comparators CMP1 and CMP2, consuming a current of 100μA. This technical solution avoids the problem of no-load overvoltage protection failure, and is simple in design and low in cost.

[0025] Preferably, it also includes a diode D2, the anode of which is electrically connected to the emitter of the power transistor NPN1 and the drain of the switching transistor N2, and the cathode of which is electrically connected to one end of the second capacitor C2 and the positive input terminal of the comparator CMP2.

[0026] As described above, by setting diode D2 and using the specific connection method described above, it is ensured that the current can only flow in the forward direction, protecting the circuit from the influence of reverse current.

[0027] Preferably, it further includes a voltage regulator unit VZ, the negative terminal of which is electrically connected to the base of the control unit and the power transistor NPN1, and the positive terminal of which is grounded.

[0028] As described above, the voltage regulator unit VZ is a Zener diode. Through the specific connection method described above, it mainly serves to clamp the base potential of the power transistor NPN1.

[0029] Preferably, it also includes resistors R1 and R2; one end of resistor R1 is connected to an external voltage VIN, the other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of comparator CMP1, and the other end of resistor R2 is grounded.

[0030] As described above, through the specific connection method, resistors R1 and R2 form a voltage divider circuit, so that when the line voltage VIN exceeds VREF2*(R2+R1) / R2, comparator CMP1 outputs a logic low level.

[0031] Preferably, it also includes a third capacitor C3; one end of the third capacitor C3 is electrically connected to the other end of resistor R1, one end of resistor R2 and the inverting input terminal of comparator CMP1 respectively, and the other end of the third capacitor C3 is grounded.

[0032] As can be seen from the above description, the third capacitor C3 serves to store energy and stabilize voltage.

[0033] Preferably, it also includes a starting resistor RS, a first capacitor C1, a diode D1, and a resistor R3; the transformer T1 includes a primary winding LP and a secondary winding LS;

[0034] One end of the primary winding LP is electrically connected to one end of the starting resistor RS and the line voltage VIN, and the other end of the primary winding LP is electrically connected to the collector of the power transistor NPN1; the other end of the starting resistor RS is electrically connected to the base of the power transistor NPN1.

[0035] One end of the secondary winding LS is electrically connected to the positive terminal of diode D1, and the negative terminal of diode D1 is electrically connected to one end of the first capacitor C1, one end of resistor R3 and the positive output terminal, respectively; the other end of the secondary winding LS is electrically connected to the other end of the first capacitor C1, the other end of resistor R3 and the negative output terminal, respectively.

[0036] As can be seen from the above description, the external circuit configuration of transformer T1 is achieved through the specific connection method described above.

[0037] Example 1

[0038] like Figures 1 to 2 This utility model provides a circuit for implementing line voltage protection, including a transformer T1, a control unit, a second capacitor C2, a third capacitor C3, a power transistor NPN1, a comparator CMP1, a comparator CMP2, an AND gate AND1, a switching transistor N2, a diode D2, a voltage regulator unit VZ, resistors R1 and R2, a starting resistor RS, a first capacitor C1, a diode D1, and a resistor R3; the transformer T1 includes a primary winding LP and a secondary winding LS;

[0039] The transformer T1 is electrically connected to the collector of the power transistor NPN1, the base of the power transistor NPN1 is electrically connected to the control unit, the emitter of the power transistor NPN1 is electrically connected to the drain of the switching transistor N2, one end of the second capacitor C2, and the positive input of the comparator CMP2, respectively, the gate of the switching transistor N2 is electrically connected to the control unit, and the source of the switching transistor N2 and the other end of the second capacitor C2 are both grounded. The inverting input of the comparator CMP2 is externally connected to a reference voltage VREF1, and the output of the comparator CMP2 is electrically connected to the control unit and one input of the AND gate AND1, respectively. The inverting input of the comparator CMP1 is externally connected to a voltage VIN, the positive input of the comparator CMP1 is externally connected to a reference voltage VREF2, the output of the comparator CMP1 is electrically connected to the other input of the AND gate AND1, and the output of the AND gate AND1 is electrically connected to the control unit.

[0040] In this embodiment, the control unit is an AC-DC control unit. The output terminal of the control unit controls the conduction frequency and output current of the power transistor NPN1 and the switching transistor N2. The control unit also generates reference voltages VREF1 and VREF2. The power transistor NPN1 is an AC-DC power transistor, which normally conducts and is cut off. The control transformer T1 transfers the line voltage VIN energy to the output load R3 through the transformer T1.

[0041] The anode of diode D2 is electrically connected to the emitter of power transistor NPN1 and the drain of switching transistor N2, respectively. The cathode of diode D2 is electrically connected to one end of the second capacitor C2 and the positive input terminal of comparator CMP2, respectively. By setting up diode D2 and using the above-described connection method, it is ensured that the current can only flow in the forward direction, protecting the circuit from the influence of reverse current.

[0042] One end of the second capacitor C2 is also connected to the VCC terminal of the control unit to supply power to the control unit.

[0043] The negative terminal of the voltage regulator unit VZ is electrically connected to both the control unit and the base of the power transistor NPN1, while the positive terminal of VZ is grounded. The voltage regulator unit VZ is a Zener diode, and through the specific connection method described above, it primarily clamps the base potential of the power transistor NPN1. In this embodiment, the regulated voltage is 5.6V, but it is not limited to 5.6V; the Zener diode can also be a voltage regulator circuit, primarily clamping the base potential of NPN1.

[0044] One end of resistor R1 is connected to an external line voltage VIN. The other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of comparator CMP1. The other end of resistor R2 is grounded. Through this specific connection method, resistors R1 and R2 form a voltage divider circuit, causing comparator CMP1 to output a logic low level when the line voltage VIN exceeds VREF2*(R2+R1) / R2.

[0045] One end of the third capacitor C3 is electrically connected to the other end of resistor R1, one end of resistor R2, and the inverting input of comparator CMP1, respectively, and the other end of the third capacitor C3 is grounded. The third capacitor C3 is provided to store energy and stabilize voltage.

[0046] One end of the primary winding LP is electrically connected to one end of the starting resistor RS and the line voltage VIN, and the other end of the primary winding LP is electrically connected to the collector of the power transistor NPN1; the other end of the starting resistor RS is electrically connected to the base of the power transistor NPN1; one end of the secondary winding LS is electrically connected to the anode of the diode D1, and the cathode of the diode D1 is electrically connected to one end of the first capacitor C1, one end of the resistor R3, and the positive output terminal; the other end of the secondary winding LS is electrically connected to the other end of the first capacitor C1, the other end of the resistor R3, and the negative output terminal. Through the above specific connection method, the peripheral circuit configuration of the transformer T1 is realized.

[0047] In this embodiment, comparator CMP1 and comparator CMP2 have the same structure. For example... Figure 2 As shown, taking comparator CMP1 as an example, the following structure is introduced: The specific structure includes: P1, P2, P3, P4, N2, N3 and N4;

[0048] The gate of P1 is electrically connected to the gate of P4, and the source of P2 is electrically connected to the source of P3 and the drain of P1. The gate of P2 is connected to the inverting input of comparator CMP1, the gate of P3 is connected to the non-inverting input of comparator CMP1, the drain of P2 is connected to the gate and drain of N2, the drain of P3 is connected to the drain of N3, the gate of N4 is electrically connected to the drain of N3, and the drain of N4 is connected to the drain of P4 and then connected to the output of the comparator.

[0049] Upon power-up, the Zener diode clamps the base of the power transistor NPN1 to 5.6V, enabling high-voltage LDO power supply. At this time, through the power transistor NPN1 and diode D2, the voltage of the second capacitor C2 is charged to 5.6 - 0.6 - 0.6 = 4.4V. The second capacitor C2 supplies power to the VCC pin of the control unit, VREF1 = 4V. When the voltage of the second capacitor C2 exceeds 4V, the comparator CMP2 outputs a logic high level. The control unit generates a reference VREF2 = 1.25V, the bias current required by the comparator CMP1, and VREF1 = 1.25V, immediately activating the line voltage detection comparator CMP1. When the voltage at the negative terminal of comparator CMP1 exceeds 1.25V, i.e., the line voltage VIN exceeds VREF2*(R2+R1) / R2, the comparator CMP1 outputs a logic low level, controlling the AND gate to output a logic low level. This cuts off the control unit's startup timing, and the control unit outputs a high-impedance state, not controlling the power transistor NPN1. The transformer transmits zero energy, achieving line voltage protection.

[0050] The line voltage protection solution using this method requires only two voltage divider resistors for line voltage detection. It achieves line voltage protection without delay, has a simple external system, high detection accuracy, and the overall system loss after protection is only 30mW when the input is 220V, which is a very low protection loss.

[0051] This utility model has been described with reference to the above-described embodiments and accompanying drawings. However, the above embodiments are merely examples for implementing this utility model. It must be noted that the disclosed embodiments do not limit the scope of this utility model. On the contrary, modifications and equivalent provisions included in the spirit and scope of the claims are all included within the scope of this utility model.

Claims

1. A circuit for implementing line voltage protection, characterized by: It includes transformer T1, control unit, second capacitor C2, power transistor NPN1, comparator CMP1, comparator CMP2, AND gate AND1, and switching transistor N2; The transformer T1 is electrically connected to the collector of the power transistor NPN1, the base of the power transistor NPN1 is electrically connected to the control unit, the emitter of the power transistor NPN1 is electrically connected to the drain of the switching transistor N2, one end of the second capacitor C2, and the positive input of the comparator CMP2, respectively, the gate of the switching transistor N2 is electrically connected to the control unit, and the source of the switching transistor N2 and the other end of the second capacitor C2 are both grounded. The inverting input of the comparator CMP2 is externally connected to a reference voltage VREF1, and the output of the comparator CMP2 is electrically connected to the control unit and one input of the AND gate AND1, respectively. The inverting input of the comparator CMP1 is externally connected to a voltage VIN, the positive input of the comparator CMP1 is externally connected to a reference voltage VREF2, the output of the comparator CMP1 is electrically connected to the other input of the AND gate AND1, and the output of the AND gate AND1 is electrically connected to the control unit.

2. The circuit for implementing line voltage protection according to claim 1, wherein: It also includes a diode D2, the anode of which is electrically connected to the emitter of the power transistor NPN1 and the drain of the switching transistor N2, and the cathode of which is electrically connected to one end of the second capacitor C2 and the positive input terminal of the comparator CMP2.

3. The circuit for implementing line voltage protection according to claim 1, wherein: It also includes a voltage regulator unit VZ, the negative terminal of which is electrically connected to the base of the control unit and the power transistor NPN1, and the positive terminal of which is grounded.

4. The circuit for implementing line voltage protection according to claim 1, wherein: It also includes resistors R1 and R2; one end of resistor R1 is connected to an external voltage VIN, the other end of resistor R1 is electrically connected to one end of resistor R2 and the inverting input of comparator CMP1, and the other end of resistor R2 is grounded.

5. The circuit for implementing line voltage protection according to claim 4, wherein: It also includes a third capacitor C3; one end of the third capacitor C3 is electrically connected to the other end of resistor R1, one end of resistor R2 and the inverting input of comparator CMP1 respectively, and the other end of the third capacitor C3 is grounded.

6. The circuit for implementing line voltage protection according to claim 1, wherein: It also includes a starting resistor RS, a first capacitor C1, a diode D1, and a resistor R3; the transformer T1 includes a primary winding LP and a secondary winding LS; One end of the primary winding LP is electrically connected to one end of the starting resistor RS and the line voltage VIN, and the other end of the primary winding LP is electrically connected to the collector of the power transistor NPN1; the other end of the starting resistor RS is electrically connected to the base of the power transistor NPN1. One end of the secondary winding LS is electrically connected to the positive terminal of diode D1, and the negative terminal of diode D1 is electrically connected to one end of the first capacitor C1, one end of resistor R3 and the positive output terminal, respectively; the other end of the secondary winding LS is electrically connected to the other end of the first capacitor C1, the other end of resistor R3 and the negative output terminal, respectively.

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